Production-level model enhancements: fix strategy selection bug, add retry/health/request_id/validation, rewrite tests with pytest assertions, harden cache

Add reset coverage, FIFO occupancy, IER×interrupt cross, error×LSR correlation

Fix field-level covergroup bit slicing for single-bit fields

Fix APB sequences: remove hardcoded 8'hFF illegal addrs (compute from reg map), remove magic control registers from wait_state/pslverr, use spec-driven register access

Fix 5 compile blockers: _ua Jinja2 literals, missing UART aliases, seq_lib reg_model, m_sequencer.vif -> base_seq vif, sequencer vif

Fix virtual_sequencer: use intf.name for InterfaceDef objects (Pydantic BaseModel not Mapping)

Fix naming consistency: replace hardcoded uart_/UART_ prefixes with {{ spec.design_name }}, derive virtual_sequencer handles from spec.interfaces

Fix V2 model slow init: move CoveragePredictor training to lazy (first predict_coverage), reduce RF 450->150 / GBR 375->120 trees, n_samples 50000->1000

Fix 3 test failures, add protocol-specific sequences (I2C/SPI/APB/AXI/UART), created sequencer.sv.j2 + top_tb.sv.j2

Fix V2 __init__: rename name_or_config -> name to accept name= kwarg from pipeline

Fix 6+7+8: add RAL access/memwalk/aliasing seqs, regression suites, fix virtual sequencer bus_seqr connection

Fix 1+2: spec-driven sequences — DLAB uses get_reg_by_offset(), UART sequences/constants conditional on register existence

Fix ML test failures: add get_state_stats(), get_recommendations(), get_common_error_patterns() aliases

Fix TEMPLATE_MAP: remove broken sequencer/reg_block/adapter refs, add rtl/ subdir

Fix missing agent subdirectory in template output dirs

Address review: register metadata engine, coverage wiring, virtual seqr fix, Xcelium wrapper, generic RAL access

Fix DLAB handling: use get_reg_by_name/get_reg_by_offset instead of hardcoded reg names

Add virtual sequencer, callbacks, factory overrides, enhanced RAL seqs, Makefile

Add assertion generator, protocol checker, cross_baud_stop covearge; wire assertions template

Fix DLAB incomplete code bug; replace hardcoded 3'hX with register address constants

Fix None access in dashboard: reg.access can be None

Fix dashboard address format: coerce reg.address to int for 02X

Fix: add width→bits alias to FieldDef for RTL parser compat

Add DesignSpec.model_rebuild() for Pydantic v2 forward refs

Fix FieldDef missing after bad edit; add Dashboard iframe to FileViewer

Fix Pydantic validation: coerce int→str for reset/reset_value, str→int for width

Phase 3: IP-XACT, CI/CD, VCS/Questa wrappers, rich dashboard

Fix UART-specific bleed in templates: rename uart_random_regs_seq, uart_write_reg/read_reg to protocol-agnostic names, guard remaining UART code

Add 5 industry improvements: pruning, coverage, hooks, metrics, timing

Fix RL learner crash: max() empty sequence on uninitialized Q2

Fix 5 test architecture issues from code review

Add DLAB register handling, functional coverage covergroups, SVA assertions

Fix disable fork bug, RAL type mismatch, driver serial injection, interrupt timeout, error seq get_response, RAL seq library removal, hw_rst timeout guard

Fix 12 test-layer issues from code review

Phase 4 comprehensive audit: fix 29 bugs across 7 templates

Fix string->sformatf, if-fatal assertions, RO addr filtering, unique obj names, cfg DB guard, configurable timeout

Fix register address mapping + read-only guards + uart_random_seq + coverage

Fix: SequenceDef unhashable type error — use attr access instead of dict indexing

Phase 3: Compile correctness + RAL consistency + test mapping + quality scoring + auto-fix suggestions

Fix: initialize sim_result before use in HTML report

Fix: add missing 'import json' in pipeline.py

Fix: add missing 'import os' in pipeline.py

Phase 2: AI quality scoring, sequence library, virtual sequences, coverage crosses, scoreboard integration

Add cross-file validator+spec coverage score; fix stray brace+hardcoded widths in sequence template; enhance sequence_item

Enhance sequence_item template: field automation, typed error injection, do_print, dynamic widths, unsigned delay

Fix Jinja2 __setitem__ hack on int objects in all 4 templates; compute addr_bits/data_width inline via map|max filters

Fix Jinja2 brace conflict in coverage_collector.sv.j2: use SV '1 literal instead of {N{1'b1}}"

Phase 1: spec-driven templates + SV checker + quality score + ZIP export

Accept width as alias for bits in FieldDef

ML model improvements: coverage predictor ensemble, coverage-driven hybrid generation, coverage RL reward shaping, pipeline integration