Commit History

Production-level model enhancements: fix strategy selection bug, add retry/health/request_id/validation, rewrite tests with pytest assertions, harden cache
6e4b4a4

Sai Kumar Taraka commited on

Add reset coverage, FIFO occupancy, IER×interrupt cross, error×LSR correlation
2cef8a9

Sai Kumar Taraka commited on

Fix field-level covergroup bit slicing for single-bit fields
5ea4979

Sai Kumar Taraka commited on

Fix APB sequences: remove hardcoded 8'hFF illegal addrs (compute from reg map), remove magic control registers from wait_state/pslverr, use spec-driven register access
215571a

Sai Kumar Taraka commited on

Fix 5 compile blockers: _ua Jinja2 literals, missing UART aliases, seq_lib reg_model, m_sequencer.vif -> base_seq vif, sequencer vif
e55c761

Sai Kumar Taraka commited on

Fix virtual_sequencer: use intf.name for InterfaceDef objects (Pydantic BaseModel not Mapping)
9024817

Sai Kumar Taraka commited on

Fix naming consistency: replace hardcoded uart_/UART_ prefixes with {{ spec.design_name }}, derive virtual_sequencer handles from spec.interfaces
2bbcdc2

Sai Kumar Taraka commited on

Fix V2 model slow init: move CoveragePredictor training to lazy (first predict_coverage), reduce RF 450->150 / GBR 375->120 trees, n_samples 50000->1000
cbcfe7a

Sai Kumar Taraka commited on

Fix 3 test failures, add protocol-specific sequences (I2C/SPI/APB/AXI/UART), created sequencer.sv.j2 + top_tb.sv.j2
f745608

Sai Kumar Taraka commited on

Fix V2 __init__: rename name_or_config -> name to accept name= kwarg from pipeline
4ab796c

Sai Kumar Taraka commited on

Fix 6+7+8: add RAL access/memwalk/aliasing seqs, regression suites, fix virtual sequencer bus_seqr connection
020f122

Sai Kumar Taraka commited on

Fix 1+2: spec-driven sequences — DLAB uses get_reg_by_offset(), UART sequences/constants conditional on register existence
4f15678

Sai Kumar Taraka commited on

Fix ML test failures: add get_state_stats(), get_recommendations(), get_common_error_patterns() aliases
63d6295

Sai Kumar Taraka commited on

Fix TEMPLATE_MAP: remove broken sequencer/reg_block/adapter refs, add rtl/ subdir
b432989

Sai Kumar Taraka commited on

Fix missing agent subdirectory in template output dirs
d3f576c

Sai Kumar Taraka commited on

Address review: register metadata engine, coverage wiring, virtual seqr fix, Xcelium wrapper, generic RAL access
7ee417c

Sai Kumar Taraka commited on

Fix DLAB handling: use get_reg_by_name/get_reg_by_offset instead of hardcoded reg names
ea3135d

Sai Kumar Taraka commited on

Add virtual sequencer, callbacks, factory overrides, enhanced RAL seqs, Makefile
68e6ea1

Sai Kumar Taraka commited on

Add assertion generator, protocol checker, cross_baud_stop covearge; wire assertions template
1207d35

Sai Kumar Taraka commited on

Fix DLAB incomplete code bug; replace hardcoded 3'hX with register address constants
93cef85

Sai Kumar Taraka commited on

Fix None access in dashboard: reg.access can be None
62e7bb5

Sai Kumar Taraka commited on

Fix dashboard address format: coerce reg.address to int for 02X
9d94437

Sai Kumar Taraka commited on

Fix: add width→bits alias to FieldDef for RTL parser compat
9094d67

Sai Kumar Taraka commited on

Add DesignSpec.model_rebuild() for Pydantic v2 forward refs
6e42776

Sai Kumar Taraka commited on

Fix FieldDef missing after bad edit; add Dashboard iframe to FileViewer
2b1ea51

Sai Kumar Taraka commited on

Fix Pydantic validation: coerce int→str for reset/reset_value, str→int for width
3452708

Sai Kumar Taraka commited on

Phase 3: IP-XACT, CI/CD, VCS/Questa wrappers, rich dashboard
06c49cc

Sai Kumar Taraka commited on

Fix UART-specific bleed in templates: rename uart_random_regs_seq, uart_write_reg/read_reg to protocol-agnostic names, guard remaining UART code
c3e3d8b

Sai Kumar Taraka commited on

Add 5 industry improvements: pruning, coverage, hooks, metrics, timing
fd8d560

Sai Kumar Taraka commited on

Fix RL learner crash: max() empty sequence on uninitialized Q2
a8e8fbd

Sai Kumar Taraka commited on

Fix 5 test architecture issues from code review
2e6a0df

Sai Kumar Taraka commited on

Add DLAB register handling, functional coverage covergroups, SVA assertions
397f5c8

Sai Kumar Taraka commited on

Fix disable fork bug, RAL type mismatch, driver serial injection, interrupt timeout, error seq get_response, RAL seq library removal, hw_rst timeout guard
ce577cd

Sai Kumar Taraka commited on

Fix 12 test-layer issues from code review
81ded74

Sai Kumar Taraka commited on

Phase 4 comprehensive audit: fix 29 bugs across 7 templates
a94548e

Sai Kumar Taraka commited on

Fix string->sformatf, if-fatal assertions, RO addr filtering, unique obj names, cfg DB guard, configurable timeout
90eee50

Sai Kumar Taraka commited on

Fix register address mapping + read-only guards + uart_random_seq + coverage
a565f54

Sai Kumar Taraka commited on

Fix: SequenceDef unhashable type error — use attr access instead of dict indexing
21a44ca

Sai Kumar Taraka commited on

Phase 3: Compile correctness + RAL consistency + test mapping + quality scoring + auto-fix suggestions
ebd4976

Sai Kumar Taraka commited on

Fix: initialize sim_result before use in HTML report
3a6984c

Sai Kumar Taraka commited on

Fix: add missing 'import json' in pipeline.py
aa93eaa

Sai Kumar Taraka commited on

Fix: add missing 'import os' in pipeline.py
78f6df0

Sai Kumar Taraka commited on

Phase 2: AI quality scoring, sequence library, virtual sequences, coverage crosses, scoreboard integration
0a05b6f

Sai Kumar Taraka commited on

Add cross-file validator+spec coverage score; fix stray brace+hardcoded widths in sequence template; enhance sequence_item
c6829f8

Sai Kumar Taraka commited on

Enhance sequence_item template: field automation, typed error injection, do_print, dynamic widths, unsigned delay
3380d4f

Sai Kumar Taraka commited on

Fix Jinja2 __setitem__ hack on int objects in all 4 templates; compute addr_bits/data_width inline via map|max filters
34dbe70

Sai Kumar Taraka commited on

Fix Jinja2 brace conflict in coverage_collector.sv.j2: use SV '1 literal instead of {N{1'b1}}"
e8a1e3c

Sai Kumar Taraka commited on

Phase 1: spec-driven templates + SV checker + quality score + ZIP export
565ba56

Sai Kumar Taraka commited on

Accept width as alias for bits in FieldDef
b8aa00f

Sai Kumar Taraka commited on

ML model improvements: coverage predictor ensemble, coverage-driven hybrid generation, coverage RL reward shaping, pipeline integration
b32bdbb

Sai Kumar Taraka commited on