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Follow-up to the ZeroGPU/Blackwell maintenance PR: load the T5 text encoder in fp16 instead of 4-bit (bitsandbytes). The new ZeroGPU hardware has ample VRAM (48GB), so the 4-bit quantization the demo originally used to fit smaller GPUs is no longer needed — fp16 matches the model's training precision, reads slightly cleaner, and removes the bitsandbytes 4-bit path (a known fragility point on the new Blackwell/sm_120 GPUs). Verified end-to-end (T2V generation) with no quality regression and no OOM. As this is admin maintenance we may merge autonomously; feel free to revert or modify. Any issues: apolinario@huggingface.co