metadata
base_model:
- meta-llama/Meta-Llama-3-8B-Instruct
datasets:
- scale-lab/MetRex
library_name: transformers
Model Details
This model is trained on the MetRex dataset for estimating delay metrics for Verilog designs. Finetuned from model: Meta-Llama-3-8B-Instruct
Prompt
Set temperature to 0.4. Use the following prompt template:
<|begin_of_text|><|start_header_id|>system<|end_header_id|>
Your task is to estimate delay for RTL designs in Skywater 130nm technology node.<|eot_id|><|start_header_id|>user<|end_header_id|>
Estimate delay for the given RTL design. Reason about the number and type of gates that would be present after synthesis.
# RTL:
module top_module(
input a,
input b,
output out
);
assign out = ~(a | b);
endmodule<|eot_id|>
Citation
@INPROCEEDINGS{abdelatty2025metrex,
author={M. {Abdelatty} and J. {Ma} and S. {Reda}},
booktitle={2025 30th Asia and South Pacific Design Automation Conference (ASP-DAC)},
title={MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs},
year={2025},
volume={},
number={},
}