parti-wave/TAV_RGC_World_DiscoverPhysics

TAV RGC World — Deterministic 49-Core Logistic Lattice

A hardware-characterized, finite-precision logistic-map lattice (49 parallel Q1.31 iterators) on an Artix-7 FPGA

This world definition provides a realistic computational substrate based on actual FPGA telemetry from the logistic_bank core on the Arty A7-100T. It implements a 49-core synchronous logistic-map lattice in Q1.31 fixed-point arithmetic (32-bit recurrent state per core), with per-core r values spanning [3.5, 4.0] to tile the period-doubling route to chaos. The state is telemetered as its top 24 bits (x_value[31:8]); the low 8 bits are retained on-chip but not transmitted.

What This World Represents

Unlike purely theoretical or software-simulated worlds, this definition is grounded in measured hardware behavior from multiple independent cold-start runs (N1, N2, N3).

Key measured properties:

• 16 cores have periods short enough to be exactly resolved within the capture window and faithfully through the 24-bit telemetry.
• 33 cores have periods that are only lower bounds, for two compounding reasons: (a) their true period in the 32-bit Q1.31 state space exceeds the observation window, and (b) the 24-bit export drops the low 8 state bits, so an apparent repeat in telemetry is not a confirmed period (distinct 32-bit states can share the same top 24 bits). The partition is therefore an observation/telemetry-resolvability property, not a structural feature of the dynamics.
• Strict data integrity: only frames with delta_n = 49 are accepted. The iteration counter n is telemetered at full 32-bit width, so the integrity accounting is exact and unaffected by the x truncation.
• Computation is reproducible across independent runs at the telemetered 24-bit x observable (and at full precision for n).

Key Features

• 49-core deterministic logistic lattice (r_k = 3.500 + k/96)
• Real telemetry-derived period information for all cores
• Clear separation between resolved and projected cores
• Built-in integrity rule enforcement (delta_n = 49)
• Multi-run provenance (N1, N2 reference, N3 abridged goal & in hand, N4 in progress)
• Accompanying Python loader and analysis tools

Reproducibility — scope of the claim

Reproducibility is asserted for the telemetered x observable (top 24 bits of the 32-bit Q1.31 state) and for the full-width n counter. The recurrent state is 32 bits; the export transmits the high 24 of those bits and drops the low 8 (noise-dominated). Identical cold-start runs therefore reproduce the same telemetered x sequences bit-for-bit, but this is reproducibility of the 24-bit observable, not a claim about the 8 untransmitted state bits. This is the strongest statement the telemetry can support, and it is the one made here.

Data Integrity and the Capture-Onset Transient

Frame integrity is enforced by a single rule: only frames carrying a global iteration delta of exactly delta_n = 49 are accepted.

Steady-state frame corruption is zero. All rejected frames occur during the capture-onset framer-lock transient — the interval before byte/frame alignment is acquired on the free-running UART stream — and they never recur once lock is established. The FPGA emits frames continuously and does not wait for the host; when the host attaches, it drops into a live stream with pre-existing bytes in the transmit FIFO and OS serial buffer. Until two consecutive sequence-numbered frames produce a valid delta_n = 49, each misaligned read fails the integrity test and is rejected. Once lock is acquired it is retained for the remainder of the capture.

Empirically the transient is a fixed-depth flush: exactly 49 frames are rejected in every run (N1, N2, N3), independent of capture length — one rejected frame per core, consistent with a single stale 49-core readout sweep being cleared before lock. The count does not scale with run length (N2 = 4,000,000 frames and N3 = 8,000,000 target both show exactly 49), which is the signature of a one-time onset event rather than ongoing loss.

These onset frames are excised by the integrity rule at the loader, not by modifying the instrument during a live capture. A rejected frame appearing after lock would be a genuine anomaly; none has been observed across N1/N2/N3.

Current Status

This world is derived from extensive hardware characterization:

• N1 (1,209,644 frames) first 48 hour run.
• N2 (4,000,000 frames) serves as the current reference run, over 158.73 hours.
• N3 (3,134,863 frames) operator interference, over 124.46 hours.
• N4 (8,000,000 frames) currently underway at ~2.5M frames over ~97 hours and counting.
• Rejected frames are confined entirely to the capture-onset transient and number exactly 49 in every run (N1/N2/N3/N4); steady-state corruption is zero.
• Cross-run determinism is verified bit-for-bit: independent cold-start runs reproduce identical telemetered sequences (24-bit x, full-width n) over their full common prefix (N1 ≡ N2, N2 ≡ N3).
• The 16/33 resolved/projected partition is reproducible across runs. Because the partition reflects which periods fit the observation window (in a 32-bit state space, ceiling ~2^32 ≈ 4.3e9 per core), extending N3 to 8M frames can promote a core to "resolved" only if its true period falls within the newly observable range; cores remaining "projected" indicate periods exceeding the window, which is an observation limit rather than a structural bound.

Full methods and analysis are documented in the accompanying tav_rgc_world.yaml and supporting scripts.

Files Included

• tav_rgc_world.yaml — Core world definition (v1.1)
• tav_rgc_world.py — Python loader
• example_load_run.py — Example loader with integrity filtering
• compare_all_runs.py — Comparison tool across N1/N2/N3
• rgc_integrity.py — Capture-onset lock detection and frame partitioning
• README.md — Usage documentation

Quick Start

from tav_rgc_world import RGCWorld

world = RGCWorld("tav_rgc_world.yaml")
print(world.summary())

resolved = world.get_resolved_cores()
projected = world.get_projected_cores()