statement stringlengths 1 2.09k | proof stringlengths 0 22.1k | type stringclasses 25
values | symbolic_name stringlengths 1 49 | library stringclasses 14
values | filename stringclasses 212
values | imports listlengths 0 63 | deps listlengths 0 64 | docstring stringlengths 0 1.82k | source_url stringclasses 1
value | commit stringclasses 1
value |
|---|---|---|---|---|---|---|---|---|---|---|
initial_state (p: program): state -> Prop | :=
| initial_state_intro: forall m0,
Genv.init_mem p = Some m0 ->
let ge := Genv.globalenv p in
let rs0 :=
(Pregmap.init Vundef)
# PC <- (Genv.symbol_address ge p.(prog_main) Ptrofs.zero)
# RA <- Vnullptr
# SP <- Vnullptr in
initial_state p (State rs0 m0). | Inductive | initial_state | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Genv",
"SP",
"Vnullptr",
"ge",
"globalenv",
"init",
"init_mem",
"program",
"state",
"symbol_address",
"zero"
] | Execution of whole programs. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
final_state: state -> int -> Prop | :=
| final_state_intro: forall rs m r,
rs#PC = Vnullptr ->
rs#X0 = Vint r ->
final_state (State rs m) r. | Inductive | final_state | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Vnullptr",
"int",
"state"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
semantics (p: program) | :=
Semantics step (initial_state p) final_state (Genv.globalenv p). | Definition | semantics | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"Genv",
"Semantics",
"final_state",
"globalenv",
"initial_state",
"program",
"step"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
extcall_arguments_determ:
forall rs m sg args1 args2,
extcall_arguments rs m sg args1 -> extcall_arguments rs m sg args2 -> args1 = args2. | Proof.
intros until m.
assert (A: forall l v1 v2,
extcall_arg rs m l v1 -> extcall_arg rs m l v2 -> v1 = v2).
{ intros. inv H; inv H0; congruence. }
assert (B: forall p v1 v2,
extcall_arg_pair rs m p v1 -> extcall_arg_pair rs m p v2 -> v1 = v2).
{ intros. inv H; inv H0.
eapply A;... | Remark | extcall_arguments_determ | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"extcall_arg",
"extcall_arg_pair",
"extcall_arguments",
"inv",
"list_forall2"
] | Determinacy of the [Asm] semantics. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
semantics_determinate: forall p, determinate (semantics p). | Proof.
Ltac Equalities :=
match goal with
| [ H1: ?a = ?b, H2: ?a = ?c |- _ ] =>
rewrite H1 in H2; inv H2; Equalities
| _ => idtac
end.
intros; constructor; simpl; intros.
- (* determ *)
inv H; inv H0; Equalities.
split. constructor. auto.
discriminate.
discriminate.
assert (vargs0 = vargs) by... | Lemma | semantics_determinate | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"determinate",
"eval_builtin_args_determ",
"exploit",
"extcall_arguments_determ",
"external_call_determ",
"external_call_trace_length",
"inv",
"semantics"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
data_preg (r: preg) : bool | :=
match r with
| IR X16 => false
| IR X30 => false
| IR _ => true
| FR _ => true
| CR _ => false
| SP => true
| PC => false
end. | Definition | data_preg | aarch64 | aarch64/Asm.v | [
"Coqlib",
"Zbits",
"Maps",
"AST",
"Integers",
"Floats",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Locations",
"Conventions",
"Stacklayout"
] | [
"CR",
"FR",
"IR",
"SP",
"preg"
] | Classification functions for processor registers (used in Asmgenproof). | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
symbol_is_aligned : ident -> Z -> bool. | Parameter | symbol_is_aligned | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"ident"
] | Alignment check for symbols | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
ireg_of (r: mreg) : res ireg | :=
match preg_of r with IR mr => OK mr | _ => Error(msg "Asmgen.ireg_of") end. | Definition | ireg_of | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"IR",
"ireg",
"mreg",
"msg",
"preg_of",
"res"
] | Extracting integer or float registers. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
freg_of (r: mreg) : res freg | :=
match preg_of r with FR mr => OK mr | _ => Error(msg "Asmgen.freg_of") end. | Definition | freg_of | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"FR",
"freg",
"mreg",
"msg",
"preg_of",
"res"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
state : Type | := SA | SB | SC | SD | SE | SF | SG | Sbad. | Inductive | state | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
start | := SA. | Definition | start | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
next (s: state) (b: bool) | :=
match s, b with
| SA,false => SB | SA,true => SC
| SB,false => SB | SB,true => SD
| SC,false => SE | SC,true => SC
| SD,false => SF | SD,true => SD
| SE,false => SE | SE,true => SG
| SF,false => SF | SF,true => Sbad
| SG,false => Sbad | SG,true => SG
... | Definition | next | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"state"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
accepting (s: state) | :=
match s with
| SA | SB | SC | SD | SE | SF | SG => true
| Sbad => false
end. | Definition | accepting | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"state"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
run (len: nat) (s: state) (x: Z) : bool | :=
match len with
| Datatypes.O => accepting s
| Datatypes.S len => run len (next s (Z.odd x)) (Z.div2 x)
end. | Fixpoint | run | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"accepting",
"next",
"state"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
logical_imm_length (x: Z) (sixtyfour: bool) : nat | :=
(** [test n] checks that the low [2n] bits of [x] are of the
form [BB], that is, two occurrences of the same [n] bits *)
let test (n: Z) : bool :=
Z.eqb (Zzero_ext n x) (Zzero_ext n (Z.shiftr x n)) in
(** If [test n] fails, we know that the candidate length [e] is
at least [2n]. Hence we test ... | Definition | logical_imm_length | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"Zzero_ext"
] | The following function determines the candidate length [e],
ensuring that [x] is a repetition [BB...B]
of a bit pattern [B] of length [e]. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
is_logical_imm32 (x: int) : bool | :=
negb (Int.eq x Int.zero) && negb (Int.eq x Int.mone) &&
Automaton.run (logical_imm_length (Int.unsigned x) false)
Automaton.start (Int.unsigned x). | Definition | is_logical_imm32 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"eq",
"int",
"logical_imm_length",
"mone",
"run",
"start",
"unsigned",
"zero"
] | A valid logical immediate is
- neither [0] nor [-1];
- composed of a repetition [BBBBB] of a bit-pattern [B] of length [e]
- the low [e] bits of the number, that is, [B], match [0*1*0*] or [1*0*1*]. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
is_logical_imm64 (x: int64) : bool | :=
negb (Int64.eq x Int64.zero) && negb (Int64.eq x Int64.mone) &&
Automaton.run (logical_imm_length (Int64.unsigned x) true)
Automaton.start (Int64.unsigned x). | Definition | is_logical_imm64 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"eq",
"int64",
"logical_imm_length",
"mone",
"run",
"start",
"unsigned",
"zero"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
is_arith_imm32 (x: int) : bool | :=
Int.eq x (Int.zero_ext 12 x)
|| Int.eq x (Int.shl (Int.zero_ext 12 (Int.shru x (Int.repr 12))) (Int.repr 12)). | Definition | is_arith_imm32 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"eq",
"int",
"repr",
"shl",
"shru",
"zero_ext"
] | Arithmetic immediates are 12-bit unsigned numbers, possibly shifted left 12 bits | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
is_arith_imm64 (x: int64) : bool | :=
Int64.eq x (Int64.zero_ext 12 x)
|| Int64.eq x (Int64.shl (Int64.zero_ext 12 (Int64.shru x (Int64.repr 12))) (Int64.repr 12)). | Definition | is_arith_imm64 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"eq",
"int64",
"repr",
"shl",
"shru",
"zero_ext"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
decompose_int (N: nat) (n p: Z) {struct N} : list (Z * Z) | :=
match N with
| Datatypes.O => nil
| Datatypes.S N =>
let frag := Zzero_ext 16 (Z.shiftr n p) in
if Z.eqb frag 0 then
decompose_int N n (p + 16)
else
(frag, p) :: decompose_int N (Z.ldiff n (Z.shiftl 65535 p)) (p + 16)
end. | Fixpoint | decompose_int | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"Zzero_ext"
] | Decompose integer literals into 16-bit fragments | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
negate_decomposition (l: list (Z * Z)) | :=
List.map (fun np => (Z.lxor (fst np) 65535, snd np)) l. | Definition | negate_decomposition | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"map"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm_k (sz: isize) (rd: ireg) (l: list (Z * Z)) (k: code) : code | :=
List.fold_right (fun np k => Pmovk sz rd (fst np) (snd np) :: k) k l. | Definition | loadimm_k | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"ireg",
"isize"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm_z (sz: isize) (rd: ireg) (l: list (Z * Z)) (k: code) : code | :=
match l with
| nil => Pmovz sz rd 0 0 :: k
| (n1, p1) :: l => Pmovz sz rd n1 p1 :: loadimm_k sz rd l k
end. | Definition | loadimm_z | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"ireg",
"isize",
"loadimm_k"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm_n (sz: isize) (rd: ireg) (l: list (Z * Z)) (k: code) : code | :=
match l with
| nil => Pmovn sz rd 0 0 :: k
| (n1, p1) :: l => Pmovn sz rd n1 p1 :: loadimm_k sz rd (negate_decomposition l) k
end. | Definition | loadimm_n | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"ireg",
"isize",
"loadimm_k",
"negate_decomposition"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm (sz: isize) (rd: ireg) (n: Z) (k: code) : code | :=
let N := match sz with W => 2%nat | X => 4%nat end in
let dz := decompose_int N n 0 in
let dn := decompose_int N (Z.lnot n) 0 in
if Nat.leb (List.length dz) (List.length dn)
then loadimm_z sz rd dz k
else loadimm_n sz rd dn k. | Definition | loadimm | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"decompose_int",
"ireg",
"isize",
"leb",
"loadimm_n",
"loadimm_z"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm32 (rd: ireg) (n: int) (k: code) : code | :=
if is_logical_imm32 n
then Porrimm W rd XZR (Int.unsigned n) :: k
else loadimm W rd (Int.unsigned n) k. | Definition | loadimm32 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"int",
"ireg",
"is_logical_imm32",
"loadimm",
"unsigned"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm64 (rd: ireg) (n: int64) (k: code) : code | :=
if is_logical_imm64 n
then Porrimm X rd XZR (Int64.unsigned n) :: k
else loadimm X rd (Int64.unsigned n) k. | Definition | loadimm64 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"int64",
"ireg",
"is_logical_imm64",
"loadimm",
"unsigned"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
addimm_aux (insn: iregsp -> iregsp -> Z -> instruction)
(rd r1: iregsp) (n: Z) (k: code) | :=
let nlo := Zzero_ext 12 n in
let nhi := n - nlo in
if Z.eqb nhi 0 then
insn rd r1 nlo :: k
else if Z.eqb nlo 0 then
insn rd r1 nhi :: k
else
insn rd r1 nhi :: insn rd rd nlo :: k. | Definition | addimm_aux | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"Zzero_ext",
"code",
"instruction",
"iregsp"
] | Add immediate | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
addimm32 (rd r1: ireg) (n: int) (k: code) : code | :=
let m := Int.neg n in
if Int.eq n (Int.zero_ext 24 n) then
addimm_aux (Paddimm W) rd r1 (Int.unsigned n) k
else if Int.eq m (Int.zero_ext 24 m) then
addimm_aux (Psubimm W) rd r1 (Int.unsigned m) k
else if Int.lt n Int.zero then
loadimm32 X16 m (Psub W rd r1 X16 SOnone :: k)
else
loadimm32 X... | Definition | addimm32 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"addimm_aux",
"code",
"eq",
"int",
"ireg",
"loadimm32",
"lt",
"neg",
"unsigned",
"zero",
"zero_ext"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
addimm64 (rd r1: iregsp) (n: int64) (k: code) : code | :=
let m := Int64.neg n in
if Int64.eq n (Int64.zero_ext 24 n) then
addimm_aux (Paddimm X) rd r1 (Int64.unsigned n) k
else if Int64.eq m (Int64.zero_ext 24 m) then
addimm_aux (Psubimm X) rd r1 (Int64.unsigned m) k
else if Int64.lt n Int64.zero then
loadimm64 X16 m (Psubext rd r1 X16 (EOuxtx Int.zero... | Definition | addimm64 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"addimm_aux",
"code",
"eq",
"int64",
"iregsp",
"loadimm64",
"lt",
"neg",
"unsigned",
"zero",
"zero_ext"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
logicalimm32
(insn1: ireg -> ireg0 -> Z -> instruction)
(insn2: ireg -> ireg0 -> ireg -> shift_op -> instruction)
(rd r1: ireg) (n: int) (k: code) : code | :=
if is_logical_imm32 n
then insn1 rd r1 (Int.unsigned n) :: k
else loadimm32 X16 n (insn2 rd r1 X16 SOnone :: k). | Definition | logicalimm32 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"instruction",
"int",
"ireg",
"ireg0",
"is_logical_imm32",
"loadimm32",
"shift_op",
"unsigned"
] | Logical immediate | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
logicalimm64
(insn1: ireg -> ireg0 -> Z -> instruction)
(insn2: ireg -> ireg0 -> ireg -> shift_op -> instruction)
(rd r1: ireg) (n: int64) (k: code) : code | :=
if is_logical_imm64 n
then insn1 rd r1 (Int64.unsigned n) :: k
else loadimm64 X16 n (insn2 rd r1 X16 SOnone :: k). | Definition | logicalimm64 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"instruction",
"int64",
"ireg",
"ireg0",
"is_logical_imm64",
"loadimm64",
"shift_op",
"unsigned"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_extension (ex: extension) (a: int) : extend_op | :=
match ex with Xsgn32 => EOsxtw a | Xuns32 => EOuxtw a end. | Definition | transl_extension | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"extend_op",
"extension",
"int"
] | Sign- or zero-extended arithmetic | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
move_extended_base
(rd: ireg) (r1: ireg) (ex: extension) (k: code) : code | :=
match ex with
| Xsgn32 => Pcvtsw2x rd r1 :: k
| Xuns32 => Pcvtuw2x rd r1 :: k
end. | Definition | move_extended_base | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"extension",
"ireg"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
move_extended
(rd: ireg) (r1: ireg) (ex: extension) (a: int) (k: code) : code | :=
if Int.eq a Int.zero then
move_extended_base rd r1 ex k
else
move_extended_base rd r1 ex (Padd X rd XZR rd (SOlsl a) :: k). | Definition | move_extended | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"eq",
"extension",
"int",
"ireg",
"move_extended_base",
"zero"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
arith_extended
(insnX: iregsp -> iregsp -> ireg -> extend_op -> instruction)
(insnS: ireg -> ireg0 -> ireg -> shift_op -> instruction)
(rd r1 r2: ireg) (ex: extension) (a: int) (k: code) : code | :=
if Int.ltu a (Int.repr 5) then
insnX rd r1 r2 (transl_extension ex a) :: k
else
move_extended_base X16 r2 ex (insnS rd r1 X16 (SOlsl a) :: k). | Definition | arith_extended | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"extend_op",
"extension",
"instruction",
"int",
"ireg",
"ireg0",
"iregsp",
"ltu",
"move_extended_base",
"repr",
"shift_op",
"transl_extension"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
shrx32 (rd r1: ireg) (n: int) (k: code) : code | :=
if Int.eq n Int.zero then
Pmov rd r1 :: k
else
Porr W X16 XZR r1 (SOasr (Int.repr 31)) ::
Padd W X16 r1 X16 (SOlsr (Int.sub Int.iwordsize n)) ::
Porr W rd XZR X16 (SOasr n) :: k. | Definition | shrx32 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"eq",
"int",
"ireg",
"iwordsize",
"repr",
"sub",
"zero"
] | Extended right shift | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
shrx64 (rd r1: ireg) (n: int) (k: code) : code | :=
if Int.eq n Int.zero then
Pmov rd r1 :: k
else
Porr X X16 XZR r1 (SOasr (Int.repr 63)) ::
Padd X X16 r1 X16 (SOlsr (Int.sub Int64.iwordsize' n)) ::
Porr X rd XZR X16 (SOasr n) :: k. | Definition | shrx64 | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"eq",
"int",
"ireg",
"iwordsize'",
"repr",
"sub",
"zero"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadsymbol (rd: ireg) (id: ident) (ofs: ptrofs) (k: code) : code | :=
if SelectOp.symbol_is_relocatable id then
if Ptrofs.eq ofs Ptrofs.zero then
Ploadsymbol rd id :: k
else
Ploadsymbol rd id :: addimm64 rd rd (Ptrofs.to_int64 ofs) k
else
Padrp rd id ofs :: Paddadr rd rd id ofs :: k. | Definition | loadsymbol | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"addimm64",
"code",
"eq",
"ident",
"ireg",
"ptrofs",
"to_int64",
"zero"
] | Load the address [id + ofs] in [rd] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_shift (s: Op.shift) (a: int): Asm.shift_op | :=
match s with
| Slsl => SOlsl a
| Slsr => SOlsr a
| Sasr => SOasr a
| Sror => SOror a
end. | Definition | transl_shift | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"int",
"shift",
"shift_op"
] | Translate a shifted operand | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_cond
(cond: condition) (args: list mreg) (k: code) | :=
match cond, args with
| (Ccomp c | Ccompu c), a1 :: a2 :: nil =>
do r1 <- ireg_of a1; do r2 <- ireg_of a2;
OK (Pcmp W r1 r2 SOnone :: k)
| (Ccompshift c s a | Ccompushift c s a), a1 :: a2 :: nil =>
do r1 <- ireg_of a1; do r2 <- ireg_of a2;
OK (Pcmp W r1 r2 (transl_shift s a) :: k)
| (... | Definition | transl_cond | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"cmp",
"code",
"condition",
"freg_of",
"ireg_of",
"is_arith_imm32",
"is_arith_imm64",
"is_logical_imm32",
"is_logical_imm64",
"loadimm32",
"loadimm64",
"mreg",
"msg",
"neg",
"transl_shift",
"unsigned"
] | Translation of a condition. Prepends to [k] the instructions
that evaluate the condition and leave its boolean result in one of
the bits of the condition register. The bit in question is
determined by the [crbit_for_cond] function. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
cond_for_signed_cmp (cmp: comparison) | :=
match cmp with
| Ceq => TCeq
| Cne => TCne
| Clt => TClt
| Cle => TCle
| Cgt => TCgt
| Cge => TCge
end. | Definition | cond_for_signed_cmp | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"cmp",
"comparison"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
cond_for_unsigned_cmp (cmp: comparison) | :=
match cmp with
| Ceq => TCeq
| Cne => TCne
| Clt => TClo
| Cle => TCls
| Cgt => TChi
| Cge => TChs
end. | Definition | cond_for_unsigned_cmp | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"cmp",
"comparison"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
cond_for_float_cmp (cmp: comparison) | :=
match cmp with
| Ceq => TCeq
| Cne => TCne
| Clt => TCmi
| Cle => TCls
| Cgt => TCgt
| Cge => TCge
end. | Definition | cond_for_float_cmp | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"cmp",
"comparison"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
cond_for_float_not_cmp (cmp: comparison) | :=
match cmp with
| Ceq => TCne
| Cne => TCeq
| Clt => TCpl
| Cle => TChi
| Cgt => TCle
| Cge => TClt
end. | Definition | cond_for_float_not_cmp | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"cmp",
"comparison"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
cond_for_cond (cond: condition) | :=
match cond with
| Ccomp cmp => cond_for_signed_cmp cmp
| Ccompu cmp => cond_for_unsigned_cmp cmp
| Ccompshift cmp s a => cond_for_signed_cmp cmp
| Ccompushift cmp s a => cond_for_unsigned_cmp cmp
| Ccompimm cmp n => cond_for_signed_cmp cmp
| Ccompuimm cmp n => cond_for_unsigned_cmp cmp
| Cmaskzero n ... | Definition | cond_for_cond | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"cmp",
"cond_for_float_cmp",
"cond_for_float_not_cmp",
"cond_for_signed_cmp",
"cond_for_unsigned_cmp",
"condition"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_cond_branch_default
(c: condition) (args: list mreg) (lbl: label) (k: code) | :=
transl_cond c args (Pbc (cond_for_cond c) lbl :: k). | Definition | transl_cond_branch_default | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"cond_for_cond",
"condition",
"label",
"mreg",
"transl_cond"
] | Translation of a conditional branch. Prepends to [k] the instructions
that evaluate the condition and ranch to [lbl] if it holds.
We recognize some conditional branches that can be implemented
without setting then testing condition flags. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_cond_branch
(c: condition) (args: list mreg) (lbl: label) (k: code) | :=
match args, c with
| a1 :: nil, (Ccompimm Cne n | Ccompuimm Cne n) =>
if Int.eq n Int.zero
then (do r1 <- ireg_of a1; OK (Pcbnz W r1 lbl :: k))
else transl_cond_branch_default c args lbl k
| a1 :: nil, (Ccompimm Ceq n | Ccompuimm Ceq n) =>
if Int.eq n Int.zero
then (do r1 <- ireg_... | Definition | transl_cond_branch | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"condition",
"eq",
"ireg_of",
"is_power2",
"is_power2'",
"label",
"mreg",
"transl_cond_branch_default",
"zero"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_op
(op: operation) (args: list mreg) (res: mreg) (k: code) | :=
match op, args with
| Omove, a1 :: nil =>
match preg_of res, preg_of a1 with
| IR r, IR a => OK (Pmov r a :: k)
| FR r, FR a => OK (Pfmov r a :: k)
| _ , _ => Error(msg "Asmgen.Omove")
end
| Ointconst n, nil =>
do rd <- ireg_of res;
OK (loadimm32 rd n k)
| Olong... | Definition | transl_op | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"FR",
"IR",
"addimm32",
"addimm64",
"arith_extended",
"cmp",
"code",
"cond_for_cond",
"eq_dec",
"freg_eq",
"freg_of",
"ireg_eq",
"ireg_of",
"loadimm32",
"loadimm64",
"loadsymbol",
"logicalimm32",
"logicalimm64",
"move_extended",
"mreg",
"msg",
"operation",
"preg_of",
"r... | Translation of the arithmetic operation [res <- op(args)].
The corresponding instructions are prepended to [k]. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
offset_representable (sz: Z) (ofs: int64) : bool | :=
let isz := Int64.repr sz in
(** either unscaled 9-bit signed *)
Int64.eq ofs (Int64.sign_ext 9 ofs) ||
(** or scaled 12-bit unsigned *)
(Int64.eq (Int64.modu ofs isz) Int64.zero
&& Int64.ltu ofs (Int64.shl isz (Int64.repr 12))). | Definition | offset_representable | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"eq",
"int64",
"ltu",
"modu",
"repr",
"shl",
"sign_ext",
"zero"
] | Translation of addressing modes | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_addressing (sz: Z) (addr: Op.addressing) (args: list mreg)
(insn: Asm.addressing -> instruction) (k: code) : res code | :=
match addr, args with
| Aindexed ofs, a1 :: nil =>
do r1 <- ireg_of a1;
if offset_representable sz ofs then
OK (insn (ADimm r1 ofs) :: k)
else
OK (loadimm64 X16 ofs (insn (ADreg r1 X16) :: k))
| Aindexed2, a1 :: a2 :: nil =>
do r1 <- ireg_of a1; do r2 <- ireg_of a2;
... | Definition | transl_addressing | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"addressing",
"arith_extended",
"code",
"eq",
"instruction",
"ireg_of",
"loadimm64",
"loadsymbol",
"modu",
"mreg",
"msg",
"offset_representable",
"one",
"repr",
"res",
"shl",
"symbol_is_aligned",
"to_int64",
"zero"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_load (chunk: memory_chunk) (addr: Op.addressing)
(args: list mreg) (dst: mreg) (k: code) : res code | :=
match chunk with
| Mint8unsigned =>
do rd <- ireg_of dst; transl_addressing 1 addr args (Pldrb W rd) k
| Mint8signed =>
do rd <- ireg_of dst; transl_addressing 1 addr args (Pldrsb W rd) k
| Mint16unsigned =>
do rd <- ireg_of dst; transl_addressing 2 addr args (Pldrh W rd) k
| Mint16signed... | Definition | transl_load | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"addressing",
"code",
"freg_of",
"ireg_of",
"memory_chunk",
"mreg",
"msg",
"res",
"transl_addressing"
] | Translation of loads and stores | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_store (chunk: memory_chunk) (addr: Op.addressing)
(args: list mreg) (src: mreg) (k: code) : res code | :=
match chunk with
| Mint8unsigned =>
do r1 <- ireg_of src; transl_addressing 1 addr args (Pstrb r1) k
| Mint16unsigned =>
do r1 <- ireg_of src; transl_addressing 2 addr args (Pstrh r1) k
| Mint32 =>
do r1 <- ireg_of src; transl_addressing 4 addr args (Pstrw r1) k
| Mint64 =>
do r1 <-... | Definition | transl_store | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"addressing",
"code",
"freg_of",
"ireg_of",
"memory_chunk",
"mreg",
"msg",
"res",
"transl_addressing"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
indexed_memory_access (insn: Asm.addressing -> instruction)
(sz: Z) (base: iregsp) (ofs: ptrofs) (k: code) | :=
let ofs := Ptrofs.to_int64 ofs in
if offset_representable sz ofs
then insn (ADimm base ofs) :: k
else loadimm64 X16 ofs (insn (ADreg base X16) :: k). | Definition | indexed_memory_access | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"addressing",
"code",
"instruction",
"iregsp",
"loadimm64",
"offset_representable",
"ptrofs",
"to_int64"
] | Register-indexed loads and stores | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
loadind (base: iregsp) (ofs: ptrofs) (ty: typ) (dst: mreg) (k: code) | :=
match ty, preg_of dst with
| Tint, IR rd => OK (indexed_memory_access (Pldrw rd) 4 base ofs k)
| Tlong, IR rd => OK (indexed_memory_access (Pldrx rd) 8 base ofs k)
| Tsingle, FR rd => OK (indexed_memory_access (Pldrs rd) 4 base ofs k)
| Tfloat, FR rd => OK (indexed_memory_access (Pldrd rd) 8 base ofs... | Definition | loadind | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"FR",
"IR",
"code",
"indexed_memory_access",
"iregsp",
"mreg",
"msg",
"preg_of",
"ptrofs",
"typ"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
storeind (src: mreg) (base: iregsp) (ofs: ptrofs) (ty: typ) (k: code) | :=
match ty, preg_of src with
| Tint, IR rd => OK (indexed_memory_access (Pstrw rd) 4 base ofs k)
| Tlong, IR rd => OK (indexed_memory_access (Pstrx rd) 8 base ofs k)
| Tsingle, FR rd => OK (indexed_memory_access (Pstrs rd) 4 base ofs k)
| Tfloat, FR rd => OK (indexed_memory_access (Pstrd rd) 8 base ofs... | Definition | storeind | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"FR",
"IR",
"code",
"indexed_memory_access",
"iregsp",
"mreg",
"msg",
"preg_of",
"ptrofs",
"typ"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadptr (base: iregsp) (ofs: ptrofs) (dst: ireg) (k: code) | :=
indexed_memory_access (Pldrx dst) 8 base ofs k. | Definition | loadptr | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"indexed_memory_access",
"ireg",
"iregsp",
"ptrofs"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
storeptr (src: ireg) (base: iregsp) (ofs: ptrofs) (k: code) | :=
indexed_memory_access (Pstrx src) 8 base ofs k. | Definition | storeptr | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"indexed_memory_access",
"ireg",
"iregsp",
"ptrofs"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
make_epilogue (f: Mach.function) (k: code) | :=
loadptr XSP f.(fn_retaddr_ofs) RA
(Pfreeframe f.(fn_stacksize) f.(fn_link_ofs) :: k). | Definition | make_epilogue | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"function",
"loadptr"
] | Function epilogue | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_instr (f: Mach.function) (i: Mach.instruction)
(r15_is_parent: bool) (k: code) : res code | :=
match i with
| Mgetstack ofs ty dst =>
loadind XSP ofs ty dst k
| Msetstack src ofs ty =>
storeind src XSP ofs ty k
| Mgetparam ofs ty dst =>
(* load via the frame pointer if it is valid *)
do c <- loadind X15 ofs ty dst k;
OK (if r15_is_parent then c else loadptr XSP f.(fn_link... | Definition | transl_instr | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"function",
"instruction",
"ireg_of",
"loadind",
"loadptr",
"make_epilogue",
"map",
"map_builtin_arg",
"map_builtin_res",
"preg_of",
"res",
"storeind",
"transl_cond_branch",
"transl_load",
"transl_op",
"transl_store"
] | Translation of a Mach instruction. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
it1_is_parent (before: bool) (i: Mach.instruction) : bool | :=
match i with
| Msetstack src ofs ty => before
| Mgetparam ofs ty dst => negb (mreg_eq dst R15)
| Mop op args res => before && negb (mreg_eq res R15)
| _ => false
end. | Definition | it1_is_parent | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"instruction",
"mreg_eq",
"res"
] | Translation of a code sequence | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_code (f: Mach.function) (il: list Mach.instruction) (it1p: bool) | :=
match il with
| nil => OK nil
| i1 :: il' =>
do k <- transl_code f il' (it1_is_parent it1p i1);
transl_instr f i1 it1p k
end. | Fixpoint | transl_code | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"function",
"instruction",
"it1_is_parent",
"transl_instr"
] | This is the naive definition that we no longer use because it
is not tail-recursive. It is kept as specification. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_code_rec (f: Mach.function) (il: list Mach.instruction)
(it1p: bool) (k: code -> res code) | :=
match il with
| nil => k nil
| i1 :: il' =>
transl_code_rec f il' (it1_is_parent it1p i1)
(fun c1 => do c2 <- transl_instr f i1 it1p c1; k c2)
end. | Fixpoint | transl_code_rec | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"code",
"function",
"instruction",
"it1_is_parent",
"res",
"transl_instr"
] | This is an equivalent definition in continuation-passing style
that runs in constant stack space. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transl_code' (f: Mach.function) (il: list Mach.instruction) (it1p: bool) | :=
transl_code_rec f il it1p (fun c => OK c). | Definition | transl_code' | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"function",
"instruction",
"transl_code_rec"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_function (f: Mach.function) | :=
do c <- transl_code' f f.(Mach.fn_code) true;
OK (mkfunction f.(Mach.fn_sig)
(Pallocframe f.(fn_stacksize) f.(fn_link_ofs) f.(fn_retaddr_ofs) ::
Pcfi_rel_offset (Ptrofs.to_int f.(fn_retaddr_ofs)) :: c)). | Definition | transl_function | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"function",
"to_int",
"transl_code'"
] | Translation of a whole function. Note that we must check
that the generated code contains less than [2^64] instructions,
otherwise the offset part of the [PC] code pointer could wrap
around, leading to incorrect executions. | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
transf_function (f: Mach.function) : res Asm.function | :=
do tf <- transl_function f;
if zlt Ptrofs.max_unsigned (list_length_z tf.(fn_code))
then Error (msg "code size exceeded")
else OK tf. | Definition | transf_function | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"function",
"list_length_z",
"max_unsigned",
"msg",
"res",
"transl_function",
"zlt"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transf_fundef (f: Mach.fundef) : res Asm.fundef | :=
transf_partial_fundef transf_function f. | Definition | transf_fundef | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"fundef",
"res",
"transf_function",
"transf_partial_fundef"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transf_program (p: Mach.program) : res Asm.program | :=
transform_partial_program transf_fundef p. | Definition | transf_program | aarch64 | aarch64/Asmgen.v | [
"Coq",
"Recdef",
"Zwf",
"Zbits",
"Coqlib",
"Errors",
"AST",
"Integers",
"Floats",
"Op",
"Locations",
"Mach",
"Asm",
"SelectOp"
] | [
"program",
"res",
"transf_fundef",
"transform_partial_program"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
match_prog (p: Mach.program) (tp: Asm.program) | :=
match_program (fun _ f tf => transf_fundef f = OK tf) eq p tp. | Definition | match_prog | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"eq",
"match_program",
"program",
"transf_fundef"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transf_program_match:
forall p tp, transf_program p = OK tp -> match_prog p tp. | Proof.
intros. eapply match_transform_partial_program; eauto.
Qed. | Lemma | transf_program_match | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"match_prog",
"match_transform_partial_program",
"transf_program"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
TRANSF: match_prog prog tprog. | Hypothesis | TRANSF | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"match_prog"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | ||
ge | := Genv.globalenv prog. | Let | ge | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"Genv",
"globalenv"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
tge | := Genv.globalenv tprog. | Let | tge | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"Genv",
"globalenv"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
symbols_preserved:
forall (s: ident), Genv.find_symbol tge s = Genv.find_symbol ge s. | Proof (Genv.find_symbol_match TRANSF). | Lemma | symbols_preserved | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"Genv",
"TRANSF",
"find_symbol",
"find_symbol_match",
"ge",
"ident",
"tge"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
senv_preserved:
Senv.equiv ge tge. | Proof (Genv.senv_match TRANSF). | Lemma | senv_preserved | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"Genv",
"TRANSF",
"equiv",
"ge",
"senv_match",
"tge"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
functions_translated:
forall b f,
Genv.find_funct_ptr ge b = Some f ->
exists tf,
Genv.find_funct_ptr tge b = Some tf /\ transf_fundef f = OK tf. | Proof (Genv.find_funct_ptr_transf_partial TRANSF). | Lemma | functions_translated | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"Genv",
"TRANSF",
"find_funct_ptr",
"find_funct_ptr_transf_partial",
"ge",
"tge",
"transf_fundef"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
functions_transl:
forall fb f tf,
Genv.find_funct_ptr ge fb = Some (Internal f) ->
transf_function f = OK tf ->
Genv.find_funct_ptr tge fb = Some (Internal tf). | Proof.
intros. exploit functions_translated; eauto. intros [tf' [A B]].
monadInv B. rewrite H0 in EQ; inv EQ; auto.
Qed. | Lemma | functions_transl | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"Genv",
"exploit",
"find_funct_ptr",
"functions_translated",
"ge",
"inv",
"monadInv",
"tge",
"transf_function"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transf_function_no_overflow:
forall f tf,
transf_function f = OK tf -> list_length_z tf.(fn_code) <= Ptrofs.max_unsigned. | Proof.
intros. monadInv H. destruct (zlt Ptrofs.max_unsigned (list_length_z x.(fn_code))); inv EQ0.
lia.
Qed. | Lemma | transf_function_no_overflow | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"inv",
"list_length_z",
"max_unsigned",
"monadInv",
"transf_function",
"zlt"
] | * Properties of control flow | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
exec_straight_exec:
forall fb f c ep tf tc c' rs m rs' m',
transl_code_at_pc ge (rs PC) fb f c ep tf tc ->
exec_straight tge tf tc rs m c' rs' m' ->
plus step tge (State rs m) E0 (State rs' m'). | Proof.
intros. inv H.
eapply exec_straight_steps_1; eauto.
eapply transf_function_no_overflow; eauto.
eapply functions_transl; eauto.
Qed. | Lemma | exec_straight_exec | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"E0",
"exec_straight",
"exec_straight_steps_1",
"functions_transl",
"ge",
"inv",
"plus",
"step",
"tge",
"transf_function_no_overflow",
"transl_code_at_pc"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
exec_straight_at:
forall fb f c ep tf tc c' ep' tc' rs m rs' m',
transl_code_at_pc ge (rs PC) fb f c ep tf tc ->
transl_code f c' ep' = OK tc' ->
exec_straight tge tf tc rs m tc' rs' m' ->
transl_code_at_pc ge (rs' PC) fb f c' ep' tf tc'. | Proof.
intros. inv H.
exploit exec_straight_steps_2; eauto.
eapply transf_function_no_overflow; eauto.
eapply functions_transl; eauto.
intros [ofs' [PC' CT']].
rewrite PC'. constructor; auto.
Qed. | Lemma | exec_straight_at | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"exec_straight",
"exec_straight_steps_2",
"exploit",
"functions_transl",
"ge",
"inv",
"tge",
"transf_function_no_overflow",
"transl_code",
"transl_code_at_pc"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm_z_label: forall sz rd l k, tail_nolabel k (loadimm_z sz rd l k). | Proof.
intros; destruct l as [ | [n1 p1] l]; simpl; TailNoLabel.
induction l as [ | [n p] l]; simpl; TailNoLabel.
Qed. | Remark | loadimm_z_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"loadimm_z",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm_n_label: forall sz rd l k, tail_nolabel k (loadimm_n sz rd l k). | Proof.
intros; destruct l as [ | [n1 p1] l]; simpl; TailNoLabel.
induction l as [ | [n p] l]; simpl; TailNoLabel.
Qed. | Remark | loadimm_n_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"loadimm_n",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm_label: forall sz rd n k, tail_nolabel k (loadimm sz rd n k). | Proof.
unfold loadimm; intros. destruct Nat.leb; [apply loadimm_z_label|apply loadimm_n_label].
Qed. | Remark | loadimm_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"leb",
"loadimm",
"loadimm_n_label",
"loadimm_z_label",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm32_label: forall r n k, tail_nolabel k (loadimm32 r n k). | Proof.
unfold loadimm32; intros. destruct (is_logical_imm32 n); TailNoLabel.
Qed. | Remark | loadimm32_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"is_logical_imm32",
"loadimm32",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadimm64_label: forall r n k, tail_nolabel k (loadimm64 r n k). | Proof.
unfold loadimm64; intros. destruct (is_logical_imm64 n); TailNoLabel.
Qed. | Remark | loadimm64_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"is_logical_imm64",
"loadimm64",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
addimm_aux: forall insn rd r1 n k,
(forall rd r1 n, nolabel (insn rd r1 n)) ->
tail_nolabel k (addimm_aux insn rd r1 n k). | Proof.
unfold addimm_aux; intros.
destruct Z.eqb. TailNoLabel. destruct Z.eqb; TailNoLabel.
Qed. | Remark | addimm_aux | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"nolabel",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
addimm32_label: forall rd r1 n k, tail_nolabel k (addimm32 rd r1 n k). | Proof.
unfold addimm32; intros.
destruct Int.eq. apply addimm_aux; intros; red; auto.
destruct Int.eq. apply addimm_aux; intros; red; auto.
destruct Int.lt; eapply tail_nolabel_trans; TailNoLabel.
Qed. | Remark | addimm32_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"addimm32",
"addimm_aux",
"eq",
"lt",
"tail_nolabel",
"tail_nolabel_trans"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
addimm64_label: forall rd r1 n k, tail_nolabel k (addimm64 rd r1 n k). | Proof.
unfold addimm64; intros.
destruct Int64.eq. apply addimm_aux; intros; red; auto.
destruct Int64.eq. apply addimm_aux; intros; red; auto.
destruct Int64.lt; eapply tail_nolabel_trans; TailNoLabel.
Qed. | Remark | addimm64_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"addimm64",
"addimm_aux",
"eq",
"lt",
"tail_nolabel",
"tail_nolabel_trans"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
logicalimm32_label: forall insn1 insn2 rd r1 n k,
(forall rd r1 n, nolabel (insn1 rd r1 n)) ->
(forall rd r1 r2 s, nolabel (insn2 rd r1 r2 s)) ->
tail_nolabel k (logicalimm32 insn1 insn2 rd r1 n k). | Proof.
unfold logicalimm32; intros.
destruct (is_logical_imm32 n). TailNoLabel. eapply tail_nolabel_trans; TailNoLabel.
Qed. | Remark | logicalimm32_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"is_logical_imm32",
"logicalimm32",
"nolabel",
"tail_nolabel",
"tail_nolabel_trans"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
logicalimm64_label: forall insn1 insn2 rd r1 n k,
(forall rd r1 n, nolabel (insn1 rd r1 n)) ->
(forall rd r1 r2 s, nolabel (insn2 rd r1 r2 s)) ->
tail_nolabel k (logicalimm64 insn1 insn2 rd r1 n k). | Proof.
unfold logicalimm64; intros.
destruct (is_logical_imm64 n). TailNoLabel. eapply tail_nolabel_trans; TailNoLabel.
Qed. | Remark | logicalimm64_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"is_logical_imm64",
"logicalimm64",
"nolabel",
"tail_nolabel",
"tail_nolabel_trans"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
move_extended_label: forall rd r1 ex a k, tail_nolabel k (move_extended rd r1 ex a k). | Proof.
unfold move_extended, move_extended_base; intros. destruct Int.eq, ex; TailNoLabel.
Qed. | Remark | move_extended_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"eq",
"move_extended",
"move_extended_base",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
arith_extended_label: forall insnX insnS rd r1 r2 ex a k,
(forall rd r1 r2 x, nolabel (insnX rd r1 r2 x)) ->
(forall rd r1 r2 s, nolabel (insnS rd r1 r2 s)) ->
tail_nolabel k (arith_extended insnX insnS rd r1 r2 ex a k). | Proof.
unfold arith_extended; intros. destruct Int.ltu.
TailNoLabel.
destruct ex; simpl; TailNoLabel.
Qed. | Remark | arith_extended_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"arith_extended",
"ltu",
"nolabel",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
loadsymbol_label: forall r id ofs k, tail_nolabel k (loadsymbol r id ofs k). | Proof.
intros; unfold loadsymbol.
destruct (SelectOp.symbol_is_relocatable id); TailNoLabel. destruct Ptrofs.eq; TailNoLabel.
Qed. | Remark | loadsymbol_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"eq",
"loadsymbol",
"tail_nolabel"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_cond_label: forall cond args k c,
transl_cond cond args k = OK c -> tail_nolabel k c. | Proof.
unfold transl_cond; intros; destruct cond; TailNoLabel.
- destruct is_arith_imm32; TailNoLabel. destruct is_arith_imm32; TailNoLabel. eapply tail_nolabel_trans; TailNoLabel.
- destruct is_arith_imm32; TailNoLabel. destruct is_arith_imm32; TailNoLabel. eapply tail_nolabel_trans; TailNoLabel.
- destruct is_logic... | Remark | transl_cond_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"is_arith_imm32",
"is_arith_imm64",
"is_logical_imm32",
"is_logical_imm64",
"tail_nolabel",
"tail_nolabel_trans",
"transl_cond"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_cond_branch_default_label: forall cond args lbl k c,
transl_cond_branch_default cond args lbl k = OK c -> tail_nolabel k c. | Proof.
unfold transl_cond_branch_default; intros.
eapply tail_nolabel_trans; [eapply transl_cond_label;eauto|TailNoLabel].
Qed. | Remark | transl_cond_branch_default_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"tail_nolabel",
"tail_nolabel_trans",
"transl_cond_branch_default",
"transl_cond_label"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_cond_branch_label: forall cond args lbl k c,
transl_cond_branch cond args lbl k = OK c -> tail_nolabel k c. | Proof.
unfold transl_cond_branch; intros; destruct args; TailNoLabel; destruct cond; TailNoLabel.
- destruct c0; TailNoLabel.
- destruct c0; TailNoLabel.
- destruct (Int.is_power2 n); TailNoLabel.
- destruct (Int.is_power2 n); TailNoLabel.
- destruct c0; TailNoLabel.
- destruct c0; TailNoLabel.
- destruct (Int64.is_p... | Remark | transl_cond_branch_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"is_power2",
"is_power2'",
"tail_nolabel",
"transl_cond_branch"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_op_label:
forall op args r k c,
transl_op op args r k = OK c -> tail_nolabel k c. | Proof.
unfold transl_op; intros; destruct op; TailNoLabel.
- destruct (preg_of r); try discriminate; destruct (preg_of m); inv H; TailNoLabel.
- destruct (Float.eq_dec n Float.zero); TailNoLabel.
- destruct (Float32.eq_dec n Float32.zero); TailNoLabel.
- apply logicalimm32_label; unfold nolabel; auto.
- apply logical... | Remark | transl_op_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"arith_extended_label",
"eq",
"eq_dec",
"inv",
"logicalimm32_label",
"logicalimm64_label",
"nolabel",
"preg_of",
"shrx32",
"shrx64",
"tail_nolabel",
"tail_nolabel_trans",
"transl_cond_label",
"transl_op",
"zero"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_addressing_label:
forall sz addr args insn k c,
transl_addressing sz addr args insn k = OK c ->
(forall ad, nolabel (insn ad)) ->
tail_nolabel k c. | Proof.
unfold transl_addressing; intros; destruct addr; TailNoLabel;
eapply tail_nolabel_trans; TailNoLabel.
eapply tail_nolabel_trans. apply arith_extended_label; unfold nolabel; auto. TailNoLabel.
Qed. | Remark | transl_addressing_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"arith_extended_label",
"nolabel",
"tail_nolabel",
"tail_nolabel_trans",
"transl_addressing"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_load_label:
forall chunk addr args dst k c,
transl_load chunk addr args dst k = OK c -> tail_nolabel k c. | Proof.
unfold transl_load; intros; destruct chunk; TailNoLabel; eapply transl_addressing_label; eauto; unfold nolabel; auto.
Qed. | Remark | transl_load_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"nolabel",
"tail_nolabel",
"transl_addressing_label",
"transl_load"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 | |
transl_store_label:
forall chunk addr args src k c,
transl_store chunk addr args src k = OK c -> tail_nolabel k c. | Proof.
unfold transl_store; intros; destruct chunk; TailNoLabel; eapply transl_addressing_label; eauto; unfold nolabel; auto.
Qed. | Remark | transl_store_label | aarch64 | aarch64/Asmgenproof.v | [
"Coqlib",
"Errors",
"Integers",
"Floats",
"AST",
"Linking",
"Values",
"Memory",
"Events",
"Globalenvs",
"Smallstep",
"Op",
"Locations",
"Mach",
"Conventions",
"Asm",
"Asmgen",
"Asmgenproof0",
"Asmgenproof1"
] | [
"TailNoLabel",
"nolabel",
"tail_nolabel",
"transl_addressing_label",
"transl_store"
] | https://github.com/AbsInt/CompCert | 0ef26dad76446c803da02d7368eb4f9d074c1401 |
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