task_id stringlengths 16 24 | shuttle_name stringclasses 7
values | project_name stringlengths 12 79 | task_name stringlengths 7 59 | top_module_name stringlengths 9 54 | system_message stringclasses 1
value | prompt stringlengths 724 368k | golden_module stringlengths 66 320k |
|---|---|---|---|---|---|---|---|
tt07-finale_0201 | tt07-finale | leeja-j-router_tinytapeout | task_router_reg | tt_um_router | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_router (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module router_reg(clock,resetn,pkt_valid,data_in,fifo_full,detect_add,
ld_state,laf_state,full_state,lfd_state,rst_int_reg,err,
parity_done,low_packet_valid,dout);
input clock,resetn,pkt_valid,fifo_full,detect_add,ld_state,laf_state,full_state,lfd_state,rst_int_reg;
input [2:0]data_... |
tt07-finale_0202 | tt07-finale | leeja-j-router_tinytapeout | task_router_sync | tt_um_router | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_router (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module router_sync(clock,resetn,data_in,detect_add,full_0,full_1,full_2,empty_0,empty_1,empty_2,write_enb_reg,read_enb_0,read_enb_1,read_enb_2,write_enb,fifo_full,vld_out_0,vld_out_1,vld_out_2,soft_reset_0,soft_reset_1,soft_reset_2);
input clock,resetn,detect_add,full_0,full_1,full_2,empty_0,empty_1,empty_2,write_enb... |
tt07-finale_0203 | tt07-finale | leeja-j-router_tinytapeout | task_router_top | tt_um_router | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_router (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module router_top(clock,resetn,pkt_valid,read_enb_0,read_enb_1,read_enb_2,data_in,
busy,err,vld_out_0,vld_out_1,vld_out_2,data_out_0,data_out_1,data_out_2);
input [2:0]data_in;
input pkt_valid,clock,resetn,read_enb_0,read_enb_1,read_enb_2;
output [2:0]data_out_0,data_out_1,data_out_2;
output vld_out_... |
tt07-finale_0204 | tt07-finale | leeja-j-router_tinytapeout | task_tt_um_router | tt_um_router | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_router (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: ... | module tt_um_router (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
i... |
tt07-finale_0205 | tt07-finale | mitsece-tt07-verilog-mitssdd | task_co_processor | tt_um_mitssdd | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs:... | module co_processor (
input [7:0] r0, // 8-bit input
input [1:0] check, // sensor checking
input reset,
input clk, // clock input
output reg Q, // output Q connected to LED
output reg [1:0] Q1
);
reg [7:0] proc = 8'b0; // processing register
reg [7:0] r1 = 8'b0;
reg [7:0] r2 = 8'b0;
reg [7:0]... |
tt07-finale_0206 | tt07-finale | mitsece-tt07-verilog-mitssdd | task_fault_pro | tt_um_mitssdd | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mitssdd (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs:... | module fault_pro(
input [7:0] r0,
input [1:0] check,
input reset,
input clk,
output reg [2:0] out,
output reg [1:0] out1);
//data storing registers
reg [9:0] r1=10'b0;
reg [9:0] r2=10'b0;
reg [9:0] r3=10'b0;
reg [9:0] r4=10'b0;
//1st 4 set mean values
reg [9:0] m1=10'b0;
reg [9:0] m2=10'b0;
reg [9:0... |
tt07-finale_0207 | tt07-finale | olofk-underserved | task_serv_aligner | tt_um_underserved | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module serv_bufreg #(
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
input wire i_cnt0,
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_mdu_op,
output wire [1:0] o_lsb,... | module serv_aligner
(
input wire clk,
input wire rst,
// serv_top
input wire [31:0] i_ibus_adr,
input wire i_ibus_cyc,
output wire [31:0] o_ibus_rdt,
output wire o_ibus_ack,
// serv_rf_top
output wire [31:0] o_wb_ibus_adr,
output wire o_wb_ibus_cyc... |
tt07-finale_0208 | tt07-finale | olofk-underserved | task_serv_bufreg2 | tt_um_underserved | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module serv_bufreg #(
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
input wire i_cnt0,
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_mdu_op,
output wire [1:0] o_lsb,... | module serv_bufreg2
(
input wire i_clk,
//State
input wire i_en,
input wire i_init,
input wire i_cnt_done,
input wire [1:0] i_lsb,
input wire i_byte_valid,
output wire o_sh_done,
output wire o_sh_done_r,
//Control
input wire i_... |
tt07-finale_0209 | tt07-finale | olofk-underserved | task_serv_compdec | tt_um_underserved | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module serv_bufreg #(
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
input wire i_cnt0,
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_mdu_op,
output wire [1:0] o_lsb,... | module serv_compdec
(
input wire i_clk,
input wire [31:0] i_instr,
input wire i_ack,
output wire [31:0] o_instr,
output reg o_iscomp);
localparam OPCODE_LOAD = 7'h03;
localparam OPCODE_OP_IMM = 7'h13;
localparam OPCODE_STORE = 7'h23;
localparam OPCODE_OP = 7'h33;
localparam ... |
tt07-finale_0210 | tt07-finale | olofk-underserved | task_spimemio | tt_um_underserved | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module serv_bufreg #(
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
input wire i_cnt0,
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_mdu_op,
output wire [1:0] o_lsb,... | module spimemio (
input clk, resetn,
input valid,
output ready,
input [23:0] addr,
output reg [31:0] rdata,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output fla... |
tt07-finale_0211 | tt07-finale | olofk-underserved | task_spimemio_xfer | tt_um_underserved | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module serv_bufreg #(
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
input wire i_cnt0,
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_mdu_op,
output wire [1:0] o_lsb,... | module spimemio_xfer (
input clk, resetn,
input din_valid,
output din_ready,
input [7:0] din_data,
input [3:0] din_tag,
input din_cont,
input din_dspi,
input din_qspi,
input din_ddr,
input din_rd,
output dout_va... |
tt07-finale_0212 | tt07-finale | olofk-underserved | task_subservient_gpio | tt_um_underserved | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module serv_bufreg #(
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
input wire i_cnt0,
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_mdu_op,
output wire [1:0] o_lsb,... | module subservient_gpio
(input wire i_wb_clk,
input wire i_wb_rst,
input wire [4:0] i_wb_dat,
input wire i_wb_we,
input wire i_wb_stb,
output reg o_wb_rdt,
output reg o_wb_ack,
output reg [4:0] o_gpio);
always @(posedge i_wb_clk) begin
o_wb_rdt <= o_gpio;
i... |
tt07-finale_0213 | tt07-finale | olofk-underserved | task_tt_um_underserved | tt_um_underserved | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | module serv_bufreg #(
parameter [0:0] MDU = 0,
parameter W = 1,
parameter B = W-1
)(
input wire i_clk,
//State
input wire i_cnt0,
input wire i_cnt1,
input wire i_en,
input wire i_init,
input wire i_mdu_op,
output wire [1:0] o_lsb,... | module tt_um_underserved (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0214 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_bitmap_rom_ddct | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module bitmap_rom_ddct (
input wire [6:0] x,
input wire [6:0] y,
output wire pixel
);
reg [7:0] mem[2047:0];
initial begin
mem[0] = 8'h00;
mem[1] = 8'h00;
mem[2] = 8'h00;
mem[3] = 8'h00;
mem[4] = 8'h00;
mem[5] = 8'h00;
mem[6] = 8'h00;
mem[7] = 8'h00;
mem[8] = 8'h00;
... |
tt07-finale_0215 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_bitmap_rom_sk | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module bitmap_rom_sk (
input wire [6:0] x,
input wire [6:0] y,
output wire pixel
);
reg [7:0] mem[2047:0];
initial begin
mem[0] = 8'h00;
mem[1] = 8'h00;
mem[2] = 8'h00;
mem[3] = 8'h00;
mem[4] = 8'h00;
mem[5] = 8'h00;
mem[6] = 8'h00;
mem[7] = 8'he0;
mem[8] = 8'h00;
... |
tt07-finale_0216 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_dot4 | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module dot4(
input clk,
input reset,
input start,
input signed [15:0] v1_x,
input signed [15:0] v1_y,
input signed [15:0] v1_z,
input signed [15:0] v1_w,
input signed [15:0] v2_x,
input signed [15:0] v2_y,
input signed [15:0] v2_z,
input signed [15:0] v2_w,
output reg done,
output reg signed [15:0] result
... |
tt07-finale_0217 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_ia | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module ia(
input clk,
input reset,
input rx,
output reg pc_ready, //must be true for only 1 clk
output reg [7:0] read_data,
output reg [6:0] idx, // 0-60
output reg update_reg
);
wire read_done;
wire [7:0] byte_data;
uart_top UART_UNIT(.clk(clk),.reset(reset),.rx(rx),
.rx_data_out(byte_da... |
tt07-finale_0218 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_raster | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module raster(
input clk,
input reset,
// from vga
input [9:0] x,
input [9:0] y,
// from VS,
input [1:0] intensity, // 2-bit
input [7:0] render_mode,
input signed [19:0] y_screen_v0, // change per frame, int20
input signed [19:0] y_screen_v1,
input signed [19:0] y_screen_v2,
input signed [1... |
tt07-finale_0219 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_tt_um_pongsagon_tiniest_gpu | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... |
tt07-finale_0220 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_vga | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module vga(
input clk,
input reset,
output HS, VS,
output [9:0] x,
output [9:0] y,
output blank
);
// Counter Registers, two each for buffering to avoid glitches
reg [9:0] xc, yc, xc_next, yc_next;
reg [1:0] prescaler;
reg HS_reg;
reg VS_reg;
wire HS_next, VS_next;
// Horizontal 640 + fp 16 + HS 96... |
tt07-finale_0221 | tt07-finale | pongsagon-tt07-tiniest-gpu | task_vs | tt_um_pongsagon_tiniest_gpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Matt Pongsagon Vichitvejpaisal
* SPDX-License-Identifier: Apache-2.0
*/
//`timescale 1ns / 1ps
module tt_um_pongsagon_tiniest_gpu (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module vs(
input clk,
input reset,
// from vga
input [9:0] x,
input [9:0] y,
// from top, set by IA
input pc_data_ready, // true for 1 clk
input signed [15:0] x_world_v0, // Q8.8
input signed [15:0] y_world_v0,
input signed [15:0] z_world_v0,
input signed [15:0] x_world_v1,
input signed [15:0] y... |
tt07-finale_0222 | tt07-finale | rejunity-vga-checkers | task_tt_um_rejunity_vga | tt_um_rejunity_vga | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 ReJ aka Renaldas Zioma
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
/*
Video sync generator, used to drive a VGA monitor.
Timing from: https://en.wikipedia.org/wiki/Video_Graphics_Array
To use:
- Wire the hsync and vsync signals to top level outputs
- Add a 3-bit (or more)... | module tt_um_rejunity_vga(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input w... |
tt07-finale_0223 | tt07-finale | rejunity-z80-open-silicon | task_tt_um_rejunity_z80 | tt_um_rejunity_z80 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Softw... | module tt_um_rejunity_z80 (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)... |
tt07-finale_0224 | tt07-finale | rejunity-z80-open-silicon | task_tv80_alu | tt_um_rejunity_z80 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Softw... | module tv80_alu (/*AUTOARG*/
// Outputs
Q, F_Out,
// Inputs
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
);
parameter Mode = 0;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = ... |
tt07-finale_0225 | tt07-finale | rejunity-z80-open-silicon | task_tv80_core | tt_um_rejunity_z80 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Softw... | module tv80_core (/*AUTOARG*/
// Outputs
m1_n, iorq, no_read, write, rfsh_n, halt_n, busak_n, A, dout, mc,
ts, intcycle_n, IntE, stop,
// Inputs
reset_n, clk, cen, wait_n, int_n, nmi_n, busrq_n, dinst, di
);
// Beginning of automatic inputs (from unused autoinst inputs)
// End of automatics
parameter... |
tt07-finale_0226 | tt07-finale | rejunity-z80-open-silicon | task_tv80_mcode | tt_um_rejunity_z80 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Softw... | module tv80_mcode
(/*AUTOARG*/
// Outputs
MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
Exc... |
tt07-finale_0227 | tt07-finale | rejunity-z80-open-silicon | task_tv80_reg | tt_um_rejunity_z80 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Softw... | module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
inpu... |
tt07-finale_0228 | tt07-finale | rejunity-z80-open-silicon | task_tv80s | tt_um_rejunity_z80 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Softw... | module tv80s (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout, write,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di, cen
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => ... |
tt07-finale_0229 | tt07-finale | rejunity-z80-open-silicon | task_z80 | tt_um_rejunity_z80 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | //
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Softw... | module z80 (
input wire clk,
input wire cen,
input wire reset_n,
input wire wait_n,
input wire int_n,
input wire nmi_n,
input wire busrq_n,
input wire [7:0] di,
output wire [7:0] dout,
output wire doe,
... |
tt07-finale_0230 | tt07-finale | shadow1229-tt07-vga-player | task_tt_um_shadow1229_vga_player | tt_um_shadow1229_vga_player | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_shadow1229_vga_player (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (... | module tt_um_shadow1229_vga_player (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, ... |
tt07-finale_0231 | tt07-finale | shivam7086-tt07-verilog-RO_PUF | task_comp | tt_um_PUF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module comp(
input [7:0] count1,
input [7:0] count2,
output reg[7:0] uo_out
);
(* S= "TRUE"*)(* ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *)
always @(count1 or count2)
begin
if(&count1 > &count2)
begin
uo_out <= count1;
... |
tt07-finale_0232 | tt07-finale | shivam7086-tt07-verilog-RO_PUF | task_counter | tt_um_PUF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module counter(
input m_out,
input rst_n,
output reg[7:0] count
);
(* S= "TRUE"*)(* ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *)
initial count=8'h00;
always @(posedge m_out or posedge rst_n)
begin
if( rst_n)
begin
count = 0;
... |
tt07-finale_0233 | tt07-finale | shivam7086-tt07-verilog-RO_PUF | task_f2g | tt_um_PUF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module f2g (output p, q, r, input a, b, c);
assign p=a;
assign q=a^b;
assign r=a^c;
endmodule |
tt07-finale_0234 | tt07-finale | shivam7086-tt07-verilog-RO_PUF | task_mux32 | tt_um_PUF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module mux32(
input wire[32:1] i,
input wire[4:0] ui_in,
output reg m_out
);
(* S= "TRUE"*)(* ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *)
always @(*)
begin
case(ui_in)
5'b00000: m_out=i[1];
5'b00001: m_out=i[2];
5'b00010: m_out=i[3];
5'b0001... |
tt07-finale_0235 | tt07-finale | shivam7086-tt07-verilog-RO_PUF | task_osc_f2g | tt_um_PUF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module osc_f2g (output out, input ena);
wire [4:0] p, q, r;
wire A;
f2g g0(p[0], q[0], r[0], A, 1'b1, 1'b1);
f2g g1(p[1], q[1], r[1], r[0], 1'b1, 1'b1);
f2g g2(p[2], q[2], r[2], q[1], 1'b1, 1'b1);
f2g g3(p[3], q[3], r[3], r[2], 1'b1, 1'b1);
f2g g4(p[4], q[4], r[4], q[3], 1'b1, 1'b1);
and a0(out, ena, r[4]);
assign A=ou... |
tt07-finale_0236 | tt07-finale | shivam7086-tt07-verilog-RO_PUF | task_top_f2g | tt_um_PUF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module top_f2g (output [7:0] count, input ena, rst_n, input [4:0] ui_in);
wire [31:0] i;
wire mux_out;
genvar x;
generate
for(x=0; x<32; x=x+1)
begin
(* S= "TRUE"*)(* ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *)
osc_f2g f0(i[x], ena);
end
endgenerate
mux32 uut(i, ui_in, mux_out);
... |
tt07-finale_0237 | tt07-finale | shivam7086-tt07-verilog-RO_PUF | task_tt_um_PUF | tt_um_PUF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Ou... | module tt_um_PUF (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
inpu... |
tt07-finale_0238 | tt07-finale | sreeramtirumalasetty-major | task_booth_encoding | tt_um_multiplier_mbm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_multiplier_mbm (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out,... | module booth_encoding(input a,b,c,
output zero,one,minus_one,two, minus_two);
wire a_n,b_n,c_n,a1,a2,a3,a4,a5,a6;
wire [7:0]i;
decoder_3_8 dec({a,b,c},i);
assign a_n=~a;
assign b_n=~b;
assign c_n=~c;
assign a1= a_n & b_n & c_n & i[0];
assign a2=a & b & c & i[7];
assign a3= a_n & b_n & c & i[1];
assig... |
tt07-finale_0239 | tt07-finale | sreeramtirumalasetty-major | task_cla | tt_um_multiplier_mbm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_multiplier_mbm (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out,... | module cla(input [15:0]x, input [13:0]y, input cin, output [15:0]sum);
wire [13:0] p;
wire [13:0]g;
wire [13:1] c;
assign sum[0]= x[0];
assign sum[1]= x[1];
assign p[0]= x[2] ^ y[0];
assign g[0]= x[2] & y[0];
assign c[1]= g[0] | (p[0] & cin);
assign sum[2]= p[0] ^ cin;
assign p[1]= x[3] ^ y[1];
assign g[1]= x[3] & ... |
tt07-finale_0240 | tt07-finale | sreeramtirumalasetty-major | task_decoder_3_8 | tt_um_multiplier_mbm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_multiplier_mbm (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out,... | module decoder_3_8(input [2:0]din,
output reg[7:0]dout);
always @( din )
begin
dout=8'd0;
case (din)
3'b000: dout[0]=1'b1;
3'b001: dout[1]=1'b1;
3'b010: dout[2]=1'b1;
3'b011: dout[3]=1'b1;
3'b100: dout... |
tt07-finale_0241 | tt07-finale | sreeramtirumalasetty-major | task_latchh | tt_um_multiplier_mbm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_multiplier_mbm (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out,... | module latchh(input [7:0]d, // 1-bit input pin for data
input clk, // 1-bit input pin for enabling the latch
output reg [7:0]q); // 1-bit output pin for data output
always @ (posedge clk)
q <= d;
endmodule |
tt07-finale_0242 | tt07-finale | sreeramtirumalasetty-major | task_tt_um_multiplier_mbm | tt_um_multiplier_mbm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_multiplier_mbm (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out,... | module tt_um_multiplier_mbm (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=outpu... |
tt07-finale_0243 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_add_sub | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module add_sub(
input wire [31:0] in_x,
input wire [31:0] in_y,
input wire operation,
input wire [2:0] round_mode,
output wire [31:0] out_z,
output wire [4:0] exceptions);
wire sign_x, sign_y;
wire [7:0] exp_x, exp_y, exp_a, exp_b, subnorm_exp, norm_exp;
wire [22:0] mant_x, mant... |
tt07-finale_0244 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_fp_add_sub | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module fp_add_sub (
input wire [31:0] a_operand,
input wire [31:0] b_operand,
input wire op_subtract,
output reg [31:0] o_result
);
add_sub a(
.in_x(a_operand),
.in_y(b_operand),
.operation(op_subtract),
.round_mode(3'b000),
.out_z(o_result)
);
endmodule |
tt07-finale_0245 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_fp_multiply | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module fp_multiply (
// input wire [31:0] a_operand,
// input wire [31:0] b_operand,
// output reg o_exception,
// output reg o_overflow,
// output reg o_underflow,
// output reg [31:0] o_result
// );
//
// Implement IEEE-754 floating point multiplication.
// ```
`default_nettype none
module ... |
tt07-finale_0246 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_leading_zero | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module leading_zero
(
input wire [23:0] in,
output wire [4:0] out
);
assign out[4:0] = ({5{(in[22] & (&(~(in[23]))))}} & 5'd1) |
({5{(in[21] & (&(~(in[23:22]))))}} & 5'd2) |
({5{(in[20] & (&(~(in[23:21]))))}} & 5'd3) |
... |
tt07-finale_0247 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_mandelbrot_func | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module mandelbrot_func (
input wire [31:0] Ci,
input wire [31:0] Cr,
input wire [31:0] Zr,
input wire [31:0] Zi,
output wire [31:0] Rr,
output wire [31:0] Ri,
output wire unbounded
);
// ZrZi = Zr * Zi
wire [31:0] ZrZi;
fp_multiply m1 (
.a_operand(Zr),
.b_operand(Zi),
... |
tt07-finale_0248 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_right_shifter | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module right_shifter
(
input wire [26:0] mantisa,
input wire [7:0] shift_amount,
output wire [26:0] out
);
assign out = ({27{(shift_amount[7:0]==8'd0)}} & mantisa) |
({27{(shift_amount[7:0]==8'd1)}} & {1'd0, mantisa[26:2], |mantisa[1:0]}) |
... |
tt07-finale_0249 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_rounding | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module rounding
(
input wire sign,
input wire [26:0] mantisa,
input wire [2:0] round_mode,
output wire [23:0] rounded_mantisa,
output wire rounding_overflow
);
wire [23:0] rne, rtz, rdn, rup, rmm;
wire rne_overflow, rtz_overflow, rdn_overflow, rup_overflow, rmm_overflow;
assign {rne_overflow, rn... |
tt07-finale_0250 | tt07-finale | urish-tt07-mandelbrot-accelarator | task_tt_um_mandelbrot_accel | tt_um_mandelbrot_accel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out... | module tt_um_mandelbrot_accel (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=out... |
tt07-finale_0251 | tt07-finale | urish-tt07-simon-game | task_play | tt_um_urish_simon | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2023-2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
/*
* Simon Says game in Verilog. Wokwi Simulation project:
* https://wokwi.com/projects/397436605640509441
*/
`default_nettype none
module wokwi (
input CLK,
input RST,
input BTN0,
input BTN1,
... | module play (
input wire clk,
input wire rst,
input wire [15:0] ticks_per_milli,
input wire [9:0] freq,
output reg sound
);
reg [31:0] tick_counter;
wire [31:0] ticks_per_second = ticks_per_milli * 1000;
wire [31:0] freq32 = {22'b0, freq};
always @(posedge clk) begin
if (rst) begin
... |
tt07-finale_0252 | tt07-finale | urish-tt07-simon-game | task_score | tt_um_urish_simon | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2023-2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
/*
* Simon Says game in Verilog. Wokwi Simulation project:
* https://wokwi.com/projects/397436605640509441
*/
`default_nettype none
module wokwi (
input CLK,
input RST,
input BTN0,
input BTN1,
... | module score (
input wire clk,
input wire rst,
input wire ena,
input wire invert,
input wire inc,
output reg [6:0] segments,
output reg [1:0] digits
);
reg active_digit;
reg [3:0] ones;
reg [3:0] tens;
wire [3:0] digit_value = active_digit ? tens : ones;
always @(posedge clk) begi... |
tt07-finale_0253 | tt07-finale | urish-tt07-simon-game | task_simon | tt_um_urish_simon | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2023-2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
/*
* Simon Says game in Verilog. Wokwi Simulation project:
* https://wokwi.com/projects/397436605640509441
*/
`default_nettype none
module wokwi (
input CLK,
input RST,
input BTN0,
input BTN1,
... | module simon (
input wire clk,
input wire rst,
input wire [15:0] ticks_per_milli,
input wire [3:0] btn,
input wire segments_invert,
output reg [3:0] led,
output wire sound,
output wire [6:0] segments,
output wire [1:0] segment_digits
);
localparam MAX_GAME_LEN = 32;
wire [9:0] ... |
tt07-finale_0254 | tt07-finale | urish-tt07-simon-game | task_tt_um_urish_simon | tt_um_urish_simon | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2023-2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
/*
* Simon Says game in Verilog. Wokwi Simulation project:
* https://wokwi.com/projects/397436605640509441
*/
`default_nettype none
module wokwi (
input CLK,
input RST,
input BTN0,
input BTN1,
... | module tt_um_urish_simon (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0255 | tt07-finale | urish-tt07-simon-game | task_wokwi | tt_um_urish_simon | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2023-2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
/*
* Simon Says game in Verilog. Wokwi Simulation project:
* https://wokwi.com/projects/397436605640509441
*/
`default_nettype none
module wokwi (
input CLK,
input RST,
input BTN0,
input BTN1,
... | module wokwi (
input CLK,
input RST,
input BTN0,
input BTN1,
input BTN2,
input BTN3,
output LED0,
output LED1,
output LED2,
output LED3,
output SND,
output SEG_A,
output SEG_B,
output SEG_C,
output SEG_D,
output SEG_E,
output SEG_F,
output SE... |
tt07-finale_0256 | tt07-finale | urish-tt07-spell | task_spell_execute | tt_um_urish_spell | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
`default_nettype none
module tt_um_urish_spell (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module spell_execute (
input wire [7:0] opcode,
input wire [7:0] pc,
input wire [4:0] sp,
input wire [7:0] stack_top,
input wire [7:0] stack_belowtop,
input wire [7:0] memory_input,
input wire out_of_order_exec,
output reg [7:0] next_pc,
output reg [4:0] next_sp,
output reg [1:0]... |
tt07-finale_0257 | tt07-finale | urish-tt07-spell | task_spell_mem | tt_um_urish_spell | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
`default_nettype none
module tt_um_urish_spell (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module spell_mem (
input wire rst_n,
input wire clk,
input wire select,
input wire [7:0] addr,
input wire [7:0] data_in,
input wire memory_type_data,
input wire write,
output reg [7:0] data_out,
output wire data_ready,
/* IO */
output wire [7:0] porta_out,
output wire [7... |
tt07-finale_0258 | tt07-finale | urish-tt07-spell | task_spell_mem_internal | tt_um_urish_spell | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
`default_nettype none
module tt_um_urish_spell (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module spell_mem_internal (
input wire rst_n,
input wire clk,
input wire select,
input wire [7:0] addr,
input wire [7:0] data_in,
input wire memory_type_data,
input wire write,
output wire [7:0] data_out,
output reg data_ready
);
localparam data_mem_size = 32;
wire code_mem_lo_... |
tt07-finale_0259 | tt07-finale | urish-tt07-spell | task_spell_mem_io | tt_um_urish_spell | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
`default_nettype none
module tt_um_urish_spell (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module spell_mem_io (
input wire rst_n,
input wire clk,
input wire select,
input wire [7:0] addr,
input wire [7:0] data_in,
input wire write,
output reg [7:0] data_out,
output reg data_ready,
/* porta */
output reg [7:0] porta_out,
output reg [7:0] porta_oe, // out enable ... |
tt07-finale_0260 | tt07-finale | urish-tt07-spell | task_tt_um_urish_spell | tt_um_urish_spell | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | // SPDX-FileCopyrightText: © 2024 Uri Shaked <uri@wokwi.com>
// SPDX-License-Identifier: MIT
`default_nettype none
module tt_um_urish_spell (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0... | module tt_um_urish_spell (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt07-finale_0261 | tt07-finale | vicvicvarunis-tt_unis_nano_24 | task_tt_um_unisnano | tt_um_unisnano | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... |
module tt_um_unisnano
(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always... | module tt_um_unisnano
(
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire ena, // always 1 ... |
tt07-finale_0262 | tt07-finale | vrteee-tt07-mini-aie-cgra | task_compute_tile | tt_um_mini_aie_2x2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_mini_aie_2x2 (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
/* verilator lint_off UNUSEDSIGNAL */
input wire [7:0] uio_in, // IOs: Bidirection... | module compute_tile
(
input wire clk,
input wire rst_n,
input [7:0] switch_data_in,
output reg [7:0] switch_data_out,
output reg [7:0] next_pe_data_out,
input [7:0] next_pe_data_in,
input [7:0] prev_pe_data_in,
output reg [7:0] prev_pe_data_out
);
reg op_type;
reg [3:0] weight;... |
tt07-finale_0263 | tt07-finale | vrteee-tt07-mini-aie-cgra | task_tt_um_mini_aie_2x2 | tt_um_mini_aie_2x2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_mini_aie_2x2 (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
/* verilator lint_off UNUSEDSIGNAL */
input wire [7:0] uio_in, // IOs: Bidirection... | module tt_um_mini_aie_2x2 (
input wire [7:0] ui_in, // Dedicated inputs - connected to the input switches
output wire [7:0] uo_out, // Dedicated outputs - connected to the 7 segment display
/* verilator lint_off UNUSEDSIGNAL */
input wire [7:0] uio_in, // IOs: Bidirectional Input path
/* ve... |
tt07-finale_0264 | tt07-finale | vzayakov-tt07-pong-vga | task_Adder | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Adder (
A,
B,
Cin,
Sum,
Cout
);
parameter WIDTH = 8;
input wire [WIDTH - 1:0] A;
input wire [WIDTH - 1:0] B;
input wire Cin;
output wire [WIDTH - 1:0] Sum;
output wire Cout;
assign {Cout, Sum} = (A + B) + Cin;
endmodule |
tt07-finale_0265 | tt07-finale | vzayakov-tt07-pong-vga | task_Ball | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Ball (
clock,
reset_ballrow,
reset_ballcol,
reset_left,
preset_left,
reset_up,
en_BR,
en_BC,
D_left,
leftHit,
rightHit,
RWin,
LWin,
Q_BC,
Q_BR,
up,
left
);
input wire clock;
input wire reset_ballrow;
input wire reset_ballcol;
input wire reset_left;
input wire preset_left;
input wire reset_... |
tt07-finale_0266 | tt07-finale | vzayakov-tt07-pong-vga | task_Color | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Color (
VGA_row,
VGA_col,
Q_BC,
Q_BR,
Q_LP,
Q_RP,
showScoreLeft,
showScoreRight,
isB_L1,
isB_R1,
isB_L2,
isB_R2,
isB_L3,
isB_R3,
isB_L4,
isB_R4,
VGA_R,
VGA_G,
VGA_B
);
input wire [8:0] VGA_row;
input wire [9:0] VGA_col;
input wire [9:0] Q_BC;
input wire [8:0] Q_BR;
input wire [8:0] Q_LP;
... |
tt07-finale_0267 | tt07-finale | vzayakov-tt07-pong-vga | task_Counter | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Counter (
en,
clear,
load,
up,
clock,
D,
Q
);
parameter WIDTH = 8;
input wire en;
input wire clear;
input wire load;
input wire up;
input wire clock;
input wire [WIDTH - 1:0] D;
output reg [WIDTH - 1:0] Q;
always @(posedge clock)
if (clear)
Q <= 1'sb0;
else if (load)
Q <= D;
else if (... |
tt07-finale_0268 | tt07-finale | vzayakov-tt07-pong-vga | task_DFlipFlop | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module DFlipFlop (
Q,
D,
clock,
reset_L,
preset_L
);
output reg Q;
input wire D;
input wire clock;
input wire reset_L;
input wire preset_L;
always @(posedge clock)
if (~reset_L)
Q <= 0;
else if (~preset_L)
Q <= 1;
else
Q <= D;
endmodule |
tt07-finale_0269 | tt07-finale | vzayakov-tt07-pong-vga | task_MagComp | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module MagComp (
A,
B,
AltB,
AeqB,
AgtB
);
parameter WIDTH = 8;
input wire [WIDTH - 1:0] A;
input wire [WIDTH - 1:0] B;
output wire AltB;
output wire AeqB;
output wire AgtB;
assign AeqB = A == B;
assign AltB = A < B;
assign AgtB = A > B;
endmodule |
tt07-finale_0270 | tt07-finale | vzayakov-tt07-pong-vga | task_Mux2to1 | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Mux2to1 (
I0,
I1,
S,
Y
);
parameter WIDTH = 8;
input wire [WIDTH - 1:0] I0;
input wire [WIDTH - 1:0] I1;
input wire S;
output wire [WIDTH - 1:0] Y;
assign Y = (S ? I1 : I0);
endmodule |
tt07-finale_0271 | tt07-finale | vzayakov-tt07-pong-vga | task_OffsetCheck | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module OffsetCheck (
delta,
low,
val,
is_between
);
parameter WIDTH = 8;
input wire [WIDTH - 1:0] delta;
input wire [WIDTH - 1:0] low;
input wire [WIDTH - 1:0] val;
output wire is_between;
wire [WIDTH - 1:0] sum;
wire cout;
wire [WIDTH:0] full_sum;
wire [WIDTH:0] full_val;
wire [WIDTH:0] full_low;
Adder ... |
tt07-finale_0272 | tt07-finale | vzayakov-tt07-pong-vga | task_Paddle | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Paddle (
en_P,
move,
clock,
reset_paddle,
up,
Q_P
);
input wire en_P;
input wire move;
input wire clock;
input wire reset_paddle;
input wire up;
output wire [8:0] Q_P;
wire cout;
wire bounds0lt;
wire bounds1gt;
reg [8:0] AddIn;
wire [8:0] D_P;
wire [8:0] M_P;
Register #(.WIDTH(9)) PaddleRow(
... |
tt07-finale_0273 | tt07-finale | vzayakov-tt07-pong-vga | task_RangeCheck | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module RangeCheck (
val,
high,
low,
is_between
);
parameter WIDTH = 8;
input wire [WIDTH - 1:0] val;
input wire [WIDTH - 1:0] high;
input wire [WIDTH - 1:0] low;
output reg is_between;
wire valLtHigh;
wire valGtHigh;
wire valEqHigh;
wire valLtLow;
wire valGtLow;
wire valEqLow;
MagComp #(.WIDTH(WIDTH)) c... |
tt07-finale_0274 | tt07-finale | vzayakov-tt07-pong-vga | task_Register | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Register (
en,
clear,
clock,
D,
Q
);
parameter WIDTH = 8;
input wire en;
input wire clear;
input wire clock;
input wire [WIDTH - 1:0] D;
output reg [WIDTH - 1:0] Q;
always @(posedge clock)
if (en)
Q <= D;
else if (clear)
Q <= 1'sb0;
endmodule |
tt07-finale_0275 | tt07-finale | vzayakov-tt07-pong-vga | task_ScoreOnDisplay | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module ScoreOnDisplay (
rowChoice,
curr_row,
colChoice,
curr_col,
hexOutput_L,
is_between
);
input wire [8:0] rowChoice;
input wire [8:0] curr_row;
input wire [9:0] colChoice;
input wire [9:0] curr_col;
input wire [6:0] hexOutput_L;
output wire is_between;
wire [9:0] a1_out;
wire [8:0] a2_out;
wire [8:0]... |
tt07-finale_0276 | tt07-finale | vzayakov-tt07-pong-vga | task_Scoring | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Scoring (
en_Rscore,
en_Lscore,
clr_score,
CLOCK_50,
L1,
L2,
L3,
L4,
R1,
R2,
R3,
R4
);
input wire en_Rscore;
input wire en_Lscore;
input wire clr_score;
input wire CLOCK_50;
output wire [3:0] L1;
output wire [3:0] L2;
output wire [3:0] L3;
output wire [3:0] L4;
output wire [3:0] R1;
output ... |
tt07-finale_0277 | tt07-finale | vzayakov-tt07-pong-vga | task_SevenSegment | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module SevenSegment (
BCDnumber,
hexOutput_L
);
input wire [3:0] BCDnumber;
output reg [6:0] hexOutput_L;
always @(*)
case (BCDnumber)
4'd0: hexOutput_L = 7'b1000000;
4'd1: hexOutput_L = 7'b1111001;
4'd2: hexOutput_L = 7'b0100100;
4'd3: hexOutput_L = 7'b0110000;
4'd4: hexOutput_L = 7'b0011001;
... |
tt07-finale_0278 | tt07-finale | vzayakov-tt07-pong-vga | task_Synchronizer | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module Synchronizer (
async,
clock,
sync
);
input wire async;
input wire clock;
output reg sync;
reg async_1;
always @(posedge clock) begin
async_1 <= async;
sync <= async_1;
end
endmodule |
tt07-finale_0279 | tt07-finale | vzayakov-tt07-pong-vga | task_pong | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module pong (
serve_L_async,
reset_L,
CLOCK_50,
R_move_async,
R_up_async,
L_move_async,
L_up_async,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7,
VGA_R,
VGA_G,
VGA_B,
HS,
VS,
blank,
L1,
L2,
L3,
L4,
R1,
R2,
R3,
R4
);
input wire serve_L_async;
input wire reset_L;
input wire CLOCK_50;
in... |
tt07-finale_0280 | tt07-finale | vzayakov-tt07-pong-vga | task_pong_fsm | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module pong_fsm (
serve_L,
reset_L,
LWin,
RWin,
CLOCK_50,
VS_display_done,
reset_paddle,
reset_ballcol,
reset_ballrow,
preset_left,
preset_up,
reset_left,
reset_up,
clr_score,
en_BR,
en_BC,
en_LPadR,
en_RPadR,
en_Lscore,
en_Rscore,
showScoreRight,
showScoreLeft
);
input wire serve_L;
input wire ... |
tt07-finale_0281 | tt07-finale | vzayakov-tt07-pong-vga | task_tt_um_vzayakov_top | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module SevenSegment (
BCDnumber,
hexOutput_L
);
input wire [3:0] BCDnumber;
output reg [6:0] hexOutput_L;
always @(*)... | module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_switch;
wire R_up_swit... |
tt07-finale_0282 | tt07-finale | vzayakov-tt07-pong-vga | task_vga | tt_um_vzayakov_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module tt_um_vzayakov_top (
ui_in,
uo_out,
uio_in,
uio_out,
uio_oe,
ena,
clk,
rst_n
);
input wire [7:0] ui_in;
output wire [7:0] uo_out;
input wire [7:0] uio_in;
output wire [7:0] uio_out;
output wire [7:0] uio_oe;
input wire ena;
input wire clk;
input wire rst_n;
wire R_move_s... | module vga (
CLOCK_50,
reset,
HS,
VS,
blank,
row,
col
);
input wire CLOCK_50;
input wire reset;
output wire HS;
output wire VS;
output wire blank;
output wire [8:0] row;
output wire [9:0] col;
reg en_vs;
wire en_hs;
wire en_row;
wire en_col;
reg clear_vs;
wire clear_hs;
reg clear_row;
wire clear_c... |
tt07-finale_0283 | tt07-finale | wilfredkisku-tt07_wilfred_fp_mac | task_FP8_ADD | tt_um_fp_mac | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module FP8_MUL(
input [7:0] io_inputA,
input [7:0] io_inputB,
output [7:0] io_output
);
wire signA = io_inputA[7]; // @[FP8_MUL.scala 13:20]
wire [4:0] expA = io_inputA[6:2]; // @[FP8_MUL.scala 14:24]
wire [1:0] sigA = io_inputA[1:0]; // @[FP8_MUL.scala 15:27]
wire signB = io_in... | module FP8_ADD(
input [7:0] io_inputA,
input [7:0] io_inputB,
output [7:0] io_output
);
wire signA = io_inputA[7]; // @[FP8_ADD.scala 13:18]
wire [4:0] expA = io_inputA[6:2]; // @[FP8_ADD.scala 14:22]
wire [1:0] sigA = io_inputA[1:0]; // @[FP8_ADD.scala 15:25]
wire signB = io_inputB[7]; // @[FP8_ADD.s... |
tt07-finale_0284 | tt07-finale | wilfredkisku-tt07_wilfred_fp_mac | task_FP8_MUL | tt_um_fp_mac | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module FP8_MUL(
input [7:0] io_inputA,
input [7:0] io_inputB,
output [7:0] io_output
);
// >>> Module Implementation Begin
// <<< Module Implementation End
endmodule
module FP8_ADD(
input [7:0] io_inputA,
input [7:0] io_inputB,
output [7:0] io_output
);
wire signA = io_inpu... | module FP8_MUL(
input [7:0] io_inputA,
input [7:0] io_inputB,
output [7:0] io_output
);
wire signA = io_inputA[7]; // @[FP8_MUL.scala 13:20]
wire [4:0] expA = io_inputA[6:2]; // @[FP8_MUL.scala 14:24]
wire [1:0] sigA = io_inputA[1:0]; // @[FP8_MUL.scala 15:27]
wire signB = io_inputB[7]; // @[FP8_MUL.s... |
tt07-finale_0285 | tt07-finale | wilfredkisku-tt07_wilfred_fp_mac | task_tt_um_fp_mac | tt_um_fp_mac | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `default_nettype none
module FP8_MUL(
input [7:0] io_inputA,
input [7:0] io_inputB,
output [7:0] io_output
);
wire signA = io_inputA[7]; // @[FP8_MUL.scala 13:20]
wire [4:0] expA = io_inputA[6:2]; // @[FP8_MUL.scala 14:24]
wire [1:0] sigA = io_inputA[1:0]; // @[FP8_MUL.scala 15:27]
wire signB = io_in... | module tt_um_fp_mac(
input clk, // clock
input rst_n, // reset_n - low to reset
input [7:0] ui_in, // io_wgt
input [7:0] uio_in, // io_ifm
output [7:0] uo_out,
output [7:0] uio_out,
output [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input ena // a... |
tt08-finale_0286 | tt08-finale | AniruddhaRanade-TT08_VGA_CBTest | task_bitmap_rom | tt_um_vga_cbtest | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_vga_cbtest (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_ou... | module bitmap_rom (
input wire [6:0] x,
input wire [6:0] y,
output wire [2:0] pixel
);
reg [2:0] mem[2047:0];
initial begin
mem[0] = 3'd7;
mem[1] = 3'd7;
mem[2] = 3'd7;
mem[3] = 3'd7;
mem[4] = 3'd7;
mem[5] = 3'd7;
mem[6] = 3'd7;
mem[7] = 3'd7;
mem[8] = 3'd7;
mem[... |
tt08-finale_0287 | tt08-finale | AniruddhaRanade-TT08_VGA_CBTest | task_palette | tt_um_vga_cbtest | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_vga_cbtest (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_ou... | module palette (
input wire [2:0] color_index,
output wire [5:0] rrggbb
);
reg [5:0] palette[7:0];
initial begin
palette[0] = 6'b111000;
palette[1] = 6'b110110;
palette[2] = 6'b101101;
palette[3] = 6'b111000;
palette[4] = 6'b110011;
palette[5] = 6'b011111;
palette[6]... |
tt08-finale_0288 | tt08-finale | AniruddhaRanade-TT08_VGA_CBTest | task_tt_um_vga_cbtest | tt_um_vga_cbtest | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_vga_cbtest (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_ou... | module tt_um_vga_cbtest (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
... |
tt08-finale_0289 | tt08-finale | Bhavuk-HDL-tty8_comm_ic | task_tt_um_comm_ic_bhavuk | tt_um_comm_ic_bhavuk | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 Bhavuk (Github: Bhavuk-HDL)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_comm_ic_bhavuk (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_... | module tt_um_comm_ic_bhavuk (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
input wire... |
tt08-finale_0290 | tt08-finale | CEJMU-tt08_cejmu | task_cla_full_adder | tt_um_cejmu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.34+43 (git sha1 d21c464ae, clang 10.0.0-4ubuntu1 -fPIC -Os) */
(* keep = 1 *)
(* hdlname = "\\cla" *)
(* dynports = 1 *)
(* keep_hierarchy = 1 *)
(* src = "cla/cla.sv:3.1-50.10" *)
module \$paramod\cla\WIDTH=s32'00000000000000000000000000011000 (a, b, z);
(* src = "cla/cla.sv:32.33-32.4... | module cla_full_adder(a, b, ci, s, p, g);
(* src = "cla/cla_full_adder.sv:11.16-11.21" *)
wire _0_;
(* src = "cla/cla_full_adder.sv:12.16-12.21" *)
wire _1_;
(* src = "cla/cla_full_adder.sv:13.16-13.21" *)
wire _2_;
(* src = "cla/cla_full_adder.sv:13.16-13.26" *)
wire _3_;
(* src = "cla/cla_full_adder... |
tt08-finale_0291 | tt08-finale | CEJMU-tt08_cejmu | task_rca_fulladder | tt_um_cejmu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.34+43 (git sha1 d21c464ae, clang 10.0.0-4ubuntu1 -fPIC -Os) */
(* keep = 1 *)
(* hdlname = "\\cla" *)
(* dynports = 1 *)
(* keep_hierarchy = 1 *)
(* src = "cla/cla.sv:3.1-50.10" *)
module \$paramod\cla\WIDTH=s32'00000000000000000000000000011000 (a, b, z);
(* src = "cla/cla.sv:32.33-32.4... | module rca_fulladder(a, b, c_in, s, c_out);
(* src = "rca/rca_fulladder.sv:11.21-11.26" *)
wire _00_;
(* src = "rca/rca_fulladder.sv:11.31-11.45" *)
wire _01_;
(* src = "rca/rca_fulladder.sv:11.20-11.46" *)
wire _02_;
(* src = "rca/rca_fulladder.sv:10.16-10.21" *)
wire _03_;
(* src = "rca/rca_fulladde... |
tt08-finale_0292 | tt08-finale | CEJMU-tt08_cejmu | task_tt_um_cejmu | tt_um_cejmu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /* Generated by Yosys 0.34+43 (git sha1 d21c464ae, clang 10.0.0-4ubuntu1 -fPIC -Os) */
(* keep = 1 *)
(* hdlname = "\\cla" *)
(* dynports = 1 *)
(* keep_hierarchy = 1 *)
(* src = "cla/cla.sv:3.1-50.10" *)
module \$paramod\cla\WIDTH=s32'00000000000000000000000000011000 (a, b, z);
(* src = "cla/cla.sv:32.33-32.4... | module tt_um_cejmu(ui_in, uo_out, uio_in, uio_out, uio_oe, ena, clk, rst_n);
(* src = "tt_um_cejmu.sv:46.11-46.45" *)
wire _0_;
(* src = "tt_um_cejmu.sv:43.18-43.24" *)
wire _1_;
(* src = "tt_um_cejmu.sv:46.21-46.45" *)
wire _2_;
(* src = "tt_um_cejmu.sv:60.25-60.52" *)
wire [24:0] _3_;
(* src = "tt_u... |
tt08-finale_0293 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_D_FF | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module D_FF(clk, D, Q);
input wire clk, D;
output reg Q;
always@(posedge clk)begin
Q <= D;
end
endmodule |
tt08-finale_0294 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_LFSR | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module LFSR(clk, rst_n, lfsr);
input wire clk, rst_n;
output reg [30:0] lfsr;
always@(posedge clk or posedge rst_n) begin
if (rst_n == 1)
lfsr <= 31'd134995; // LFSR SEED AFFECTS ACCURACY A LOT
else begin
lfsr[0] <= lfsr[27] ^ lfsr[30] ;
lfsr[30:1] <= lfsr[29:0] ;
... |
tt08-finale_0295 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_SN_Generators | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module SN_Generators(lfsr, Input_1, Input_2, SN_Bit_1, SN_Bit_1_Input2, SN_Bit_2, SN_Bit_sel);
input wire [30:0] lfsr;
input wire [8:0] Input_1, Input_2;
output wire SN_Bit_1, SN_Bit_1_Input2, SN_Bit_2, SN_Bit_sel;
assign SN_Bit_1 = (lfsr[8:0] < Input_1[8:0]) ;
assign SN_Bit_1_Input2 = (lfsr[20:12] < Input_1[8:0]);
as... |
tt08-finale_0296 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_absolute_value | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module absolute_value(clk, SN_Bit_1, SN_Bit_Out);
input wire clk, SN_Bit_1;
output wire SN_Bit_Out;
wire SN_Bit_Q;
D_FF delay_1_SN_Bit(clk, SN_Bit_1, SN_Bit_Q);
assign SN_Bit_Out = !(SN_Bit_1 ^ SN_Bit_Q);
endmodule |
tt08-finale_0297 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_adder | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module adder(SN_Bit_1, SN_Bit_2, SN_Bit_sel, SN_Bit_Out);
input wire SN_Bit_1, SN_Bit_2, SN_Bit_sel;
output wire SN_Bit_Out;
assign SN_Bit_Out = (SN_Bit_sel == 0) ? SN_Bit_1 : SN_Bit_2;
endmodule |
tt08-finale_0298 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_input_checker | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module input_checker(input_precheck, output_postcheck);
input wire [8:0] input_precheck;
wire over_limit, under_limit, limit;
output wire [8:0] output_postcheck;
assign over_limit = (input_precheck > 9'b100001111);
assign under_limit = (input_precheck < 9'b011110001);
assign limit = (over_limit||under_limit) == 1;
as... |
tt08-finale_0299 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_multiplier | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module multiplier(SN_Bit_1, SN_Bit_2, SN_Bit_Out);
input wire SN_Bit_1, SN_Bit_2;
output wire SN_Bit_Out;
assign SN_Bit_Out = !(SN_Bit_1 ^ SN_Bit_2);
endmodule |
tt08-finale_0300 | tt08-finale | CL-123-abc-tt_um_stochastic_addmultiply_CL123abc | task_self_multiplier | tt_um_stochastic_addmultiply_CL123abc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | /*
* Copyright (c) 2024 CL-123-abc
* SPDX-License-Identifier: Apache-2.0
*/
/* Module name: tt_um_stochastic_addmultiply_CL123abc
* Module description:
* Stochastic adder, multiplier and self-multiplier that takes in 9-bit (+ 1 bit buffer) inputs and gives 9-bit (+ 1 bit buffer) outputs
* after 2^17+1 clock cyc... | module self_multiplier(clk, SN_Bit_Input1, SN_Bit_Input2, SN_Bit_Out);
input wire clk, SN_Bit_Input1, SN_Bit_Input2;
output wire SN_Bit_Out;
wire SN_Bit_Q;
D_FF delay_1_SN_Bit(clk, SN_Bit_Input1, SN_Bit_Q);
assign SN_Bit_Out = !(SN_Bit_Q ^ SN_Bit_Input2);
endmodule |
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