Add SDXL-Turbo W8A16 Hexagon NPU bundle (V75-native, fwd-compat V79/V81) + manifest
39ae3a9 verified | { | |
| "model": "sdxl-turbo", | |
| "pipeline": "StableDiffusionXLPipeline", | |
| "variant": "fp16-encoders + TAESDXL", | |
| "dsp_arch": 75, | |
| "skel": "libQnnHtpV75Skel.so", | |
| "qairt_runtime_required": "2.40", | |
| "quantization": "W8A16", | |
| "resolution": 1024, | |
| "latent": [1, 4, 128, 128], | |
| "scheduler": "EulerAncestralDiscrete", | |
| "steps_default": 4, | |
| "guidance_scale": 0.0, | |
| "cross_attention_dim": 2048, | |
| "vae_scaling_factor": 0.13025, | |
| "text_encoders": { | |
| "text_encoder_1": "CLIP-L (penultimate, hidden -2) -> [1,77,768]", | |
| "text_encoder_2": "OpenCLIP-bigG (+projection) -> last_hidden [1,77,1280] + pooled [1,1280]" | |
| }, | |
| "text_embedding": "concat CLIP-L[768] ++ bigG[1280] -> [1,77,2048]", | |
| "host_emb": "sdxl_emb_mlp.bin -> emb[1,1280] per step (fold-proofs timestep + add_time)", | |
| "vae": "TAESDXL CPU tiny-VAE (taesdxl_decoder.mnn) via --vae_mnn, SDXL_VAE_BACKEND=cpu", | |
| "graph_name": "model", | |
| "io_contract": "ours-sdxl-emb" | |
| } | |