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Add SDXL-Turbo W8A16 Hexagon NPU bundle (V75-native, fwd-compat V79/V81) + manifest

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.gitattributes CHANGED
@@ -33,3 +33,4 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
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  *tfevents* filter=lfs diff=lfs merge=lfs -text
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+ v75/taesdxl_decoder.mnn filter=lfs diff=lfs merge=lfs -text
README.md ADDED
@@ -0,0 +1,110 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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+ ---
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+ license: other
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+ license_name: stabilityai-ai-community
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+ license_link: https://huggingface.co/stabilityai/sdxl-turbo/blob/main/LICENSE.md
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+ tags:
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+ - stable-diffusion-xl
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+ - sdxl-turbo
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+ - qnn
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+ - hexagon
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+ - npu
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+ - w8a16
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+ - text-to-image
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+ - tokforge
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+ pipeline_tag: text-to-image
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+ library_name: qnn
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+ inference: false
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+ ---
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+
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+ # TokForge SDXL-Turbo · Hexagon NPU (W8A16)
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+
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+ **PRIVATE** model bundle for the **TokForge** Android app (`dev.tokforge`). This repo hosts the
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+ **SDXL-Turbo** image-generation pipeline compiled to **QNN context binaries** for the
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+ **Qualcomm Hexagon DSP (HTP)**, so TokForge can fetch the SDXL-NPU "Faithful" backend from scratch
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+ (previously hand-staged on devices only).
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+
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+ Sibling of [`darkmaniac7/TokForge-SD15-QNN-NPU`](https://huggingface.co/darkmaniac7/TokForge-SD15-QNN-NPU)
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+ (SD1.5). Same non-root `untrusted_app` cDSP recipe; this is the higher-quality 1024px tier.
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+
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+ ## What this is
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+
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+ - **Model:** SDXL-Turbo (few-step distilled SDXL), native **1024×1024** (128×128 latent).
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+ - **Quantization:** **W8A16** (8-bit weights, 16-bit activations) on the Hexagon HTP.
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+ - **Runtime:** **QAIRT 2.40**. Bin set is **V75-native** (`libQnnHtpV75Skel.so`).
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+ - **Variant:** **fp16 text encoders + TAESDXL** tiny-VAE (see below).
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+ - **Footprint:** **~4.3 GB** on disk (the on-device fresh download is this big).
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+
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+ ## Pipeline / variant
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+
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+ This bundle is the **fp16-encoders + TAESDXL** variant the `libsdxl_qnn_driver` runs end-to-end
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+ (no host orchestration beyond the emb-MLP):
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+
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+ | Stage | File | Where it runs |
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+ |-------|------|---------------|
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+ | CLIP-L text encoder | `text_encoder_1_fp16.bin` | DSP (fp16) → `last_hidden [1,77,768]` |
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+ | OpenCLIP-bigG text encoder (+proj) | `text_encoder_2_fp16.bin` | DSP (fp16) → `last_hidden [1,77,1280]` + `pooled [1,1280]` |
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+ | text_embedding | concat → `[1,77,2048]` | driver |
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+ | combined-emb MLP | `sdxl_emb_mlp.bin` | **host CPU** → `emb [1,1280]` per step |
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+ | UNet (EulerAncestral, 4 steps, guidance 0) | `unet.bin` (2.6 GB) | DSP |
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+ | VAE decode (1024px) | `taesdxl_decoder.mnn` (2.4 MB) | **CPU** (MNN tiny-VAE) |
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+
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+ **Why the host emb-MLP:** qairt-converter 2.40 constant-folds SDXL's two sinusoidal paths
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+ (`time_proj` and `add_time_proj`). The driver dodges both by precomputing the **combined**
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+ `emb = time_embedding(time_proj(t)) + add_embedding(cat(pooled, add_time_proj(time_ids)))` on host
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+ (weights in `sdxl_emb_mlp.bin`) and feeding it as ONE float UNet input, so no foldable path remains.
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+
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+ **Why TAESDXL CPU VAE:** it is the **only validated** VAE path. The DSP VAE is blocked at 1024px on
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+ V75 (unsigned-PD HTP cap) and the OpenCL/Vulkan VAE SIGSEGVs Adreno in `Session::resize`. The driver
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+ always selects `--vae_mnn` + `SDXL_VAE_BACKEND=cpu`.
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+
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+ **SDXL-Turbo is guidance-free** (`guidance_scale 0`): NO CFG → one UNet pass per step. EulerAncestral,
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+ 4 steps native (6 for quality), VAE scaling factor **0.13025**.
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+
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+ ## Arch coverage & verification
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+
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+ | Set | dsp_arch | Skel | Verified |
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+ |-----|----------|------|----------|
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+ | `ours/v75` | 75 (V75) | `libQnnHtpV75Skel.so` | **YES** — device-verified coherent+crisp on Lenovo **SM8650/V75** (.69) |
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+
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+ **Forward-compat:** a lower-arch bin runs on a higher-arch DSP. The **V75-native** set is the
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+ shipping set for **V73 → V81**, and was **verified by forward-compat on V81** (RedMagic **SM8850**
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+ handsets .82 and .80, coherent+crisp). **Native V81/V79 SDXL bins are NOT separately built** — V75-native
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+ is the single own-built set today.
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+
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+ | SoC class | Hexagon | Status |
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+ |-----------|---------|--------|
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+ | 8 Gen 2 / 8s Gen 3 (SM8550/SM8635) | V73 | covered by V75-native forward-compat (untested on device) |
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+ | 8 Gen 3 (SM8650) | V75 | **device-verified** |
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+ | 8 Elite (SM8750) | V79 | forward-compat (untested on V79 silicon) |
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+ | 8 Elite Gen 5 (SM8850) | V81 | **forward-compat verified** (.82, .80) |
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+
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+ ## Provenance
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+
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+ Clean-room conversion, our own pipeline (no third-party NPU bins):
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+
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+ 1. **Base:** `stabilityai/sdxl-turbo` (fp16 safetensors) → ONNX export (UNet emb-input/fold-proofed
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+ graph, dual CLIP encoders, TAESDXL decoder).
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+ 2. **Quantize:** **W8A16** via QAIRT (calibration set), graph name `model`.
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+ 3. **Compile:** `qnn-context-binary-generator` → V75 HTP context binaries (**QAIRT 2.40**).
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+ 4. **VAE:** TAESDXL exported to a CPU MNN model (`taesdxl_decoder.mnn`).
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+
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+ ## License
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+
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+ **SDXL-Turbo — Stability AI Community License** (`stabilityai/sdxl-turbo`).
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+
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+ - Commercial use **permitted** for organizations/individuals with **< $1M USD annual revenue**.
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+ - Above $1M revenue requires a **Stability AI Enterprise license**.
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+ - **Attribution + license text must be retained** with the model.
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+ - This is **NOT** OpenRAIL-M (that covers the sibling SD1.5 bundle).
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+
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+ Text encoder bases: OpenCLIP bigG (MIT-class), OpenAI CLIP-L (MIT).
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+
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+ ## Files
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+
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+ See `manifest.json` for the authoritative file set with per-file md5 + size. The app reads
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+ `manifest.json`, resolves the device Hexagon arch, downloads the matching set into
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+ `filesDir/image_models/SDXL-QNN-NPU/`, and the `libsdxl_qnn_driver` loads the bins flat from there.
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+
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+ **Driver-required files** (every one must be present + non-empty for a usable bundle):
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+ `unet.bin`, `text_encoder_1_fp16.bin`, `text_encoder_2_fp16.bin`, `sdxl_emb_mlp.bin`,
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+ `taesdxl_decoder.mnn`, `tokenizer/{vocab.json,merges.txt}`, `tokenizer_2/{vocab.json,merges.txt}`.
manifest.json ADDED
@@ -0,0 +1,171 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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+ {
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+ "schema": "tokforge-sdxl-qnn-npu/manifest@1",
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+ "model": "sdxl-turbo",
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+ "variant": "fp16-encoders + TAESDXL",
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+ "license": "Stability AI Community License (SDXL-Turbo)",
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+ "license_note": "Commercial use permitted for orgs/individuals with < $1M USD annual revenue; above that requires a Stability AI Enterprise license. Attribution + license text must be retained with the model. NOT OpenRAIL (that was SD1.5).",
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+ "generated": "2026-06-05T03:08:58Z",
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+ "repo": "darkmaniac7/TokForge-SDXL-QNN-NPU (PRIVATE)",
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+ "notes": [
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+ "App reads the device Hexagon arch (dsp_arch) and picks the matching set. SDXL ships ONE own-built set today: V75-native (ours).",
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+ "Forward-compat: a lower-arch bin runs on a higher-arch DSP. The V75-native SDXL set is forward-compat to V79/V81 silicon (verified on the V81 SM8850 handset, .82 + .80). NATIVE V81/V79 SDXL bins are NOT separately built yet.",
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+ "source=ours: our own clean-room SDXL-Turbo -> W8A16 -> QAIRT 2.40 conversion, drop-in for our libsdxl_qnn_driver (graph name 'model', host combined-emb input). There is no AI-Hub SDXL set in this repo.",
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+ "verified=true means run on real silicon and confirmed coherent+crisp. verified=false = produced + offline-validated but NEEDS a handset before NPU-enabling.",
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+ "VAE path: TAESDXL CPU tiny-VAE (taesdxl_decoder.mnn, 2.4 MB) via --vae_mnn / SDXL_VAE_BACKEND=cpu. The DSP VAE is blocked at 1024px on V75 (unsigned-PD HTP cap) and the OpenCL/Vulkan VAE SIGSEGVs Adreno in Session::resize. CPU TAESDXL is the ONLY validated VAE path.",
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+ "On-device fresh download is ~4.3 GB (4,308,394,979 bytes): unet.bin 2.6 GB + text_encoder_2_fp16 1.4 GB + text_encoder_1_fp16 235 MB + sdxl_emb_mlp 29 MB + taesdxl 2.4 MB + tokenizers/config."
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+ ],
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+ "arch_to_socs": {
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+ "73": {
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+ "name": "Hexagon V73",
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+ "socs": [
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+ "SM8550 (Snapdragon 8 Gen 2)",
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+ "SM8635 (8s Gen 3)",
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+ "SM7475 (7+ Gen 3)"
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+ ]
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+ },
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+ "75": {
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+ "name": "Hexagon V75",
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+ "socs": [
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+ "SM8650 (Snapdragon 8 Gen 3)",
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+ "SM7675 (7 Gen 4)"
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+ ]
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+ },
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+ "79": {
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+ "name": "Hexagon V79",
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+ "socs": [
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+ "SM8750 (Snapdragon 8 Elite)",
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+ "SM8750-AB (8 Elite for Galaxy)"
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+ ]
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+ },
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+ "81": {
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+ "name": "Hexagon V81",
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+ "socs": [
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+ "SM8850 (Snapdragon 8 Elite Gen 5)"
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+ ]
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+ }
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+ },
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+ "io_contracts": {
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+ "ours-sdxl-emb": {
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+ "graph_name": "model",
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+ "unet_inputs": {
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+ "sample": "[1,4,128,128] UFIXED16 (NCHW, raw scheduler latent)",
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+ "emb": "[1,1280] UFIXED16 host combined-emb = time_embedding(time_proj(t)) + add_embedding(cat(pooled, add_time_proj(time_ids))); computed host-side via sdxl_emb_mlp.bin to fold-proof BOTH sinusoidal paths qairt-converter 2.40 would constant-fold",
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+ "text_embedding": "[1,77,2048] UFIXED16 = concat CLIP-L last_hidden[1,77,768] ++ bigG last_hidden[1,77,1280]"
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+ },
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+ "unet_output": "output [1,4,128,128] UFIXED16",
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+ "text_encoder_1": "CLIP-L: in input_ids INT32 [1,77] -> out last_hidden [1,77,768] (penultimate, hidden -2)",
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+ "text_encoder_2": "OpenCLIP-bigG (+projection): in input_ids INT32 [1,77] -> out last_hidden [1,77,1280] + pooled [1,1280] (pooled feeds the host emb compute)",
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+ "vae": "TAESDXL CPU tiny-VAE (taesdxl_decoder.mnn), in latent [1,4,128,128] -> out [1,3,1024,1024]; CPU MNN path only (SDXL_VAE_BACKEND=cpu)",
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+ "scheduler": "EulerAncestralDiscrete, trailing spacing, epsilon prediction, 4 steps native, guidance_scale 0 (NO CFG -> ONE UNet pass per step)",
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+ "vae_scaling_factor": 0.13025,
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+ "resolution": 1024,
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+ "driver": "libsdxl_qnn_driver.so (#51 ImageGenerationSdxlNpuCliHelper); flags --text_encoder_1/--text_encoder_2/--unet/--vae_mnn/--emb_mlp/--vocab_1/--merges_1/--vocab_2/--merges_2/--backend/--system_library; env SDXL_VAE_BACKEND=cpu"
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+ }
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+ },
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+ "sets": {
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+ "ours/v75": {
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+ "source": "ours",
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+ "dsp_arch": 75,
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+ "representative_soc": "SM8650 (Snapdragon 8 Gen 3)",
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+ "soc_model": 57,
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+ "qairt_runtime_required": "2.40",
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+ "skel": "libQnnHtpV75Skel.so",
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+ "io_contract": "ours-sdxl-emb",
74
+ "verified": true,
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+ "verify_note": "Device-verified coherent+crisp on Lenovo SM8650/V75 (.69), EulerAncestral, 4-6 steps. Forward-compat verified: these exact V75-native bins also ran coherent+crisp on the RedMagic SM8850/V81 handset (.82) and a second V81 (.80). Native-V81/V79 SDXL bins NOT separately built; V75-native is the shipping set for V73->V81.",
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+ "files": {
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+ "unet.bin": {
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+ "path": "v75/unet.bin",
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+ "size": 2637398016,
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+ "md5": "d7be73631e7c2a57875517c9af09dbe8"
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+ "unet.bin",
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+ "text_encoder_1_fp16.bin",
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+ "text_encoder_2_fp16.bin",
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+ "sdxl_emb_mlp.bin",
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+ "taesdxl_decoder.mnn"
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+ ],
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+ "bundle_dir_name": "SDXL-QNN-NPU",
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+ "model_id": "image-sdxl-qnn-npu",
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+ "total_bytes": 4308394979,
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+ "total_human": "4.31 GB (4.01 GiB)"
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+ }
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+ {
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+ "model": "sdxl-turbo",
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+ "pipeline": "StableDiffusionXLPipeline",
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+ "variant": "fp16-encoders + TAESDXL",
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+ "dsp_arch": 75,
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+ "skel": "libQnnHtpV75Skel.so",
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+ "qairt_runtime_required": "2.40",
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+ "quantization": "W8A16",
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+ "resolution": 1024,
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+ "latent": [1, 4, 128, 128],
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+ "scheduler": "EulerAncestralDiscrete",
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+ "vae_scaling_factor": 0.13025,
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+ "text_encoder_1": "CLIP-L (penultimate, hidden -2) -> [1,77,768]",
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+ "text_encoder_2": "OpenCLIP-bigG (+projection) -> last_hidden [1,77,1280] + pooled [1,1280]"
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+ },
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+ "text_embedding": "concat CLIP-L[768] ++ bigG[1280] -> [1,77,2048]",
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+ "host_emb": "sdxl_emb_mlp.bin -> emb[1,1280] per step (fold-proofs timestep + add_time)",
22
+ "vae": "TAESDXL CPU tiny-VAE (taesdxl_decoder.mnn) via --vae_mnn, SDXL_VAE_BACKEND=cpu",
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+ "graph_name": "model",
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+ "io_contract": "ours-sdxl-emb"
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The diff for this file is too large to render. See raw diff
 
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