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"schema": "tokforge-sdxl-qnn-npu/manifest@1",
"model": "realvisxl-v4.0-lightning",
"variant": "fp16-encoders + TAESDXL",
"scheduler": "EulerDiscrete",
"native_steps": 6,
"license": "openrail++",
"license_note": "RealVisXL V4.0 Lightning is released under the CreativeML OpenRAIL++-M license. Commercial use permitted; no revenue cap (unlike the prior SDXL-Turbo Stability AI Community License). Use-based restrictions per the OpenRAIL++ schedule apply.",
"generated": "2026-06-06T00:00:00Z",
"repo": "darkmaniac7/TokForge-SDXL-QNN-NPU",
"notes": [
"vc410: 'Faithful' NPU tier = RealVisXL-v4.0-Lightning, replacing cursed base SDXL-Turbo (few-step distillation -> fused heads / doubled bodies). Bin-only swap on the SAME W8A16 NPU recipe + IO contract; the driver default scheduler flips EulerAncestral -> EulerDiscrete (Lightning is distilled for deterministic few-step Euler) and native steps 4 -> 6.",
"App reads the device Hexagon arch (dsp_arch) and picks the matching native set. Four native sets ship: v73/v75/v79/v81. Forward-compat still applies (a lower-arch bin runs on a higher-arch DSP) as a fallback.",
"source=ours: clean-room RealVisXL -> W8A16 -> QAIRT 2.40 conversion, drop-in for our libsdxl_qnn_driver (graph name 'model', host combined-emb input).",
"verified=true = run on real silicon and confirmed coherent (no body-horror). V75 (Lenovo .69) + V81 (RedMagic .82) device-verified. v73/v79 offline-validated, awaiting handsets.",
"The 4 per-arch bins (unet/text_encoder_1_fp16/text_encoder_2_fp16/sdxl_emb_mlp) are the only RealVisXL swap; taesdxl_decoder.mnn (universal SDXL tiny-VAE) + the dual CLIP tokenizers + config are checkpoint-agnostic and byte-identical to the prior set."
],
"arch_to_socs": {
"73": {
"name": "Hexagon V73",
"socs": [
"SM8550 (Snapdragon 8 Gen 2)",
"SM8635 (8s Gen 3)",
"SM7475 (7+ Gen 3)"
]
},
"75": {
"name": "Hexagon V75",
"socs": [
"SM8650 (Snapdragon 8 Gen 3)",
"SM7675 (7 Gen 4)"
]
},
"79": {
"name": "Hexagon V79",
"socs": [
"SM8750 (Snapdragon 8 Elite)",
"SM8750-AB (8 Elite for Galaxy)"
]
},
"81": {
"name": "Hexagon V81",
"socs": [
"SM8850 (Snapdragon 8 Elite Gen 5)"
]
}
},
"io_contracts": {
"ours-sdxl-emb": {
"graph_name": "model",
"unet_inputs": {
"sample": "[1,4,128,128] UFIXED16 (NCHW, raw scheduler latent)",
"emb": "[1,1280] UFIXED16 host combined-emb = time_embedding(time_proj(t)) + add_embedding(cat(pooled, add_time_proj(time_ids))); computed host-side via sdxl_emb_mlp.bin",
"text_embedding": "[1,77,2048] UFIXED16 = concat CLIP-L last_hidden[1,77,768] ++ bigG last_hidden[1,77,1280]"
},
"unet_output": "output [1,4,128,128] UFIXED16",
"text_encoder_1": "CLIP-L: in input_ids INT32 [1,77] -> out last_hidden [1,77,768] (penultimate, hidden -2)",
"text_encoder_2": "OpenCLIP-bigG (+projection): in input_ids INT32 [1,77] -> out last_hidden [1,77,1280] + pooled [1,1280]",
"vae": "TAESDXL CPU tiny-VAE (taesdxl_decoder.mnn), in latent [1,4,128,128] -> out [1,3,1024,1024]; CPU MNN path only (SDXL_VAE_BACKEND=cpu)",
"scheduler": "EulerDiscrete (deterministic, sigma_up=0), trailing spacing, epsilon prediction, 6 steps native, guidance_scale 0 (NO CFG -> ONE UNet pass per step)",
"vae_scaling_factor": 0.13025,
"resolution": 1024,
"driver": "libsdxl_qnn_driver.so (#51 ImageGenerationSdxlNpuCliHelper); flags --text_encoder_1/--text_encoder_2/--unet/--vae_mnn/--emb_mlp/--vocab_1/--merges_1/--vocab_2/--merges_2/--backend/--system_library; env SDXL_VAE_BACKEND=cpu"
}
},
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"soc_model": 43,
"qairt_runtime_required": "2.40",
"skel": "libQnnHtpV73Skel.so",
"io_contract": "ours-sdxl-emb",
"verified": false,
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} |