root commited on
Commit
65158f7
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1 Parent(s): a006edb

compatible with L40

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Files changed (1) hide show
  1. vllm_hacked/v1/sample/sampler.py +1 -0
vllm_hacked/v1/sample/sampler.py CHANGED
@@ -103,6 +103,7 @@ class Sampler(nn.Module):
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  # logits = scores_processed
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  # # logits = logits_processor_stage1(logits)
 
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  if logits.dim() == 1 or (logits.size(0) != sampling_metadata.top_k.size(0)):
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  batch_size = sampling_metadata.top_k.size(0)
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  # 1. ζž„ι€ ε‡ηš„ι‡‡ζ ·η»“ζžœ (batch_size,)
 
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  # logits = scores_processed
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  # # logits = logits_processor_stage1(logits)
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+ print("logits.shape:", logits.shape)
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  if logits.dim() == 1 or (logits.size(0) != sampling_metadata.top_k.size(0)):
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  batch_size = sampling_metadata.top_k.size(0)
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  # 1. ζž„ι€ ε‡ηš„ι‡‡ζ ·η»“ζžœ (batch_size,)