# AXI4-Lite Protocol Definition — UVM TB Generator
protocol: axi4lite
description: AXI4-Lite — simplified address-only bus
tags: [bus, memory-mapped, synchronous, AMBA]

interface_template:
  signals:
    # Write address channel
    - {name: awvalid, direction: input,  width: 1, description: Write address valid}
    - {name: awready, direction: output, width: 1, description: Write address ready}
    - {name: awaddr,  direction: input,  width: 32, description: Write address}
    - {name: awprot,  direction: input,  width: 3, description: Protection type}
    # Write data channel
    - {name: wvalid,  direction: input,  width: 1, description: Write data valid}
    - {name: wready,  direction: output, width: 1, description: Write data ready}
    - {name: wdata,   direction: input,  width: 32, description: Write data}
    - {name: wstrb,   direction: input,  width: 4, description: Write strobes}
    # Write response channel
    - {name: bvalid,  direction: output, width: 1, description: Write response valid}
    - {name: bready,  direction: input,  width: 1, description: Write response ready}
    - {name: bresp,   direction: output, width: 2, description: Write response}
    # Read address channel
    - {name: arvalid, direction: input,  width: 1, description: Read address valid}
    - {name: arready, direction: output, width: 1, description: Read address ready}
    - {name: araddr,  direction: input,  width: 32, description: Read address}
    - {name: arprot,  direction: input,  width: 3, description: Protection type}
    # Read data channel
    - {name: rvalid,  direction: output, width: 1, description: Read data valid}
    - {name: rready,  direction: input,  width: 1, description: Read data ready}
    - {name: rdata,   direction: output, width: 32, description: Read data}
    - {name: rresp,   direction: output, width: 2, description: Read response}

config_parameters:
  - {name: ADDR_WIDTH, type: int, default: 32, enum: [12, 16, 32]}
  - {name: DATA_WIDTH, type: int, default: 32, enum: [32, 64]}

register_template:
  - name: AXI_CTRL
    address: 0x0000
    access: rw
    fields:
      - {name: enable,  bits: 0, description: Core enable}
      - {name: irq_en,  bits: 1, description: Interrupt enable}
  - name: AXI_STATUS
    address: 0x0004
    access: ro
    fields:
      - {name: ready,   bits: 0, description: Core ready}
      - {name: error,   bits: 1, description: Error detected}

sequence_template:
  name: axi4lite_sequence
  body: |
    // AXI4-Lite read-modify-write sequence
    drv.axi_read_reg(base_addr + offset, read_data);
    read_data[field] = value;
    drv.axi_write_reg(base_addr + offset, read_data);

coverage_template:
  - name: axi_cg
    type: covergroup
    items:
      - {name: cg_resp, type: coverpoint, expression: {bresp, rresp}}
      - {name: cg_addr, type: coverpoint, expression: {awaddr, araddr}}