Address review: register metadata engine, coverage wiring, virtual seqr fix, Xcelium wrapper, generic RAL access

Fix: add width→bits alias to FieldDef for RTL parser compat

Add DesignSpec.model_rebuild() for Pydantic v2 forward refs

Fix FieldDef missing after bad edit; add Dashboard iframe to FileViewer

Fix Pydantic validation: coerce int→str for reset/reset_value, str→int for width

Phase 3: IP-XACT, CI/CD, VCS/Questa wrappers, rich dashboard

Phase 3: Compile correctness + RAL consistency + test mapping + quality scoring + auto-fix suggestions

Accept width as alias for bits in FieldDef

feat: Advanced ML V2 Model with Reinforcement Learning

feat: Add actual AI/ML capabilities with LLM, semantic embeddings, and reinforcement learning

feat: Add enhanced ML model with retrieval-augmented generation

Initial commit: UVM testbench generator with coverage-driven auto-training