Initial commit: UVM testbench generator with coverage-driven auto-training

.env.example

@@ -0,0 +1,17 @@
+# Production environment variables for UVM TB Generator
+# Copy to .env and fill in secrets
+
+# Backend
+UVMGEN_LOG_LEVEL=info
+UVMGEN_OUTPUT_DIR=/app/output
+UVMGEN_SIMULATOR=stub
+
+# Frontend
+REACT_APP_API_URL=http://localhost:8000
+
+# Security (change in production)
+UVMGEN_SECRET_KEY=change-me-in-production
+UVMGEN_CORS_ORIGINS=http://localhost:3000,http://localhost
+
+# MLflow (optional)
+# UVMGEN_MLFLOW_TRACKING_URI=http://mlflow:5000

.github/workflows/ci.yml

@@ -0,0 +1,153 @@
+name: CI — UVM TB Generator
+
+on:
+  push:
+    branches: [main, develop]
+    paths-ignore: ["docs/**", "README.md"]
+  pull_request:
+    branches: [main]
+  workflow_dispatch:
+
+env:
+  PYTHON_VERSION: "3.11"
+
+jobs:
+  lint:
+    name: Lint & Format Check
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: ${{ env.PYTHON_VERSION }}
+      - name: Install dependencies
+        run: |
+          pip install flake8 black yamllint
+          pip install -r requirements.txt
+      - name: Run flake8
+        run: flake8 src/ tests/ --max-line-length=120 --extend-ignore=E203
+      - name: Run yamllint on configs and protocols
+        run: yamllint configs/ protocols/
+
+  test:
+    name: Tests (Python ${{ matrix.python-version }})
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        python-version: ["3.10", "3.11", "3.12"]
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: ${{ matrix.python-version }}
+      - name: Install dependencies
+        run: |
+          pip install pytest pytest-cov
+          pip install -r requirements.txt
+      - name: Run tests with coverage
+        run: |
+          python -m pytest tests/ -v --cov=src --cov-report=xml --cov-report=term-missing
+      - name: Upload coverage
+        uses: codecov/codecov-action@v5
+        with:
+          file: ./coverage.xml
+          fail_ci_if_error: false
+
+  generate:
+    name: Generation Smoke Test
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: ${{ env.PYTHON_VERSION }}
+      - name: Install dependencies
+        run: |
+          pip install -r requirements.txt
+      - name: Generate from YAML spec
+        run: |
+          python -m src.main --spec configs/uart_demo.yaml --json
+      - name: Generate from .core file
+        run: |
+          python -m src.main --spec configs/uart16550-1.5.core --json
+      - name: Verify output files exist
+        run: |
+          test -d output/uart_tb
+          test -f output/uart_tb/testbench.sv
+          test -f output/uart_tb/interface_uart.sv
+          test -d output/uart16550_tb
+          test -f output/uart16550_tb/testbench.sv
+          echo "All output files verified"
+      - name: Verify API server imports
+        run: |
+          python -c "from src.api.server import app; print('API server OK')"
+
+  regression:
+    name: Multi-Seed Regression Test
+    runs-on: ubuntu-latest
+    needs: [generate]
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: ${{ env.PYTHON_VERSION }}
+      - name: Install dependencies
+        run: |
+          pip install -r requirements.txt
+      - name: Run auto-training with 3 seeds
+        run: |
+          python -m src.main --spec configs/uart16550-1.5.core --auto-train \
+            --max-iterations 3 --coverage-target 75 --simulator stub
+      - name: Export coverage trend
+        run: |
+          python -c "
+          import json
+          from pathlib import Path
+          trend_file = next(Path('output').rglob('*coverage_trend*'), None)
+          if trend_file:
+              print('Coverage trend:')
+              print(trend_file.read_text())
+          else:
+              # Show registry content
+              reg_dir = Path('output') / 'model_registry'
+              if reg_dir.exists():
+                  versions = sorted(reg_dir.iterdir())
+                  print(f'Versions: {[v.name for v in versions]}')
+          " || true
+      - name: Verify FuseSoC .core file generated
+        run: |
+          test -f output/uart16550_tb/uart16550.core && echo "FuseSoC .core found" || echo "No FuseSoC core"
+
+  schema:
+    name: Schema Validation
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: ${{ env.PYTHON_VERSION }}
+      - name: Install deps
+        run: pip install pyyaml jsonschema
+      - name: Validate demo specs against schema
+        run: |
+          python -c "
+import json, yaml, sys
+from jsonschema import validate
+
+with open('configs/schema/master_schema.json') as f:
+    schema = json.load(f)
+
+for spec_file in ['configs/uart_demo.yaml', 'configs/uart16550-1.5.core']:
+    with open(spec_file) as f:
+        if spec_file.endswith('.core'):
+            # .core files wrap spec in a different format; validate the relevant parts
+            data = yaml.safe_load(f)
+        else:
+            data = yaml.safe_load(f)
+    try:
+        validate(instance=data, schema=schema)
+        print(f'OK: {spec_file} passes schema')
+    except Exception as e:
+        print(f'FAIL: {spec_file} — {e}')
+        sys.exit(1)
+"

.github/workflows/release.yml

@@ -0,0 +1,25 @@
+name: Release
+
+on:
+  push:
+    tags: ["v*"]
+
+jobs:
+  release:
+    runs-on: ubuntu-latest
+    permissions:
+      contents: write
+    steps:
+      - uses: actions/checkout@v4
+      - uses: actions/setup-python@v5
+        with:
+          python-version: "3.11"
+      - name: Build package
+        run: |
+          pip install build
+          python -m build
+      - name: Create GitHub Release
+        uses: softprops/action-gh-release@v2
+        with:
+          files: dist/*
+          generate_release_notes: true

.gitignore

@@ -0,0 +1,27 @@
+__pycache__/
+*.pyc
+*.pyo
+.pytest_cache/
+.coverage
+htmlcov/
+.env
+.env.local
+output/
+logs/
+model_registry/
+models/saved/
+!frontend/build/.gitkeep
+*.egg-info/
+dist/
+build/
+.DS_Store
+*.log
+*.pid
+*.sock
+node_modules/
+frontend/build/
+.mypy_cache/
+.ruff_cache/
+.venv/
+venv/
+

.pre-commit-config.yaml

@@ -0,0 +1,38 @@
+repos:
+  - repo: https://github.com/pre-commit/pre-commit-hooks
+    rev: v5.0.0
+    hooks:
+      - id: trailing-whitespace
+      - id: end-of-file-fixer
+      - id: check-yaml
+      - id: check-json
+      - id: check-added-large-files
+      - id: detect-private-key
+      - id: check-merge-conflict
+
+  - repo: https://github.com/psf/black
+    rev: 25.1.0
+    hooks:
+      - id: black
+        language_version: python3.11
+
+  - repo: https://github.com/PyCQA/flake8
+    rev: 7.1.2
+    hooks:
+      - id: flake8
+        args: [--max-line-length=120, --extend-ignore=E203,W503]
+        additional_dependencies: [flake8]
+
+  - repo: https://github.com/pre-commit/mirrors-mypy
+    rev: v1.15.0
+    hooks:
+      - id: mypy
+        args: [--ignore-missing-imports, --follow-imports=silent]
+        additional_dependencies: [pydantic]
+
+  - repo: https://github.com/PyCQA/bandit
+    rev: 1.8.3
+    hooks:
+      - id: bandit
+        args: [--skip=B101, --recursive, src/]
+        additional_dependencies: [bandit]

Dockerfile

@@ -0,0 +1,40 @@
+# Multi-stage: frontend build + Python backend
+
+# Stage 1: Build React frontend
+FROM node:20-alpine AS frontend-builder
+WORKDIR /app
+COPY frontend/package.json frontend/package-lock.json ./
+RUN npm ci --omit=dev
+COPY frontend/ .
+RUN npm run build
+
+# Stage 2: Python backend
+FROM python:3.11-slim AS backend-builder
+
+RUN apt-get update && apt-get install -y --no-install-recommends \
+    iverilog \
+    && rm -rf /var/lib/apt/lists/*
+
+WORKDIR /app
+COPY requirements.txt .
+RUN pip install --no-cache-dir --upgrade pip && \
+    pip install --no-cache-dir -r requirements.txt
+
+COPY . .
+COPY --from=frontend-builder /app/build /app/frontend/build
+
+RUN pip install --no-cache-dir -e .
+
+RUN groupadd -r uvmgen && useradd -r -g uvmgen -d /app -s /sbin/nologin uvmgen
+RUN mkdir -p /app/output /app/logs /var/data && chown -R uvmgen:uvmgen /app /var/data
+
+EXPOSE 8000
+
+ENV UVMGEN_OUTPUT_DIR=/var/data/uvmgen_output
+
+HEALTHCHECK --interval=30s --timeout=5s --start-period=15s --retries=3 \
+    CMD python -c "import urllib.request; print(urllib.request.urlopen('http://localhost:8000/api/health').read().decode())"
+
+USER uvmgen
+
+CMD ["uvicorn", "src.api.server:app", "--host", "0.0.0.0", "--port", "8000", "--workers", "1", "--log-level", "info"]

Makefile

@@ -0,0 +1,32 @@
+.PHONY: install test clean run
+
+install:
+	pip install -r requirements.txt
+
+install-dev:
+	pip install -r requirements.txt -r requirements-dev.txt
+
+test:
+	python -m pytest tests/ -v --cov=src --cov-report=term-missing
+
+run:
+	python -m src.main --spec configs/uart_demo.yaml
+
+run-json:
+	python -m src.main --spec configs/uart_demo.yaml --json
+
+eval-only:
+	python -m src.main --spec configs/uart_demo.yaml --eval-only
+
+clean:
+	rm -rf output/* logs/* .pytest_cache __pycache__ */__pycache__ */*/__pycache__
+	rm -rf models/saved/*.json
+
+docker-build:
+	docker build -t uvm-tb-generator .
+
+docker-run:
+	docker run --rm -v $(PWD)/output:/app/output uvm-tb-generator --spec configs/uart_demo.yaml
+
+lint:
+	python -m flake8 src/ tests/

README.md

@@ -1 +1,31 @@
-# UVM-verification
+# UVM-verification
+
+Automated UVM testbench generation from YAML / `.core` specifications — with **protocol libraries**, **schema validation**, **coverage-driven auto-training**, and **CI/CD integration**.
+
+## Quick Start
+
+```bash
+pip install -r requirements.txt
+
+python -m src.main --spec configs/uart_demo.yaml
+python -m src.main --spec configs/uart16550-1.5.core
+python -m src.main --spec configs/uart16550-1.5.core --auto-train --max-iterations 3
+```
+
+## API Server
+
+```bash
+uvicorn src.api.server:app --host 0.0.0.0 --port 8000
+```
+
+## Frontend
+
+```bash
+cd frontend && npm install && npm run build
+```
+
+## Docker
+
+```bash
+docker-compose up --build
+```

configs/base_config.yaml

@@ -0,0 +1,26 @@
+# Base pipeline configuration — inherit + override per environment
+
+generation:
+  templates_dir: src/generation/templates
+  output_dir: output
+  overwrite: false
+  strict_validation: true
+
+evaluation:
+  enabled: true
+  metrics:
+    - completeness
+    - syntax_validity
+    - coverage_readiness
+  threshold: 0.7
+
+tracking:
+  enabled: false
+  backend: local
+  experiment_name: uvm_tb_generator
+  tracking_uri: null
+
+logging:
+  level: INFO
+  file: null
+  format: "%(asctime)s | %(levelname)-8s | %(name)s | %(message)s"

configs/logging.yaml

@@ -0,0 +1,25 @@
+version: 1
+formatters:
+  standard:
+    format: "%(asctime)s | %(levelname)-8s | %(name)s | %(message)s"
+handlers:
+  console:
+    class: logging.StreamHandler
+    level: INFO
+    formatter: standard
+    stream: ext://sys.stdout
+  file:
+    class: logging.handlers.RotatingFileHandler
+    level: DEBUG
+    formatter: standard
+    filename: logs/generator.log
+    maxBytes: 10485760
+    backupCount: 5
+loggers:
+  uvmgen:
+    level: DEBUG
+    handlers: [console, file]
+    propagate: no
+root:
+  level: INFO
+  handlers: [console]

configs/schema/master_schema.json

@@ -0,0 +1,219 @@
+{
+  "$schema": "https://json-schema.org/draft/2020-12/schema",
+  "$id": "https://github.com/your-org/uvm-tb-generator/schema/master_schema.json",
+  "title": "UVM TB Generator — Master Specification Schema",
+  "description": "Industry-grade schema for describing digital IP cores for automated UVM testbench generation. Supports multi-protocol, multi-clock, multi-power-domain designs.",
+  "type": "object",
+  "required": ["design_name", "interfaces"],
+
+  "definitions": {
+    "signal": {
+      "type": "object",
+      "required": ["name", "direction"],
+      "properties": {
+        "name":       { "type": "string", "pattern": "^[a-zA-Z_][a-zA-Z0-9_]*$", "description": "Signal name" },
+        "direction":  { "type": "string", "enum": ["input", "output", "inout"] },
+        "width":      { "type": "integer", "minimum": 1, "default": 1, "description": "Bus width in bits" },
+        "description":{ "type": "string" }
+      }
+    },
+
+    "field": {
+      "type": "object",
+      "required": ["name", "bits"],
+      "properties": {
+        "name":        { "type": "string", "pattern": "^[a-zA-Z_][a-zA-Z0-9_]*$" },
+        "bits":        { "type": "string", "pattern": "^([0-9]+|[0-9]+:[0-9]+)$", "description": "Single bit (e.g. '0') or range (e.g. '7:0')" },
+        "description": { "type": "string" },
+        "access":      { "type": "string", "enum": ["ro", "wo", "rw", "rc", "rs", "w1c"], "default": "rw" },
+        "reset":       { "type": "string", "description": "Reset value in hex (e.g. '0x00')" },
+        "hw_impl":     { "type": "boolean", "default": true, "description": "Hardware-implemented field" },
+        "sw_access":   { "type": "string", "enum": ["read-only", "write-only", "read-write", "read-clear"], "default": "read-write" }
+      }
+    },
+
+    "register": {
+      "type": "object",
+      "required": ["name", "address"],
+      "properties": {
+        "name":        { "type": "string", "pattern": "^[a-zA-Z_][a-zA-Z0-9_]*$" },
+        "address":     { "type": "string", "pattern": "^0x[0-9a-fA-F]+$", "description": "Hex address" },
+        "size":        { "type": "integer", "minimum": 1, "default": 1, "description": "Number of bytes" },
+        "access":      { "type": "string", "enum": ["ro", "wo", "rw", "rc", "rs", "w1c"], "default": "rw" },
+        "description": { "type": "string" },
+        "fields":      { "type": "array", "items": { "$ref": "#/definitions/field" } },
+        "reset_value": { "type": "string", "description": "Full register reset value (hex)" },
+        "volatile":    { "type": "boolean", "default": false }
+      }
+    },
+
+    "clock_domain": {
+      "type": "object",
+      "required": ["name"],
+      "properties": {
+        "name":     { "type": "string" },
+        "frequency":{ "type": "integer", "description": "Frequency in Hz" },
+        "primary":  { "type": "boolean", "default": false }
+      }
+    },
+
+    "reset_domain": {
+      "type": "object",
+      "required": ["name", "signal", "active"],
+      "properties": {
+        "name":   { "type": "string" },
+        "signal": { "type": "string" },
+        "active": { "type": "integer", "enum": [0, 1], "description": "0 = active-low, 1 = active-high" },
+        "async":  { "type": "boolean", "default": false }
+      }
+    },
+
+    "interface": {
+      "type": "object",
+      "required": ["name", "signals"],
+      "properties": {
+        "name":        { "type": "string", "pattern": "^[a-zA-Z_][a-zA-Z0-9_]*$" },
+        "protocol":    { "type": "string", "enum": ["uart", "spi", "i2c", "axi", "axi4", "axi4lite", "apb", "ahb", "wishbone", "custom"], "description": "Bus protocol standard" },
+        "direction":   { "type": "string", "enum": ["master", "slave", "monitor"], "default": "slave" },
+        "description": { "type": "string" },
+        "signals":     { "type": "array", "items": { "$ref": "#/definitions/signal" }, "minItems": 1 }
+      }
+    },
+
+    "interrupt": {
+      "type": "object",
+      "required": ["name", "signal"],
+      "properties": {
+        "name":      { "type": "string" },
+        "signal":    { "type": "string" },
+        "type":      { "type": "string", "enum": ["level", "edge", "pulse"], "default": "level" },
+        "sensitivity": { "type": "string", "enum": ["high", "low", "rising", "falling"], "default": "high" },
+        "description": { "type": "string" }
+      }
+    },
+
+    "memory_map": {
+      "type": "object",
+      "required": ["name", "base_address", "size"],
+      "properties": {
+        "name":         { "type": "string" },
+        "base_address": { "type": "string", "pattern": "^0x[0-9a-fA-F]+$" },
+        "size":         { "type": "integer", "description": "Size in bytes" },
+        "description":  { "type": "string" }
+      }
+    },
+
+    "coverage": {
+      "type": "object",
+      "properties": {
+        "bins":            { "type": "array", "items": { "type": "object", "properties": {
+          "name":           { "type": "string" },
+          "type":           { "type": "string", "enum": ["coverpoint", "cross", "assertion"] },
+          "expression":     { "type": "string" },
+          "description":    { "type": "string" }
+        }}}
+      }
+    },
+
+    "parameter": {
+      "type": "object",
+      "required": ["name", "type"],
+      "properties": {
+        "name":        { "type": "string" },
+        "type":        { "type": "string", "enum": ["int", "string", "bool", "float"], "default": "int" },
+        "default":     { "type": ["integer", "string", "boolean", "number"], "description": "Default value" },
+        "minimum":     { "type": ["integer", "number"] },
+        "maximum":     { "type": ["integer", "number"] },
+        "description": { "type": "string" }
+      }
+    },
+
+    "assertion": {
+      "type": "object",
+      "required": ["name", "expression"],
+      "properties": {
+        "name":        { "type": "string" },
+        "expression":  { "type": "string", "description": "SVA assertion expression" },
+        "severity":    { "type": "string", "enum": ["error", "warning", "info"], "default": "error" },
+        "description": { "type": "string" }
+      }
+    }
+  },
+
+  "properties": {
+    "design_name":  { "type": "string", "pattern": "^[a-zA-Z_][a-zA-Z0-9_]*$" },
+    "version":      { "type": "string", "description": "IP version (semver)" },
+    "vendor":       { "type": "string", "description": "IP vendor name" },
+    "description":  { "type": "string" },
+    "technology":   { "type": "string", "description": "Target technology (e.g. 28nm, FPGA)" },
+    "language":     { "type": "string", "enum": ["verilog", "vhdl", "systemverilog"], "default": "systemverilog" },
+
+    "parameters": {
+      "type": "object",
+      "additionalProperties": { "$ref": "#/definitions/parameter" },
+      "description": "Design parameters / generics"
+    },
+
+    "clock_reset": {
+      "type": "object",
+      "required": ["clock", "reset"],
+      "properties": {
+        "clock":        { "type": "string" },
+        "reset":        { "type": "string" },
+        "reset_active": { "type": "integer", "enum": [0, 1], "default": 0 },
+        "clock_freq":   { "type": "integer", "description": "Clock frequency in Hz" }
+      }
+    },
+
+    "clock_domains": {
+      "type": "array",
+      "items": { "$ref": "#/definitions/clock_domain" },
+      "description": "Multi-clock domain definitions"
+    },
+
+    "reset_domains": {
+      "type": "array",
+      "items": { "$ref": "#/definitions/reset_domain" },
+      "description": "Multi-reset domain definitions"
+    },
+
+    "interfaces": {
+      "type": "array",
+      "items": { "$ref": "#/definitions/interface" },
+      "minItems": 1
+    },
+
+    "registers": {
+      "type": "array",
+      "items": { "$ref": "#/definitions/register" }
+    },
+
+    "interrupts": {
+      "type": "array",
+      "items": { "$ref": "#/definitions/interrupt" }
+    },
+
+    "memory_maps": {
+      "type": "array",
+      "items": { "$ref": "#/definitions/memory_map" }
+    },
+
+    "coverage": { "$ref": "#/definitions/coverage" },
+
+    "assertions": {
+      "type": "array",
+      "items": { "$ref": "#/definitions/assertion" }
+    },
+
+    "validation_rules": {
+      "type": "object",
+      "properties": {
+        "min_registers":     { "type": "boolean", "default": false },
+        "require_reset":     { "type": "boolean", "default": true },
+        "require_interrupt": { "type": "boolean", "default": false },
+        "address_alignment": { "type": "integer", "default": 1, "description": "Required address alignment in bytes" },
+        "no_reserved_holes": { "type": "boolean", "default": false, "description": "No gaps in register address map" }
+      }
+    }
+  }
+}

configs/uart16550-1.5.core

@@ -0,0 +1,190 @@
+# UART 16550 v1.5 Core Description
+# FuseSoC-compatible .core format
+# Ref: https://github.com/fusesoc/fusesoc
+
+name: uart16550
+version: "1.5"
+description: Universal Asynchronous Receiver-Transmitter (UART) 16550-compatible core
+author: DV Automation Team
+
+parameters:
+  clk_freq:
+    datatype: int
+    default: 50000000
+    description: System clock frequency in Hz
+  baud_rate:
+    datatype: int
+    default: 115200
+    description: Target baud rate
+  data_bits:
+    datatype: int
+    default: 8
+    paramtype: vlogparam
+  fifo_depth:
+    datatype: int
+    default: 16
+    description: Depth of TX/RX FIFOs
+
+interfaces:
+  - name: bus
+    type: wb
+    description: Wishbone bus interface
+    signals:
+      - {name: clk, direction: input, width: 1}
+      - {name: rstn, direction: input, width: 1}
+      - {name: addr, direction: input, width: 3}
+      - {name: we, direction: input, width: 1}
+      - {name: cs, direction: input, width: 1}
+      - {name: data_in, direction: input, width: 8}
+      - {name: data_out, direction: output, width: 8}
+      - {name: irq, direction: output, width: 1}
+  - name: serial
+    type: uart
+    description: Serial interface
+    signals:
+      - {name: srx, direction: input, width: 1}
+      - {name: stx, direction: output, width: 1}
+  - name: modem
+    type: modem
+    description: Modem control interface
+    signals:
+      - {name: cts_n, direction: input, width: 1}
+      - {name: rts_n, direction: output, width: 1}
+      - {name: dsr_n, direction: input, width: 1}
+      - {name: dtr_n, direction: output, width: 1}
+      - {name: ri_n, direction: input, width: 1}
+      - {name: dcd_n, direction: input, width: 1}
+
+clock_reset:
+  clock: clk
+  reset: rstn
+  reset_active: 0
+
+registers:
+  - name: RBR
+    description: Receiver Buffer Register (read-only, DLAB=0)
+    address: '0x00'
+    access: ro
+    fields:
+      - {name: rbr_data, bits: '7:0', description: Received data}
+  - name: THR
+    description: Transmitter Holding Register (write-only, DLAB=0)
+    address: '0x00'
+    access: wo
+    fields:
+      - {name: thr_data, bits: '7:0', description: Data to transmit}
+  - name: IER
+    description: Interrupt Enable Register
+    address: '0x01'
+    access: rw
+    fields:
+      - {name: erbfi, bits: '0', description: Enable RX Data Available Interrupt}
+      - {name: etbei, bits: '1', description: Enable TX Holding Register Empty Interrupt}
+      - {name: elsi, bits: '2', description: Enable RX Line Status Interrupt}
+      - {name: edssi, bits: '3', description: Enable Modem Status Interrupt}
+  - name: IIR
+    description: Interrupt Identification Register (read-only)
+    address: '0x02'
+    access: ro
+    fields:
+      - {name: int_id, bits: '3:0', description: Interrupt identification}
+      - {name: fifos_en, bits: '7:6', description: FIFO enable status}
+  - name: FCR
+    description: FIFO Control Register (write-only)
+    address: '0x02'
+    access: wo
+    fields:
+      - {name: fifo_en, bits: '0', description: Enable FIFOs}
+      - {name: rclr, bits: '1', description: Clear RX FIFO}
+      - {name: tclr, bits: '2', description: Clear TX FIFO}
+      - {name: dma_mode, bits: '3', description: DMA mode select}
+      - {name: rx_trigger, bits: '7:6', description: RX FIFO trigger level}
+  - name: LCR
+    description: Line Control Register
+    address: '0x03'
+    access: rw
+    fields:
+      - {name: wls, bits: '1:0', description: Word length select}
+      - {name: stb, bits: '2', description: Stop bits}
+      - {name: pen, bits: '3', description: Parity enable}
+      - {name: eps, bits: '4', description: Even parity select}
+      - {name: sp, bits: '5', description: Stick parity}
+      - {name: bc, bits: '6', description: Break control}
+      - {name: dlab, bits: '7', description: Divisor latch access bit}
+  - name: MCR
+    description: Modem Control Register
+    address: '0x04'
+    access: rw
+    fields:
+      - {name: dtr, bits: '0', description: Data Terminal Ready}
+      - {name: rts, bits: '1', description: Request To Send}
+      - {name: out1, bits: '2', description: Output 1}
+      - {name: out2, bits: '3', description: Output 2}
+      - {name: loop, bits: '4', description: Loopback mode}
+  - name: LSR
+    description: Line Status Register (read-only)
+    address: '0x05'
+    access: ro
+    fields:
+      - {name: dr, bits: '0', description: Data Ready}
+      - {name: oe, bits: '1', description: Overrun Error}
+      - {name: pe, bits: '2', description: Parity Error}
+      - {name: fe, bits: '3', description: Framing Error}
+      - {name: bi, bits: '4', description: Break Interrupt}
+      - {name: thre, bits: '5', description: TX Holding Register Empty}
+      - {name: temt, bits: '6', description: TX Empty}
+      - {name: err, bits: '7', description: Error in RX FIFO}
+  - name: MSR
+    description: Modem Status Register (read-only)
+    address: '0x06'
+    access: ro
+    fields:
+      - {name: dcts, bits: '0', description: Delta Clear To Send}
+      - {name: ddsr, bits: '1', description: Delta Data Set Ready}
+      - {name: teri, bits: '2', description: Trailing Edge RI}
+      - {name: ddcd, bits: '3', description: Delta Data Carrier Detect}
+      - {name: cts, bits: '4', description: Clear To Send}
+      - {name: dsr, bits: '5', description: Data Set Ready}
+      - {name: ri, bits: '6', description: Ring Indicator}
+      - {name: dcd, bits: '7', description: Data Carrier Detect}
+  - name: SCR
+    description: Scratch Register
+    address: '0x07'
+    access: rw
+    fields:
+      - {name: scratch, bits: '7:0', description: Scratch value}
+  - name: DLL
+    description: Divisor Latch LSB (DLAB=1)
+    address: '0x00'
+    access: rw
+    fields:
+      - {name: dll, bits: '7:0', description: Divisor latch low byte}
+  - name: DLH
+    description: Divisor Latch MSB (DLAB=1)
+    address: '0x01'
+    access: rw
+    fields:
+      - {name: dlh, bits: '7:0', description: Divisor latch high byte}
+
+filesets:
+  - name: rtl
+    files:
+      - uart16550.v
+      - uart_baud.v
+      - uart_fifo.v
+    file_type: verilogSource
+
+targets:
+  default:
+    filesets: [rtl]
+    parameters:
+      - clk_freq
+      - baud_rate
+  sim:
+    filesets: [rtl]
+    parameters:
+      - clk_freq
+      - baud_rate
+    tools:
+      - verilator
+      - iverilog

configs/uart_demo.yaml

@@ -0,0 +1,31 @@
+design_name: uart
+clock_reset:
+  clock: clk
+  reset: rst_n
+  reset_active: 0
+
+interfaces:
+  - name: uart_if
+    signals:
+      - name: tx
+        direction: output
+      - name: rx
+        direction: input
+      - name: baud_tick
+        direction: input
+
+registers:
+  - name: ctrl
+    address: '0x00'
+    fields:
+      - name: enable
+        bits: '0'
+      - name: baud_div
+        bits: '7:2'
+  - name: status
+    address: '0x04'
+    fields:
+      - name: tx_full
+        bits: '0'
+      - name: rx_empty
+        bits: '1'

docker-compose.yml

@@ -0,0 +1,23 @@
+services:
+  app:
+    build:
+      context: .
+      dockerfile: Dockerfile
+    container_name: uvmgen
+    ports:
+      - "8000:8000"
+    environment:
+      - PYTHONUNBUFFERED=1
+      - LOG_LEVEL=info
+    volumes:
+      - uvmgen_data:/var/data
+    healthcheck:
+      test: ["CMD", "python", "-c", "import urllib.request; print(urllib.request.urlopen('http://localhost:8000/api/health').read().decode())"]
+      interval: 30s
+      timeout: 5s
+      retries: 3
+      start_period: 15s
+    restart: unless-stopped
+
+volumes:
+  uvmgen_data:

frontend/package.json

@@ -0,0 +1,38 @@
+{
+  "name": "uvm-tb-generator-ui",
+  "version": "0.3.0",
+  "private": true,
+  "description": "Semiconductor Verification Pipeline — Frontend",
+  "dependencies": {
+    "js-yaml": "^4.1.0",
+    "lucide-react": "^0.468.0",
+    "react": "^18.3.1",
+    "react-dom": "^18.3.1",
+    "react-scripts": "^5.0.1",
+    "react-syntax-highlighter": "^15.6.1"
+  },
+  "devDependencies": {
+    "autoprefixer": "^10.4.20",
+    "postcss": "^8.4.49",
+    "tailwindcss": "^3.4.17"
+  },
+  "scripts": {
+    "start": "react-scripts start",
+    "build": "react-scripts build",
+    "test": "react-scripts test",
+    "eject": "react-scripts eject"
+  },
+  "browserslist": {
+    "production": [
+      ">0.2%",
+      "not dead",
+      "not op_mini all"
+    ],
+    "development": [
+      "last 1 chrome version",
+      "last 1 firefox version",
+      "last 1 safari version"
+    ]
+  },
+  "proxy": false
+}

frontend/postcss.config.js

@@ -0,0 +1,6 @@
+module.exports = {
+  plugins: {
+    tailwindcss: {},
+    autoprefixer: {},
+  },
+};

frontend/public/index.html

@@ -0,0 +1,14 @@
+<!DOCTYPE html>
+<html lang="en">
+  <head>
+    <meta charset="utf-8" />
+    <meta name="viewport" content="width=device-width, initial-scale=1" />
+    <meta name="theme-color" content="#0f172a" />
+    <meta name="description" content="Semiconductor Verification Pipeline — UVM Testbench Generator" />
+    <title>Verification Pipeline · UVM Generator</title>
+  </head>
+  <body class="bg-slate-50 text-slate-900 antialiased">
+    <noscript>You need to enable JavaScript to run this app.</noscript>
+    <div id="root"></div>
+  </body>
+</html>

frontend/src/App.js

@@ -0,0 +1,49 @@
+import React, { useState, useCallback } from "react";
+import Header from "./components/Header";
+import Footer from "./components/Footer";
+import YAMLForm from "./components/YAMLForm";
+import PreviewPanel from "./components/PreviewPanel";
+import PipelineRunner from "./components/PipelineRunner";
+import ErrorBoundary from "./components/ErrorBoundary";
+
+export default function App() {
+  const [spec, setSpec] = useState(null);
+
+  const handleSpecChange = useCallback((parsed) => {
+    setSpec(parsed);
+  }, []);
+
+  return (
+    <div className="min-h-screen flex flex-col bg-slate-50">
+      <Header />
+
+      <main className="flex-1 max-w-7xl mx-auto w-full px-4 sm:px-6 lg:px-8 py-6 space-y-6">
+        {/* Intro */}
+        <div className="bg-gradient-to-r from-brand-600 to-brand-800 rounded-xl px-6 py-5 text-white">
+          <h2 className="text-lg font-bold">UVM Testbench Generator</h2>
+          <p className="text-sm text-brand-100 mt-1 max-w-2xl">
+            Upload or paste a FuseSoC-style YAML / .core specification, edit signals and registers
+            directly, then run the pipeline to generate a complete UVM testbench.
+          </p>
+        </div>
+
+        {/* Form + Preview side by side */}
+        <div className="grid grid-cols-1 xl:grid-cols-2 gap-6">
+          <ErrorBoundary>
+            <YAMLForm onSpecChange={handleSpecChange} />
+          </ErrorBoundary>
+          <ErrorBoundary>
+            <PreviewPanel spec={spec} />
+          </ErrorBoundary>
+        </div>
+
+        {/* Pipeline runner */}
+        <ErrorBoundary>
+          <PipelineRunner spec={spec} />
+        </ErrorBoundary>
+      </main>
+
+      <Footer />
+    </div>
+  );
+}

frontend/src/components/ErrorBoundary.js

@@ -0,0 +1,87 @@
+import React from "react";
+
+const ERROR_STYLES = {
+  container: {
+    minHeight: "200px",
+    display: "flex",
+    alignItems: "center",
+    justifyContent: "center",
+  },
+  card: {
+    maxWidth: "480px",
+    padding: "24px",
+    background: "#fff",
+    borderRadius: "12px",
+    border: "1px solid #fecaca",
+    boxShadow: "0 4px 6px -1px rgba(0,0,0,0.1)",
+    textAlign: "center",
+  },
+  title: {
+    fontSize: "16px",
+    fontWeight: 600,
+    color: "#991b1b",
+    marginBottom: "8px",
+  },
+  message: {
+    fontSize: "13px",
+    color: "#7f1d1d",
+    marginBottom: "16px",
+    lineHeight: 1.5,
+  },
+  button: {
+    padding: "8px 20px",
+    fontSize: "13px",
+    fontWeight: 500,
+    background: "#dc2626",
+    color: "#fff",
+    border: "none",
+    borderRadius: "8px",
+    cursor: "pointer",
+  },
+};
+
+export default class ErrorBoundary extends React.Component {
+  constructor(props) {
+    super(props);
+    this.state = { hasError: false, error: null };
+  }
+
+  static getDerivedStateFromError(error) {
+    return { hasError: true, error };
+  }
+
+  componentDidCatch(error, errorInfo) {
+    console.error("[ErrorBoundary]", error, errorInfo);
+    if (this.props.onError) {
+      this.props.onError(error, errorInfo);
+    }
+  }
+
+  handleReset = () => {
+    this.setState({ hasError: false, error: null });
+  };
+
+  render() {
+    if (this.state.hasError) {
+      if (this.props.fallback) {
+        return this.props.fallback;
+      }
+      return (
+        <div style={ERROR_STYLES.container}>
+          <div style={ERROR_STYLES.card}>
+            <div style={ERROR_STYLES.title}>Something went wrong</div>
+            <div style={ERROR_STYLES.message}>
+              {this.state.error?.message || "An unexpected error occurred."}
+              <br />
+              Try refreshing the page or resetting the component.
+            </div>
+            <button style={ERROR_STYLES.button} onClick={this.handleReset}>
+              Reset
+            </button>
+          </div>
+        </div>
+      );
+    }
+    return this.props.children;
+  }
+}

frontend/src/components/Footer.js

@@ -0,0 +1,25 @@
+import React from "react";
+import { Cpu } from "lucide-react";
+
+export default function Footer() {
+  return (
+    <footer className="bg-white border-t border-slate-200 mt-12">
+      <div className="max-w-7xl mx-auto px-4 sm:px-6 lg:px-8 py-6">
+        <div className="flex flex-col sm:flex-row items-center justify-between gap-3">
+          <div className="flex items-center gap-2 text-sm text-slate-500">
+            <Cpu size={16} className="text-brand-500" />
+            <span>
+              Semiconductor Verification Pipeline &mdash; Developed by{" "}
+              <span className="font-semibold text-slate-700">Sai Kumar Taraka</span>
+            </span>
+          </div>
+          <div className="flex items-center gap-4 text-xs text-slate-400">
+            <span>UVM TB Generator v0.3.0</span>
+            <span className="hidden sm:inline">&middot;</span>
+            <span className="hidden sm:inline">MIT License</span>
+          </div>
+        </div>
+      </div>
+    </footer>
+  );
+}

frontend/src/components/Header.js

@@ -0,0 +1,40 @@
+import React from "react";
+import { Cpu, GitBranch } from "lucide-react";
+
+export default function Header() {
+  return (
+    <header className="bg-white border-b border-slate-200 sticky top-0 z-40">
+      <div className="max-w-7xl mx-auto px-4 sm:px-6 lg:px-8">
+        <div className="flex items-center justify-between h-16">
+          <div className="flex items-center gap-3">
+            <div className="w-9 h-9 rounded-lg bg-brand-600 flex items-center justify-center">
+              <Cpu size={20} className="text-white" />
+            </div>
+            <div>
+              <h1 className="text-base font-bold text-slate-900 leading-tight">
+                Verification Pipeline
+              </h1>
+              <p className="text-[11px] text-slate-500 leading-tight">
+                UVM Testbench Generator
+              </p>
+            </div>
+          </div>
+
+          <div className="flex items-center gap-4">
+            <a
+              href="#"
+              className="hidden sm:inline-flex items-center gap-1.5 text-xs text-slate-500 hover:text-slate-700 transition-colors"
+            >
+              <GitBranch size={14} />
+              v0.3.0
+            </a>
+            <span className="hidden sm:inline-flex items-center gap-1.5 text-xs text-slate-400">
+              <span className="w-2 h-2 rounded-full bg-emerald-400" />
+              API Ready
+            </span>
+          </div>
+        </div>
+      </div>
+    </header>
+  );
+}

frontend/src/components/PipelineRunner.js

@@ -0,0 +1,461 @@
+import React, { useRef, useEffect, useState } from "react";
+import {
+  Play,
+  Square,
+  FileText,
+  Download,
+  Terminal,
+  CheckCircle2,
+  XCircle,
+  Loader2,
+  AlertTriangle,
+  Info,
+  BarChart3,
+  GitBranch,
+  RefreshCw,
+  Target,
+  TrendingUp,
+} from "lucide-react";
+import usePipeline from "../hooks/usePipeline";
+import { toYAML } from "../utils/yamlUtils";
+
+const LOG_ICONS = {
+  info: Info,
+  success: CheckCircle2,
+  error: XCircle,
+  warn: AlertTriangle,
+};
+
+const LOG_COLORS = {
+  info: "text-slate-600",
+  success: "text-emerald-600",
+  error: "text-red-600",
+  warn: "text-amber-600",
+};
+
+function LogEntry({ entry }) {
+  const Icon = LOG_ICONS[entry.level] || Info;
+  return (
+    <div className={`flex items-start gap-2 ${LOG_COLORS[entry.level] || "text-slate-600"}`}>
+      <Icon size={14} className="shrink-0 mt-0.5" />
+      <span className="flex-1">{entry.message}</span>
+      <span className="text-[10px] text-slate-400 font-mono shrink-0">{entry.timestamp}</span>
+    </div>
+  );
+}
+
+function CoverageBar({ pct }) {
+  const color =
+    pct >= 90 ? "bg-emerald-500" : pct >= 70 ? "bg-amber-500" : "bg-red-500";
+  return (
+    <div className="flex items-center gap-2">
+      <div className="flex-1 h-2 bg-slate-100 rounded-full overflow-hidden">
+        <div
+          className={`h-full rounded-full transition-all duration-500 ${color}`}
+          style={{ width: `${Math.min(pct, 100)}%` }}
+        />
+      </div>
+      <span className="text-xs font-mono text-slate-600 w-10 text-right">{pct.toFixed(0)}%</span>
+    </div>
+  );
+}
+
+function CoverageTrendChart({ trend }) {
+  if (!trend || trend.length < 2) return null;
+  const max = Math.max(...trend.map((t) => t.coverage));
+  const min = Math.min(...trend.map((t) => t.coverage));
+  const range = max - min || 1;
+
+  return (
+    <div className="rounded-lg border border-slate-200 bg-white p-4">
+      <div className="flex items-center gap-2 mb-3">
+        <TrendingUp size={16} className="text-brand-600" />
+        <span className="text-sm font-semibold text-slate-800">Coverage Trend</span>
+        {trend.length >= 2 && (
+          <span className="text-xs text-slate-400 ml-auto">
+            Delta: {(trend[trend.length-1].coverage - trend[0].coverage) > 0 ? '+' : ''}
+            {(trend[trend.length-1].coverage - trend[0].coverage).toFixed(1)}%
+          </span>
+        )}
+      </div>
+      <div className="flex items-end gap-1 h-28">
+        {trend.map((t, i) => {
+          const h = ((t.coverage - min) / range) * 100;
+          const color =
+            t.coverage >= 90 ? "bg-emerald-400" :
+            t.coverage >= 70 ? "bg-amber-400" : "bg-red-400";
+          const prevCov = i > 0 ? trend[i-1].coverage : t.coverage;
+          const gain = t.coverage - prevCov;
+          return (
+            <div key={i} className="flex-1 flex flex-col items-center gap-1">
+              <span className="text-[10px] font-mono text-slate-500">{t.coverage.toFixed(0)}%</span>
+              <div className="flex flex-col items-center w-full">
+                {i > 0 && gain !== 0 && (
+                  <span className={`text-[8px] ${gain > 0 ? 'text-emerald-500' : 'text-red-400'}`}>
+                    {gain > 0 ? '+' : ''}{gain.toFixed(1)}%
+                  </span>
+                )}
+                <div
+                  className={`w-full rounded-t transition-all duration-500 ${color}`}
+                  style={{ height: `${Math.max(h, 5)}%`, minHeight: '8px' }}
+                  title={`${t.version}: ${t.coverage.toFixed(1)}%`}
+                />
+              </div>
+              <span className="text-[9px] text-slate-400">{t.version}</span>
+            </div>
+          );
+        })}
+      </div>
+    </div>
+  );
+}
+
+function SeedCoverageSummary({ seeds }) {
+  if (!seeds || seeds.length === 0) return null;
+  const best = Math.max(...seeds.map(s => s.pct));
+  const worst = Math.min(...seeds.map(s => s.pct));
+  return (
+    <div className="flex items-center gap-3 text-xs text-slate-500">
+      <span className="font-medium text-slate-600">Seeds:</span>
+      {seeds.map((s, i) => {
+        const color = s.pct >= 90 ? "text-emerald-600" : s.pct >= 70 ? "text-amber-600" : "text-red-600";
+        return <span key={i} className={`font-mono ${color}`}>s{i+1}={s.pct.toFixed(0)}%</span>;
+      })}
+      <span className="text-slate-300">|</span>
+      <span className="font-mono text-slate-500">Δ{best - worst > 0 ? '+' : ''}{(best - worst).toFixed(0)}%</span>
+    </div>
+  );
+}
+
+function VersionHistory({ versions, latestGaps }) {
+  if (!versions || versions.length === 0) return null;
+  const passed = versions.filter(v => v.coverage >= 90).length;
+  const failed = versions.length - passed;
+  const bestCov = Math.max(...versions.map(v => v.coverage));
+  return (
+    <div className="rounded-lg border border-slate-200 bg-white">
+      <div className="flex items-center gap-2 px-4 py-3 border-b border-slate-100">
+        <GitBranch size={16} className="text-brand-600" />
+        <span className="text-sm font-semibold text-slate-800">Version History</span>
+        <span className="text-xs text-slate-400 ml-auto">{versions.length} versions</span>
+      </div>
+      {/* Pass/Fail summary */}
+      <div className="flex items-center gap-4 px-4 py-2 bg-slate-50 border-b border-slate-100">
+        <div className="flex items-center gap-1.5">
+          <CheckCircle2 size={14} className="text-emerald-500" />
+          <span className="text-xs font-medium text-slate-700">{passed} passed</span>
+        </div>
+        <div className="flex items-center gap-1.5">
+          <XCircle size={14} className="text-red-500" />
+          <span className="text-xs font-medium text-slate-700">{failed} failed</span>
+        </div>
+        <div className="flex items-center gap-1.5 ml-auto">
+          <span className="text-xs text-slate-400">Best:</span>
+          <span className="text-xs font-bold text-slate-700">{bestCov.toFixed(1)}%</span>
+        </div>
+      </div>
+      <div className="divide-y divide-slate-100 max-h-64 overflow-y-auto">
+        {[...versions].reverse().map((v, i) => {
+          const prev = i < versions.length - 1 ? versions[versions.length - 1 - (i + 1)] : null;
+          const delta = prev ? v.coverage - prev.coverage : null;
+          return (
+            <div key={i} className="flex items-center gap-3 px-4 py-2.5">
+              <div className={`w-8 h-8 rounded-full flex items-center justify-center ${
+                v.coverage >= 90 ? 'bg-emerald-50' : v.coverage >= 70 ? 'bg-amber-50' : 'bg-red-50'
+              }`}>
+                <span className={`text-xs font-bold ${
+                  v.coverage >= 90 ? 'text-emerald-700' : v.coverage >= 70 ? 'text-amber-700' : 'text-red-700'
+                }`}>{v.version}</span>
+              </div>
+              <div className="flex-1">
+                <div className="flex items-center gap-2">
+                  <span className="text-sm text-slate-700">{v.files} files</span>
+                  <span className="text-[11px] text-slate-300">|</span>
+                  <span className={`text-sm font-medium ${
+                    v.coverage >= 90 ? 'text-emerald-700' : 'text-slate-800'
+                  }`}>{v.coverage.toFixed(1)}%</span>
+                  {delta !== null && (
+                    <span className={`text-[11px] font-mono ${
+                      delta > 0 ? 'text-emerald-500' : delta < 0 ? 'text-red-400' : 'text-slate-400'
+                    }`}>
+                      {delta > 0 ? '+' : ''}{delta.toFixed(1)}%
+                    </span>
+                  )}
+                </div>
+                <CoverageBar pct={v.coverage} />
+              </div>
+            </div>
+          );
+        })}
+      </div>
+    </div>
+  );
+}
+
+function CoverageGapsList({ gaps }) {
+  if (!gaps || gaps.length === 0) return null;
+  return (
+    <div className="rounded-lg border border-amber-200 bg-amber-50">
+      <div className="flex items-center gap-2 px-4 py-3 border-b border-amber-100">
+        <Target size={16} className="text-amber-600" />
+        <span className="text-sm font-semibold text-amber-800">Coverage Gaps</span>
+        <span className="text-xs text-amber-600 ml-auto">{gaps.length} uncovered</span>
+      </div>
+      <div className="p-3 space-y-1 max-h-32 overflow-y-auto">
+        {gaps.map((g, i) => (
+          <div key={i} className="flex items-center gap-2 text-xs text-amber-700 font-mono">
+            <span className="w-2 h-2 rounded-full bg-amber-400 shrink-0" />
+            {g.bin}
+          </div>
+        ))}
+      </div>
+    </div>
+  );
+}
+
+export default function PipelineRunner({ spec }) {
+  const {
+    running,
+    autoTraining,
+    logs,
+    artifacts,
+    error,
+    versions,
+    coverageTrend,
+    coverageGaps,
+    seedResults,
+    autoTrainMax,
+    runPipeline,
+    runAutoTrain,
+  } = usePipeline();
+  const logEndRef = useRef(null);
+  const [maxIter, setMaxIter] = useState(5);
+
+  useEffect(() => {
+    logEndRef.current?.scrollIntoView({ behavior: "smooth" });
+  }, [logs]);
+
+  const handleRun = () => {
+    if (!spec) return;
+    const yamlText = toYAML(spec);
+    runPipeline(yamlText);
+  };
+
+  const handleAutoTrain = () => {
+    if (!spec) return;
+    const yamlText = toYAML(spec);
+    runAutoTrain(yamlText, maxIter);
+  };
+
+  const handleDownload = (file) => {
+    const blob = new Blob([file.content || ""], { type: "text/plain" });
+    const url = URL.createObjectURL(blob);
+    const a = document.createElement("a");
+    a.href = url;
+    a.download = file.name;
+    document.body.appendChild(a);
+    a.click();
+    document.body.removeChild(a);
+    URL.revokeObjectURL(url);
+  };
+
+  const handleDownloadAll = () => {
+    artifacts.forEach((file) => handleDownload(file));
+  };
+
+  const canRun = spec && Object.keys(spec).length > 0 && !running;
+
+  return (
+    <div className="card">
+      <div className="card-header">
+        <Terminal size={18} className="text-brand-600" />
+        <h2>Pipeline Runner</h2>
+        {autoTraining && (
+          <span className="badge badge-warning text-xs ml-2">
+            <RefreshCw size={12} className="animate-spin inline mr-1" />
+            Auto-Training
+          </span>
+        )}
+        {versions.length > 0 && !running && (
+          <span className="badge badge-success text-xs ml-2">v{versions.length}</span>
+        )}
+
+        <div className="ml-auto flex items-center gap-3">
+          {spec && (
+            <span className="text-xs text-slate-400">
+              Spec: <span className="font-mono text-slate-600">{spec.design_name || "unnamed"}</span>
+            </span>
+          )}
+          <div className="flex items-center gap-2">
+            <label className="text-[11px] text-slate-400">Iterations</label>
+            <input
+              type="number"
+              min={1}
+              max={20}
+              value={maxIter}
+              onChange={(e) => setMaxIter(Math.max(1, Math.min(20, parseInt(e.target.value) || 5)))}
+              className="w-14 px-2 py-1 text-xs border border-slate-200 rounded-md text-center"
+              disabled={running}
+            />
+          </div>
+          <button
+            className="btn-primary text-xs"
+            onClick={handleRun}
+            disabled={!canRun}
+            title="Single pass generation"
+          >
+            {running && !autoTraining ? (
+              <>
+                <Loader2 size={14} className="animate-spin" />
+                Running...
+              </>
+            ) : (
+              <>
+                <Play size={14} />
+                Run
+              </>
+            )}
+          </button>
+          <button
+            className={running ? "btn-secondary text-xs opacity-50" : "btn-primary text-xs bg-amber-600 hover:bg-amber-700"}
+            onClick={handleAutoTrain}
+            disabled={!canRun}
+            title={`Coverage-driven auto-training (${maxIter} iterations max)`}
+          >
+            {running && autoTraining ? (
+              <>
+                <Loader2 size={14} className="animate-spin" />
+                Training...
+              </>
+            ) : (
+              <>
+                <RefreshCw size={14} />
+                Auto-Train
+              </>
+            )}
+          </button>
+        </div>
+      </div>
+
+      <div className="card-body space-y-4">
+        {/* Logs */}
+        <div className="rounded-lg bg-slate-900 border border-slate-700">
+          <div className="flex items-center justify-between px-4 py-2 border-b border-slate-700">
+            <span className="text-[11px] font-medium text-slate-400 uppercase tracking-wider">
+              Pipeline Logs
+            </span>
+            <span className="text-[11px] text-slate-500">{logs.length} entries</span>
+          </div>
+          <div className="p-4 space-y-1 max-h-48 overflow-y-auto" style={{ minHeight: "80px" }}>
+            {logs.length === 0 && (
+              <p className="text-xs text-slate-500 italic">Click "Run" or "Auto-Train" to start</p>
+            )}
+            {logs.map((entry, i) => (
+              <LogEntry key={i} entry={entry} />
+            ))}
+            <div ref={logEndRef} />
+          </div>
+        </div>
+
+        {/* Error */}
+        {error && (
+          <div className="rounded-lg bg-red-50 border border-red-200 px-4 py-3">
+            <div className="flex items-center gap-2 text-sm text-red-700">
+              <XCircle size={16} />
+              {error}
+            </div>
+          </div>
+        )}
+
+        {/* Coverage Trend */}
+        {coverageTrend && coverageTrend.length > 1 && <CoverageTrendChart trend={coverageTrend} />}
+
+        {/* Seed Coverage Summary */}
+        {seedResults && seedResults.length > 0 && (
+          <SeedCoverageSummary seeds={seedResults} />
+        )}
+
+        {/* Coverage Gaps */}
+        <CoverageGapsList gaps={coverageGaps} />
+
+        {/* Version History + Artifacts side by side */}
+        {versions.length > 0 && (
+          <div className="grid grid-cols-1 lg:grid-cols-3 gap-4">
+            {/* Version History */}
+            <div className="lg:col-span-1">
+              <VersionHistory versions={versions} latestGaps={coverageGaps} />
+            </div>
+
+            {/* Artifacts */}
+            <div className="lg:col-span-2">
+              <div className="rounded-lg border border-slate-200 bg-white">
+                <div className="flex items-center justify-between px-4 py-3 border-b border-slate-100">
+                  <div className="flex items-center gap-2">
+                    <FileText size={16} className="text-brand-600" />
+                    <h3 className="text-sm font-semibold text-slate-800">Generated Artifacts</h3>
+                  </div>
+                  <div className="flex items-center gap-2">
+                    <span className="text-xs text-slate-400">{artifacts.length} files</span>
+                    <button className="btn-secondary text-xs" onClick={handleDownloadAll}>
+                      <Download size={14} />
+                      Download All
+                    </button>
+                  </div>
+                </div>
+                <div className="divide-y divide-slate-100 max-h-80 overflow-y-auto">
+                  {artifacts.map((file, i) => (
+                    <div
+                      key={i}
+                      className="flex items-center gap-3 px-4 py-2.5 hover:bg-slate-50 cursor-pointer transition-colors"
+                      onClick={() => handleDownload(file)}
+                    >
+                      <div className="w-8 h-8 rounded-md bg-brand-50 flex items-center justify-center shrink-0">
+                        <FileText size={16} className="text-brand-600" />
+                      </div>
+                      <div className="flex-1 min-w-0">
+                        <p className="text-sm font-medium text-slate-800 truncate">{file.name}</p>
+                        <p className="text-[11px] text-slate-400 truncate">{file.path}</p>
+                      </div>
+                      <div className="flex items-center gap-2 shrink-0">
+                        <span className="text-[11px] text-slate-400">{file.size}</span>
+                        <button className="p-1.5 rounded-md text-slate-400 hover:text-brand-600 hover:bg-brand-50 transition-all">
+                          <Download size={14} />
+                        </button>
+                      </div>
+                    </div>
+                  ))}
+                </div>
+              </div>
+            </div>
+          </div>
+        )}
+
+        {/* Summary footer */}
+        {versions.length > 0 && !running && (
+          <div className="flex items-center justify-between text-xs text-slate-400 border-t border-slate-100 pt-3">
+            <div className="flex items-center gap-4">
+              <span className="flex items-center gap-1">
+                <GitBranch size={12} />
+                {versions.length} versions
+              </span>
+              <span className="flex items-center gap-1">
+                <BarChart3 size={12} />
+                Best: {Math.max(...versions.map((v) => v.coverage)).toFixed(1)}%
+              </span>
+              <span className="flex items-center gap-1">
+                <FileText size={12} />
+                {artifacts.length} files
+              </span>
+            </div>
+            {coverageGaps && coverageGaps.length > 0 && (
+              <span className="text-amber-600 flex items-center gap-1">
+                <Target size={12} />
+                {coverageGaps.length} gaps remaining
+              </span>
+            )}
+          </div>
+        )}
+      </div>
+    </div>
+  );
+}

frontend/src/components/PreviewPanel.js

@@ -0,0 +1,246 @@
+import React, { useMemo } from "react";
+import { Eye, AlertCircle, CheckCircle2, Layers } from "lucide-react";
+import { toYAML, validateYAML, PROTOCOLS } from "../utils/yamlUtils";
+
+function MissingField({ label }) {
+  return (
+    <span className="inline-flex items-center gap-1 px-2 py-0.5 rounded bg-red-50 text-red-600 text-[11px] font-medium">
+      <AlertCircle size={12} />
+      missing: {label}
+    </span>
+  );
+}
+
+function ProtocolBadge({ protocol }) {
+  const colorMap = {
+    uart: "bg-sky-50 text-sky-700",
+    spi: "bg-violet-50 text-violet-700",
+    i2c: "bg-amber-50 text-amber-700",
+    axi4lite: "bg-rose-50 text-rose-700",
+    apb: "bg-teal-50 text-teal-700",
+    wishbone: "bg-indigo-50 text-indigo-700",
+  };
+  const cls = colorMap[protocol] || "bg-slate-100 text-slate-600";
+  return (
+    <span className={`inline-flex items-center rounded-full px-2 py-0.5 text-[11px] font-medium ${cls}`}>
+      {protocol.toUpperCase()}
+    </span>
+  );
+}
+
+function Section({ title, children, icon, count, error }) {
+  return (
+    <div className={`rounded-lg border ${error ? "border-red-200 bg-red-50/30" : "border-slate-200"} p-4 space-y-3`}>
+      <div className="flex items-center justify-between">
+        <div className="flex items-center gap-2 text-sm font-semibold text-slate-800">
+          {icon}
+          {title}
+          {count !== undefined && (
+            <span className="text-xs font-normal text-slate-400">({count})</span>
+          )}
+        </div>
+        {error && <MissingField label={error} />}
+      </div>
+      {children}
+    </div>
+  );
+}
+
+export default function PreviewPanel({ spec }) {
+  const errors = useMemo(() => (spec ? validateYAML(toYAML(spec)) : ["No spec loaded"]), [spec]);
+
+  if (!spec || Object.keys(spec).length === 0) {
+    return (
+      <div className="card">
+        <div className="card-header">
+          <Eye size={18} className="text-slate-400" />
+          <h2 className="text-slate-400">Preview</h2>
+        </div>
+        <div className="card-body">
+          <div className="flex flex-col items-center justify-center py-12 text-slate-400">
+            <Layers size={40} className="mb-3 opacity-40" />
+            <p className="text-sm">Load a spec to see the parsed preview</p>
+          </div>
+        </div>
+      </div>
+    );
+  }
+
+  const hasErrors = errors.length > 0;
+
+  return (
+    <div className="card">
+      <div className="card-header">
+        <Eye size={18} className="text-brand-600" />
+        <h2>Parsed Specification</h2>
+        <span className={hasErrors ? "badge-error ml-auto" : "badge-success ml-auto"}>
+          {hasErrors ? `${errors.length} issue${errors.length > 1 ? "s" : ""}` : "Valid"}
+        </span>
+      </div>
+
+      <div className="card-body space-y-4">
+        {/* Errors */}
+        {hasErrors && (
+          <div className="rounded-lg bg-red-50 border border-red-200 px-4 py-3">
+            <div className="text-xs text-red-700 space-y-0.5">
+              {errors.map((e, i) => (
+                <p key={i} className="flex items-center gap-1.5">
+                  <AlertCircle size={12} className="shrink-0" />
+                  {e}
+                </p>
+              ))}
+            </div>
+          </div>
+        )}
+
+        {/* Design metadata */}
+        <div className="grid grid-cols-2 sm:grid-cols-4 gap-3">
+          <div className="bg-slate-50 rounded-lg p-3">
+            <p className="text-[11px] text-slate-500 font-medium uppercase tracking-wider">Design</p>
+            <p className="text-sm font-semibold text-slate-900 mt-0.5">
+              {spec.design_name || <MissingField label="design_name" />}
+            </p>
+          </div>
+          <div className="bg-slate-50 rounded-lg p-3">
+            <p className="text-[11px] text-slate-500 font-medium uppercase tracking-wider">Version</p>
+            <p className="text-sm text-slate-900 mt-0.5">{spec.version || "—"}</p>
+          </div>
+          <div className="bg-slate-50 rounded-lg p-3">
+            <p className="text-[11px] text-slate-500 font-medium uppercase tracking-wider">Vendor</p>
+            <p className="text-sm text-slate-900 mt-0.5">{spec.vendor || "—"}</p>
+          </div>
+          <div className="bg-slate-50 rounded-lg p-3">
+            <p className="text-[11px] text-slate-500 font-medium uppercase tracking-wider">Protocol</p>
+            <p className="mt-0.5">
+              {spec.protocol ? (
+                <ProtocolBadge protocol={spec.protocol} />
+              ) : (
+                <span className="badge-warning">Auto</span>
+              )}
+            </p>
+          </div>
+        </div>
+
+        {/* Clock / Reset */}
+        <Section
+          title="Clock & Reset"
+          icon={<span className="w-2 h-2 rounded-full bg-amber-400" />}
+          error={!spec.clock_reset ? "clock_reset" : null}
+        >
+          <div className="grid grid-cols-3 gap-3 text-sm">
+            <div>
+              <span className="text-[11px] text-slate-500">Clock</span>
+              <p className="font-mono text-slate-900">{spec.clock_reset?.clock || "—"}</p>
+            </div>
+            <div>
+              <span className="text-[11px] text-slate-500">Reset</span>
+              <p className="font-mono text-slate-900">{spec.clock_reset?.reset || "—"}</p>
+            </div>
+            <div>
+              <span className="text-[11px] text-slate-500">Active</span>
+              <p className="font-mono text-slate-900">
+                {spec.clock_reset?.reset_active === 0 ? "Low" : spec.clock_reset?.reset_active === 1 ? "High" : "—"}
+              </p>
+            </div>
+          </div>
+        </Section>
+
+        {/* Interfaces */}
+        <Section
+          title="Interfaces"
+          icon={<span className="w-2 h-2 rounded-full bg-brand-500" />}
+          count={spec.interfaces?.length}
+          error={!spec.interfaces?.length ? "interfaces" : null}
+        >
+          {(spec.interfaces || []).map((iface, i) => (
+            <div key={i} className="border-t border-slate-100 pt-2 first:border-0 first:pt-0">
+              <div className="flex items-center gap-2 mb-1.5">
+                <span className="text-sm font-medium text-slate-800">{iface.name || `iface_${i}`}</span>
+                {iface.protocol && <ProtocolBadge protocol={iface.protocol} />}
+                <span className="text-xs text-slate-400">
+                  {Array.isArray(iface.signals) ? iface.signals.length : 0} signals
+                </span>
+              </div>
+              <div className="flex flex-wrap gap-1.5">
+                {Array.isArray(iface.signals) && iface.signals.map((sig, j) => (
+                  <span
+                    key={j}
+                    className={`inline-flex items-center gap-1 rounded-md px-2 py-0.5 text-[11px] font-mono
+                      ${sig.direction === "output"
+                        ? "bg-emerald-50 text-emerald-700"
+                        : sig.direction === "inout"
+                        ? "bg-amber-50 text-amber-700"
+                        : "bg-sky-50 text-sky-700"
+                      }`}
+                  >
+                    {sig.name}
+                    <span className="opacity-60">
+                      {(sig.width || 1) > 1 ? `[${sig.width - 1}:0]` : ""}
+                    </span>
+                    <span className="opacity-50 text-[10px]">({sig.direction[0]})</span>
+                  </span>
+                ))}
+              </div>
+            </div>
+          ))}
+        </Section>
+
+        {/* Registers */}
+        <Section
+          title="Registers"
+          icon={<span className="w-2 h-2 rounded-full bg-violet-500" />}
+          count={spec.registers?.length}
+        >
+          {(spec.registers || []).length === 0 && (
+            <p className="text-xs text-slate-400 italic">No registers defined</p>
+          )}
+          {(spec.registers || []).map((reg, i) => (
+            <div key={i} className="border-t border-slate-100 pt-2 first:border-0 first:pt-0">
+              <div className="flex items-center gap-2 mb-1">
+                <span className="text-sm font-mono font-semibold text-slate-800">{reg.name}</span>
+                <span className="text-xs font-mono text-slate-500">@{reg.address}</span>
+                <span className={`badge text-[10px] ${
+                  reg.access === "ro" ? "badge-warning" :
+                  reg.access === "wo" ? "badge-error" :
+                  "badge-info"
+                }`}>
+                  [{reg.access || "rw"}]
+                </span>
+                {reg.description && (
+                  <span className="text-xs text-slate-400 truncate max-w-[200px]">{reg.description}</span>
+                )}
+              </div>
+              {(reg.fields || []).length > 0 && (
+                <div className="ml-3 flex flex-wrap gap-1">
+                  {(reg.fields || []).map((f, j) => (
+                    <span key={j} className="inline-flex items-center gap-1 rounded bg-slate-100 px-1.5 py-0.5 text-[11px] font-mono text-slate-600">
+                      {f.name}[{f.bits}]
+                    </span>
+                  ))}
+                </div>
+              )}
+            </div>
+          ))}
+        </Section>
+
+        {/* Parameters */}
+        {spec.parameters && Object.keys(spec.parameters).length > 0 && (
+          <Section
+            title="Parameters"
+            icon={<span className="w-2 h-2 rounded-full bg-slate-400" />}
+            count={Object.keys(spec.parameters).length}
+          >
+            <div className="grid grid-cols-2 sm:grid-cols-3 gap-2">
+              {Object.entries(spec.parameters).map(([k, v]) => (
+                <div key={k} className="bg-slate-50 rounded px-2.5 py-1.5">
+                  <p className="text-[11px] font-mono text-slate-700">{k}</p>
+                  <p className="text-xs text-slate-500">{v ?? "—"}</p>
+                </div>
+              ))}
+            </div>
+          </Section>
+        )}
+      </div>
+    </div>
+  );
+}

frontend/src/components/YAMLForm.js

@@ -0,0 +1,516 @@
+import React, { useState, useRef, useCallback } from "react";
+import {
+  Upload,
+  FileCode,
+  Plus,
+  Trash2,
+  AlertCircle,
+  CheckCircle2,
+  Settings2,
+} from "lucide-react";
+import { parseYAML, validateYAML, toYAML, PROTOCOLS, DEFAULT_YAML } from "../utils/yamlUtils";
+
+export default function YAMLForm({ onSpecChange, validationErrors }) {
+  const [yamlText, setYamlText] = useState(DEFAULT_YAML);
+  const [parsed, setParsed] = useState(() => parseYAML(DEFAULT_YAML));
+  const [mode, setMode] = useState("editor"); // editor | parsed | split
+  const [activeTab, setActiveTab] = useState("spec"); // spec | signals | registers
+  const fileRef = useRef(null);
+
+  const handleChange = useCallback(
+    (text) => {
+      setYamlText(text);
+      try {
+        const obj = parseYAML(text);
+        setParsed(obj);
+        onSpecChange(obj);
+      } catch {
+        // keep previous parsed state
+      }
+    },
+    [onSpecChange]
+  );
+
+  const handleFileUpload = useCallback(
+    (e) => {
+      const file = e.target.files?.[0];
+      if (!file) return;
+      const reader = new FileReader();
+      reader.onload = (ev) => handleChange(ev.target.result);
+      reader.readAsText(file);
+    },
+    [handleChange]
+  );
+
+  const handlePasteExample = useCallback(() => {
+    handleChange(DEFAULT_YAML);
+  }, [handleChange]);
+
+  const errors = validateYAML(yamlText);
+
+  // ── Signal / Register editors ────────────────────────────────────
+
+  const updateInterface = (idx, field, value) => {
+    const ifaces = [...(parsed.interfaces || [])];
+    ifaces[idx] = { ...ifaces[idx], [field]: value };
+    const updated = { ...parsed, interfaces: ifaces };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const addSignal = (ifaceIdx) => {
+    const ifaces = [...(parsed.interfaces || [])];
+    const existing = Array.isArray(ifaces[ifaceIdx]?.signals) ? ifaces[ifaceIdx].signals : [];
+    const signals = [...existing, { name: "", direction: "input", width: 1 }];
+    ifaces[ifaceIdx] = { ...ifaces[ifaceIdx], signals };
+    const updated = { ...parsed, interfaces: ifaces };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const updateSignal = (ifaceIdx, sigIdx, field, value) => {
+    const ifaces = [...(parsed.interfaces || [])];
+    const existing = Array.isArray(ifaces[ifaceIdx]?.signals) ? ifaces[ifaceIdx].signals : [];
+    const signals = [...existing];
+    signals[sigIdx] = { ...signals[sigIdx], [field]: value };
+    ifaces[ifaceIdx] = { ...ifaces[ifaceIdx], signals };
+    const updated = { ...parsed, interfaces: ifaces };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const removeSignal = (ifaceIdx, sigIdx) => {
+    const ifaces = [...(parsed.interfaces || [])];
+    const sigs = Array.isArray(ifaces[ifaceIdx].signals) ? ifaces[ifaceIdx].signals : [];
+    ifaces[ifaceIdx] = {
+      ...ifaces[ifaceIdx],
+      signals: sigs.filter((_, i) => i !== sigIdx),
+    };
+    const updated = { ...parsed, interfaces: ifaces };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const addRegister = () => {
+    const regs = [...(parsed.registers || []), { name: "", address: "0x00", access: "rw", fields: [] }];
+    const updated = { ...parsed, registers: regs };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const updateRegister = (idx, field, value) => {
+    const regs = [...(parsed.registers || [])];
+    regs[idx] = { ...regs[idx], [field]: value };
+    const updated = { ...parsed, registers: regs };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const removeRegister = (idx) => {
+    const updated = { ...parsed, registers: parsed.registers.filter((_, i) => i !== idx) };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const addField = (regIdx) => {
+    const regs = [...(parsed.registers || [])];
+    const fields = [...(regs[regIdx]?.fields || []), { name: "", bits: "0", description: "" }];
+    regs[regIdx] = { ...regs[regIdx], fields };
+    const updated = { ...parsed, registers: regs };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const updateField = (regIdx, fldIdx, field, value) => {
+    const regs = [...(parsed.registers || [])];
+    const fields = [...(regs[regIdx]?.fields || [])];
+    fields[fldIdx] = { ...fields[fldIdx], [field]: value };
+    regs[regIdx] = { ...regs[regIdx], fields };
+    const updated = { ...parsed, registers: regs };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  const removeField = (regIdx, fldIdx) => {
+    const regs = [...(parsed.registers || [])];
+    regs[regIdx] = {
+      ...regs[regIdx],
+      fields: regs[regIdx].fields.filter((_, i) => i !== fldIdx),
+    };
+    const updated = { ...parsed, registers: regs };
+    setParsed(updated);
+    handleChange(toYAML(updated));
+  };
+
+  return (
+    <div className="card">
+      <div className="card-header">
+        <FileCode size={18} className="text-brand-600" />
+        <h2>Design Specification</h2>
+      </div>
+
+      <div className="card-body space-y-4">
+        {/* Toolbar */}
+        <div className="flex flex-wrap items-center gap-2">
+          <button className="btn-secondary text-xs" onClick={() => fileRef.current?.click()}>
+            <Upload size={14} /> Upload .core / .yaml
+          </button>
+          <input
+            ref={fileRef}
+            type="file"
+            accept=".yaml,.yml,.core,.json"
+            className="hidden"
+            onChange={handleFileUpload}
+          />
+          <button className="btn-secondary text-xs" onClick={handlePasteExample}>
+            Load Example
+          </button>
+          <div className="ml-auto flex items-center gap-1 bg-slate-100 rounded-lg p-0.5">
+            {["spec", "signals", "registers"].map((t) => (
+              <button
+                key={t}
+                onClick={() => setActiveTab(t)}
+                className={`px-3 py-1.5 text-xs font-medium rounded-md transition-colors ${
+                  activeTab === t
+                    ? "bg-white text-slate-900 shadow-sm"
+                    : "text-slate-500 hover:text-slate-700"
+                }`}
+              >
+                {t === "spec" ? "Spec" : t === "signals" ? "Signals" : "Registers"}
+              </button>
+            ))}
+          </div>
+        </div>
+
+        {/* Validation status */}
+        {errors.length > 0 && (
+          <div className="rounded-lg bg-red-50 border border-red-200 px-4 py-3">
+            <div className="flex items-start gap-2">
+              <AlertCircle size={16} className="text-red-500 mt-0.5 shrink-0" />
+              <div className="text-xs text-red-700 space-y-0.5">
+                {errors.map((e, i) => (
+                  <p key={i}>{e}</p>
+                ))}
+              </div>
+            </div>
+          </div>
+        )}
+        {errors.length === 0 && yamlText.trim() && (
+          <div className="flex items-center gap-2 text-xs text-emerald-600">
+            <CheckCircle2 size={14} />
+            YAML syntax valid
+          </div>
+        )}
+
+        {/* ── Spec tab ─────────────────────────────────── */}
+        {activeTab === "spec" && (
+          <div className="space-y-3">
+            <div className="grid grid-cols-1 sm:grid-cols-3 gap-3">
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Design Name</label>
+                <input
+                  className="input-field text-sm"
+                  value={parsed.design_name || ""}
+                  onChange={(e) => {
+                    const updated = { ...parsed, design_name: e.target.value };
+                    setParsed(updated);
+                    handleChange(toYAML(updated));
+                  }}
+                  placeholder="uart16550"
+                />
+              </div>
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Version</label>
+                <input
+                  className="input-field text-sm"
+                  value={parsed.version || ""}
+                  onChange={(e) => {
+                    const updated = { ...parsed, version: e.target.value };
+                    setParsed(updated);
+                    handleChange(toYAML(updated));
+                  }}
+                  placeholder="1.5"
+                />
+              </div>
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Vendor</label>
+                <input
+                  className="input-field text-sm"
+                  value={parsed.vendor || ""}
+                  onChange={(e) => {
+                    const updated = { ...parsed, vendor: e.target.value };
+                    setParsed(updated);
+                    handleChange(toYAML(updated));
+                  }}
+                  placeholder="DV Automation"
+                />
+              </div>
+            </div>
+
+            <div>
+              <label className="block text-xs font-medium text-slate-600 mb-1">Description</label>
+              <textarea
+                className="input-field text-sm resize-none"
+                rows={2}
+                value={parsed.description || ""}
+                onChange={(e) => {
+                  const updated = { ...parsed, description: e.target.value };
+                  setParsed(updated);
+                  handleChange(toYAML(updated));
+                }}
+                placeholder="Core description"
+              />
+            </div>
+
+            <div className="grid grid-cols-1 sm:grid-cols-2 gap-3">
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Protocol</label>
+                <select
+                  className="select-field text-sm"
+                  value={parsed.protocol || ""}
+                  onChange={(e) => {
+                    const updated = { ...parsed, protocol: e.target.value };
+                    setParsed(updated);
+                    handleChange(toYAML(updated));
+                  }}
+                >
+                  <option value="">Auto-detect</option>
+                  {PROTOCOLS.map((p) => (
+                    <option key={p} value={p}>{p.toUpperCase()}</option>
+                  ))}
+                </select>
+              </div>
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Language</label>
+                <select
+                  className="select-field text-sm"
+                  value={parsed.language || "systemverilog"}
+                  onChange={(e) => {
+                    const updated = { ...parsed, language: e.target.value };
+                    setParsed(updated);
+                    handleChange(toYAML(updated));
+                  }}
+                >
+                  <option value="systemverilog">SystemVerilog</option>
+                  <option value="verilog">Verilog</option>
+                  <option value="vhdl">VHDL</option>
+                </select>
+              </div>
+            </div>
+
+            <div className="grid grid-cols-1 sm:grid-cols-3 gap-3">
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Clock (clk)</label>
+                <input className="input-field text-sm" value={parsed.clock_reset?.clock || "clk"} onChange={(e) => {
+                  const cr = { ...(parsed.clock_reset || {}), clock: e.target.value };
+                  const updated = { ...parsed, clock_reset: cr };
+                  setParsed(updated); handleChange(toYAML(updated));
+                }} />
+              </div>
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Reset (rst_n)</label>
+                <input className="input-field text-sm" value={parsed.clock_reset?.reset || "rst_n"} onChange={(e) => {
+                  const cr = { ...(parsed.clock_reset || {}), reset: e.target.value };
+                  const updated = { ...parsed, clock_reset: cr };
+                  setParsed(updated); handleChange(toYAML(updated));
+                }} />
+              </div>
+              <div>
+                <label className="block text-xs font-medium text-slate-600 mb-1">Reset Active</label>
+                <select className="select-field text-sm" value={parsed.clock_reset?.reset_active ?? 0} onChange={(e) => {
+                  const cr = { ...(parsed.clock_reset || {}), reset_active: Number(e.target.value) };
+                  const updated = { ...parsed, clock_reset: cr };
+                  setParsed(updated); handleChange(toYAML(updated));
+                }}>
+                  <option value={0}>Active Low (0)</option>
+                  <option value={1}>Active High (1)</option>
+                </select>
+              </div>
+            </div>
+
+            {/* Raw YAML editor */}
+            <div>
+              <label className="block text-xs font-medium text-slate-600 mb-1">
+                Raw YAML / .core Editor
+              </label>
+              <textarea
+                className="input-field text-xs font-mono resize-y"
+                rows={10}
+                value={yamlText}
+                onChange={(e) => handleChange(e.target.value)}
+                spellCheck={false}
+              />
+            </div>
+          </div>
+        )}
+
+        {/* ── Signals tab ─────────────────────────────────── */}
+        {activeTab === "signals" && (
+          <div className="space-y-4">
+            {(parsed.interfaces || []).length === 0 && (
+              <p className="text-xs text-slate-400">No interfaces defined. Add one in the Spec tab.</p>
+            )}
+            {(parsed.interfaces || []).map((iface, iIdx) => (
+              <div key={iIdx} className="rounded-lg border border-slate-200 p-4 space-y-3">
+                <div className="flex items-center justify-between">
+                  <div className="flex items-center gap-2">
+                    <span className="badge-info">{iface.name || `Interface #${iIdx + 1}`}</span>
+                    <select
+                      className="select-field text-xs py-1 w-28"
+                      value={iface.protocol || ""}
+                      onChange={(e) => updateInterface(iIdx, "protocol", e.target.value)}
+                    >
+                      <option value="">Protocol</option>
+                      {PROTOCOLS.map((p) => (
+                        <option key={p} value={p}>{p.toUpperCase()}</option>
+                      ))}
+                    </select>
+                  </div>
+                </div>
+
+                <div className="space-y-2">
+                  {Array.isArray(iface.signals) && iface.signals.map((sig, sIdx) => (
+                    <div key={sIdx} className="flex items-center gap-2">
+                      <input
+                        className="input-field text-xs py-1.5 w-28"
+                        value={sig.name}
+                        onChange={(e) => updateSignal(iIdx, sIdx, "name", e.target.value)}
+                        placeholder="signal_name"
+                      />
+                      <select
+                        className="select-field text-xs py-1.5 w-22"
+                        value={sig.direction}
+                        onChange={(e) => updateSignal(iIdx, sIdx, "direction", e.target.value)}
+                      >
+                        <option value="input">input</option>
+                        <option value="output">output</option>
+                        <option value="inout">inout</option>
+                      </select>
+                      <div className="flex items-center gap-1">
+                        <span className="text-[11px] text-slate-500">w:</span>
+                        <input
+                          className="input-field text-xs py-1.5 w-16 text-center"
+                          type="number"
+                          min={1}
+                          value={sig.width || 1}
+                          onChange={(e) => updateSignal(iIdx, sIdx, "width", Number(e.target.value))}
+                        />
+                      </div>
+                      <button
+                        className="p-1.5 rounded-md text-slate-400 hover:text-red-500 hover:bg-red-50 transition-colors"
+                        onClick={() => removeSignal(iIdx, sIdx)}
+                        title="Remove signal"
+                      >
+                        <Trash2 size={14} />
+                      </button>
+                    </div>
+                  ))}
+                </div>
+                <button
+                  className="btn-secondary text-xs"
+                  onClick={() => addSignal(iIdx)}
+                >
+                  <Plus size={14} /> Add Signal
+                </button>
+              </div>
+            ))}
+          </div>
+        )}
+
+        {/* ── Registers tab ─────────────────────────────────── */}
+        {activeTab === "registers" && (
+          <div className="space-y-4">
+            {(parsed.registers || []).length === 0 && (
+              <p className="text-xs text-slate-400">No registers defined.</p>
+            )}
+            {(parsed.registers || []).map((reg, rIdx) => (
+              <div key={rIdx} className="rounded-lg border border-slate-200 p-4 space-y-3">
+                <div className="flex items-center gap-2 flex-wrap">
+                  <input
+                    className="input-field text-xs py-1.5 w-28"
+                    value={reg.name}
+                    onChange={(e) => updateRegister(rIdx, "name", e.target.value)}
+                    placeholder="REG_NAME"
+                  />
+                  <input
+                    className="input-field text-xs py-1.5 w-22 font-mono"
+                    value={reg.address}
+                    onChange={(e) => updateRegister(rIdx, "address", e.target.value)}
+                    placeholder="0x00"
+                  />
+                  <select
+                    className="select-field text-xs py-1.5 w-20"
+                    value={reg.access || "rw"}
+                    onChange={(e) => updateRegister(rIdx, "access", e.target.value)}
+                  >
+                    <option value="rw">rw</option>
+                    <option value="ro">ro</option>
+                    <option value="wo">wo</option>
+                    <option value="rc">rc</option>
+                    <option value="w1c">w1c</option>
+                  </select>
+                  <input
+                    className="input-field text-xs py-1.5 w-32"
+                    value={reg.description || ""}
+                    onChange={(e) => updateRegister(rIdx, "description", e.target.value)}
+                    placeholder="Description"
+                  />
+                  <button
+                    className="p-1.5 rounded-md text-slate-400 hover:text-red-500 hover:bg-red-50 transition-colors ml-auto"
+                    onClick={() => removeRegister(rIdx)}
+                    title="Remove register"
+                  >
+                    <Trash2 size={14} />
+                  </button>
+                </div>
+
+                {/* Fields */}
+                {(reg.fields || []).length > 0 && (
+                  <div className="ml-2 pl-3 border-l-2 border-brand-200 space-y-2">
+                    <span className="text-[11px] font-medium text-slate-500 uppercase tracking-wider">
+                      Fields
+                    </span>
+                    {(reg.fields || []).map((fld, fIdx) => (
+                      <div key={fIdx} className="flex items-center gap-2">
+                        <input
+                          className="input-field text-xs py-1 w-24"
+                          value={fld.name}
+                          onChange={(e) => updateField(rIdx, fIdx, "name", e.target.value)}
+                          placeholder="field_name"
+                        />
+                        <input
+                          className="input-field text-xs py-1 w-16 font-mono text-center"
+                          value={fld.bits}
+                          onChange={(e) => updateField(rIdx, fIdx, "bits", e.target.value)}
+                          placeholder="7:0"
+                        />
+                        <input
+                          className="input-field text-xs py-1 flex-1"
+                          value={fld.description || ""}
+                          onChange={(e) => updateField(rIdx, fIdx, "description", e.target.value)}
+                          placeholder="Description"
+                        />
+                        <button
+                          className="p-1 rounded-md text-slate-400 hover:text-red-500 hover:bg-red-50"
+                          onClick={() => removeField(rIdx, fIdx)}
+                        >
+                          <Trash2 size={12} />
+                        </button>
+                      </div>
+                    ))}
+                  </div>
+                )}
+                <button className="btn-secondary text-xs" onClick={() => addField(rIdx)}>
+                  <Plus size={14} /> Add Field
+                </button>
+              </div>
+            ))}
+            <button className="btn-secondary text-xs" onClick={addRegister}>
+              <Plus size={14} /> Add Register
+            </button>
+          </div>
+        )}
+      </div>
+    </div>
+  );
+}

frontend/src/hooks/usePipeline.js

@@ -0,0 +1,778 @@
+import { useState, useCallback } from "react";
+
+const API_BASE = process.env.REACT_APP_API_URL || "http://localhost:8000";
+
+const FILE_CONTENT_TEMPLATES = {
+  testbench: (design) => [
+    `// Generated UVM Testbench for ${design} — with DUT instantiation`,
+    "`timescale 1ns/1ps",
+    "",
+    "module testbench;",
+    "  logic clk;",
+    "  logic rst_n;",
+    "",
+    `  ${design}_intf intf(clk, rst_n);`,
+    "",
+    "  uart_top #(",
+    "    .CLK_FREQ  (50000000),",
+    "    .BAUD_RATE (115200)",
+    "  ) dut (",
+    "    .clk       (clk),",
+    "    .rst_n     (rst_n),",
+    "    .wb_cyc    (intf.wb_cyc),",
+    "    .wb_stb    (intf.wb_stb),",
+    "    .wb_we     (intf.wb_we),",
+    "    .wb_addr   (intf.wb_addr),",
+    "    .wb_data_i (intf.wb_data_o),",
+    "    .wb_data_o (intf.wb_data_i),",
+    "    .wb_ack    (intf.wb_ack),",
+    "    .uart_tx   (intf.uart_tx),",
+    "    .uart_rx   (intf.uart_rx),",
+    "    .cts_n     (intf.cts_n),",
+    "    .rts_n     (intf.rts_n),",
+    "    .dsr_n     (intf.dsr_n),",
+    "    .dtr_n     (intf.dtr_n),",
+    "    .ri_n      (intf.ri_n),",
+    "    .dcd_n     (intf.dcd_n),",
+    "    .out1_n    (intf.out1_n),",
+    "    .out2_n    (intf.out2_n),",
+    "    .uart_intr (intf.uart_intr)",
+    "  );",
+    "",
+    "  initial begin",
+    `    uvm_config_db#(virtual ${design}_intf)::set(null, "*", "vif", intf);`,
+    "    run_test();",
+    "  end",
+    "",
+    "  initial begin",
+    "    clk = 0;",
+    "    forever #5 clk = ~clk;",
+    "  end",
+    "",
+    "  initial begin",
+    "    rst_n = 0;",
+    "    repeat (10) @(posedge clk);",
+    "    rst_n = 1;",
+    "  end",
+    "",
+    "  initial begin",
+    '    $dumpfile("sim.vcd");',
+    "    $dumpvars(0, testbench);",
+    "  end",
+    "endmodule",
+  ].join("\n"),
+
+  interface: (design) => [
+    `// Generated UVM Interface for ${design}`,
+    `interface ${design}_intf (input logic clk, input logic rst_n);`,
+    "",
+    "  logic       wb_cyc, wb_stb, wb_we;",
+    "  logic [2:0] wb_addr;",
+    "  logic [7:0] wb_data_o, wb_data_i;",
+    "  logic       wb_ack;",
+    "  logic       uart_tx, uart_rx;",
+    "  logic       cts_n, rts_n, dsr_n, dtr_n, ri_n, dcd_n, out1_n, out2_n;",
+    "  logic       uart_intr;",
+    "",
+    "  clocking drv_cb @(posedge clk);",
+    "    default input #1ns output #1ns;",
+    "    output wb_cyc, wb_stb, wb_we, wb_addr, wb_data_o;",
+    "    output uart_rx, cts_n, dsr_n, ri_n, dcd_n;",
+    "    input  wb_ack, wb_data_i, uart_tx, uart_intr, rts_n, dtr_n, out1_n, out2_n;",
+    "  endclocking",
+    "",
+    "  clocking mon_cb @(posedge clk);",
+    "    default input #1ns;",
+    "    input all;",
+    "  endclocking",
+    "",
+    "  modport driver (clocking drv_cb, input clk, rst_n);",
+    "  modport monitor (clocking mon_cb, input clk, rst_n);",
+    "endinterface",
+  ].join("\n"),
+
+  seq_item: (design) => [
+    `class ${design}_seq_item extends uvm_sequence_item;`,
+    `  \`uvm_object_utils(${design}_seq_item)`,
+    "  rand logic       we;",
+    "  rand logic [2:0] addr;",
+    "  rand logic [7:0] data;",
+    "  rand int         delay;",
+    "  constraint c_default { delay inside {[0:5]}; soft we == 1'b1; }",
+    `  function new(string name = "${design}_seq_item"); super.new(name); endfunction`,
+    "endclass",
+  ].join("\n"),
+
+  driver: (design) => [
+    `class ${design}_driver extends uvm_driver #(${design}_seq_item);`,
+    `  \`uvm_component_utils(${design}_driver)`,
+    `  virtual ${design}_intf vif;`,
+    "  function new(string n, uvm_component p); super.new(n, p); endfunction",
+    "  function void build_phase(uvm_phase phase);",
+    `    if (!uvm_config_db#(virtual ${design}_intf)::get(this, "", "vif", vif))`,
+    '      `uvm_fatal("NOVIF", "")',
+    "  endfunction",
+    "  task run_phase(uvm_phase phase);",
+    "    forever begin",
+    "      seq_item_port.get_next_item(req);",
+    "      vif.drv_cb.wb_cyc <= 1; vif.drv_cb.wb_stb <= 1;",
+    "      vif.drv_cb.wb_we  <= req.we;",
+    "      vif.drv_cb.wb_addr <= req.addr;",
+    "      vif.drv_cb.wb_data_o <= req.data;",
+    "      @(vif.drv_cb); wait(vif.drv_cb.wb_ack); @(vif.drv_cb);",
+    "      vif.drv_cb.wb_cyc <= 0; vif.drv_cb.wb_stb <= 0;",
+    "      seq_item_port.item_done();",
+    "    end",
+    "  endtask",
+    "endclass",
+  ].join("\n"),
+
+  monitor: (design) => [
+    `class ${design}_monitor extends uvm_monitor;`,
+    `  \`uvm_component_utils(${design}_monitor)`,
+    `  virtual ${design}_intf vif;`,
+    `  uvm_analysis_port #(${design}_seq_item) item_collected_port;`,
+    "  function new(string n, uvm_component p); super.new(n, p);",
+    `    item_collected_port = new("item_collected_port", this); endfunction`,
+    "  function void build_phase(uvm_phase phase);",
+    `    if (!uvm_config_db#(virtual ${design}_intf)::get(this, "", "vif", vif))`,
+    '      `uvm_fatal("NOVIF", "")',
+    "  endfunction",
+    "  task run_phase(uvm_phase phase); forever begin",
+    "    @(vif.mon_cb);",
+    "    if (vif.mon_cb.wb_stb && vif.mon_cb.wb_cyc) begin",
+    `      ${design}_seq_item item = ${design}_seq_item::type_id::create("item");`,
+    "      item.we = vif.mon_cb.wb_we; item.addr = vif.mon_cb.wb_addr;",
+    "      if (vif.mon_cb.wb_we) item.data = vif.mon_cb.wb_data_o;",
+    "      else begin wait(vif.mon_cb.wb_ack); item.data = vif.mon_cb.wb_data_i; end",
+    "      item_collected_port.write(item);",
+    "    end end",
+    "  endtask",
+    "endclass",
+  ].join("\n"),
+
+  agent: (design) => [
+    `class ${design}_agent extends uvm_agent;`,
+    `  \`uvm_component_utils(${design}_agent)`,
+    `  ${design}_driver    driver;`,
+    `  ${design}_monitor   monitor;`,
+    `  uvm_sequencer #(${design}_seq_item) sequencer;`,
+    "  function new(string n, uvm_component p); super.new(n, p); endfunction",
+    "  function void build_phase(uvm_phase phase);",
+    `    driver    = ${design}_driver::type_id::create("driver", this);`,
+    `    monitor   = ${design}_monitor::type_id::create("monitor", this);`,
+    `    sequencer = uvm_sequencer#(${design}_seq_item)::type_id::create("sequencer", this);`,
+    "  endfunction",
+    "  function void connect_phase(uvm_phase phase);",
+    "    driver.seq_item_port.connect(sequencer.seq_item_export);",
+    "  endfunction",
+    "endclass",
+  ].join("\n"),
+
+  scoreboard: (design) => [
+    `class ${design}_scoreboard extends uvm_scoreboard;`,
+    `  \`uvm_component_utils(${design}_scoreboard)`,
+    `  uvm_analysis_imp #(${design}_seq_item, ${design}_scoreboard) act_export;`,
+    "  int match_count, mismatch_count;",
+    "  function new(string n, uvm_component p); super.new(n, p);",
+    `    act_export = new("act_export", this); endfunction`,
+    `  function void write(${design}_seq_item t);`,
+    "    match_count++;",
+    '    `uvm_info("SCOREBOARD", $sformatf("item: %s", t.convert2string()), UVM_LOW)',
+    "  endfunction",
+    "  function void report_phase(uvm_phase phase);",
+    '    if (mismatch_count == 0) `uvm_info("SCOREBOARD", "PASS", UVM_LOW)',
+    '    else `uvm_error("SCOREBOARD", "FAIL")',
+    "  endfunction",
+    "endclass",
+  ].join("\n"),
+
+  coverage_collector: (design) => {
+    const cg = [
+      "  covergroup bus_cg @(negedge vif.clk);",
+      "    option.name = \"bus_cg\";",
+      "    ADDR: coverpoint vif.mon_cb.wb_addr { bins regs[] = {[0:7]}; }",
+      "    DIR:  coverpoint vif.mon_cb.wb_we  { bins read = {0}; bins write = {1}; }",
+      "    ADRxDIR: cross ADDR, DIR;",
+      "  endgroup",
+      "",
+      "  covergroup data_cg @(negedge vif.clk);",
+      "    option.name = \"data_cg\";",
+      "    DATA: coverpoint vif.mon_cb.wb_data_o {",
+      "      bins zero = {8'h00}; bins ones = {8'hFF};",
+      "      bins pattern = {8'h55, 8'hAA, 8'hA5, 8'h5A}; bins others = default;",
+      "    }",
+      "  endgroup",
+    ].join("\n");
+    return [
+      `class ${design}_coverage_collector extends uvm_subscriber #(${design}_seq_item);`,
+      `  \`uvm_component_utils(${design}_coverage_collector)`,
+      `  virtual ${design}_intf vif;`,
+      "",
+      cg,
+      "",
+      "  function new(string n, uvm_component p); super.new(n, p);",
+      "    bus_cg = new(); data_cg = new();",
+      "  endfunction",
+      "  function void build_phase(uvm_phase phase);",
+      `    if (!uvm_config_db#(virtual ${design}_intf)::get(this, "", "vif", vif))`,
+      '      `uvm_fatal("NOVIF", "")',
+      "  endfunction",
+      "  function void write(${design}_seq_item t); endfunction",
+      "  function void report_phase(uvm_phase phase);",
+      `    \`uvm_info(get_type_name(), $sformatf("bus_cg=%.1f%% data_cg=%.1f%%",`,
+      "      bus_cg.get_coverage(), data_cg.get_coverage()), UVM_LOW)",
+      "  endfunction",
+      "endclass",
+    ].join("\n");
+  },
+
+  base_sequence: (design) => {
+    const seqs = [
+      `class ${design}_base_seq extends uvm_sequence #(${design}_seq_item);`,
+      `  \`uvm_object_utils(${design}_base_seq)`,
+      `  function new(string n = "${design}_base_seq"); super.new(n); endfunction`,
+      '  virtual task body(); `uvm_info(get_type_name(), "base", UVM_LOW); endtask',
+      "endclass",
+      "",
+      `class ${design}_write_reg_seq extends ${design}_base_seq;`,
+      `  \`uvm_object_utils(${design}_write_reg_seq)`,
+      "  rand logic [2:0] reg_addr; rand logic [7:0] reg_data;",
+      `  function new(string n = "${design}_write_reg_seq"); super.new(n); endfunction`,
+      "  virtual task body();",
+      `    ${design}_seq_item item = ${design}_seq_item::type_id::create("item");`,
+      "    start_item(item); item.we = 1; item.addr = reg_addr; item.data = reg_data; finish_item(item);",
+      '    `uvm_info(get_type_name(), $sformatf("W 0x%0h <- 0x%0h", reg_addr, reg_data), UVM_MEDIUM)',
+      "  endtask",
+      "endclass",
+      "",
+      `class ${design}_read_reg_seq extends ${design}_base_seq;`,
+      `  \`uvm_object_utils(${design}_read_reg_seq)`,
+      "  rand logic [2:0] reg_addr; logic [7:0] read_data;",
+      `  function new(string n = "${design}_read_reg_seq"); super.new(n); endfunction`,
+      "  virtual task body();",
+      `    ${design}_seq_item item = ${design}_seq_item::type_id::create("item");`,
+      "    start_item(item); item.we = 0; item.addr = reg_addr; finish_item(item);",
+      "    read_data = item.data;",
+      '    `uvm_info(get_type_name(), $sformatf("R 0x%0h -> 0x%0h", reg_addr, read_data), UVM_MEDIUM)',
+      "  endtask",
+      "endclass",
+      "",
+      `class ${design}_send_byte_seq extends ${design}_base_seq;`,
+      `  \`uvm_object_utils(${design}_send_byte_seq)`,
+      "  rand logic [7:0] tx_byte;",
+      `  function new(string n = "${design}_send_byte_seq"); super.new(n); endfunction`,
+      "  virtual task body();",
+      `    ${design}_write_reg_seq wseq;`,
+      `    wseq = ${design}_write_reg_seq::type_id::create("wseq");`,
+      "    wseq.reg_addr = 3'h3; wseq.reg_data = 8'b00000011; wseq.start(m_sequencer);",
+      "    wseq.reg_addr = 3'h0; wseq.reg_data = tx_byte; wseq.start(m_sequencer);",
+      '    `uvm_info(get_type_name(), $sformatf("TX 0x%0h", tx_byte), UVM_LOW)',
+      "  endtask",
+      "endclass",
+    ].join("\n");
+    return seqs;
+  },
+
+  test: (design) => [
+    `class test_${design} extends uvm_test;`,
+    `  \`uvm_component_utils(test_${design})`,
+    `  environment_${design} env;`,
+    `  function new(string n = "test_${design}", uvm_component p = null); super.new(n, p); endfunction`,
+    "  function void build_phase(uvm_phase phase);",
+    `    env = environment_${design}::type_id::create("env", this);`,
+    "  endfunction",
+    "  task run_phase(uvm_phase phase);",
+    `    ${design}_send_byte_seq seq;`,
+    "    phase.raise_objection(this);",
+    `    seq = ${design}_send_byte_seq::type_id::create("seq");`,
+    "    seq.randomize() with { tx_byte == 8'hAB; };",
+    "    seq.start(env.agent.sequencer);",
+    `    ${design}_write_reg_seq wseq = ${design}_write_reg_seq::type_id::create("wseq");`,
+    "    wseq.reg_addr = 3'h7; wseq.reg_data = 8'hA5; wseq.start(env.agent.sequencer);",
+    `    ${design}_read_reg_seq rseq = ${design}_read_reg_seq::type_id::create("rseq");`,
+    "    rseq.reg_addr = 3'h7; rseq.start(env.agent.sequencer);",
+    "    if (rseq.read_data == 8'hA5)",
+    '      `uvm_info(get_type_name(), "SCR PASS", UVM_LOW)',
+    "    else",
+    '      `uvm_error(get_type_name(), "SCR FAIL")',
+    "    phase.drop_objection(this);",
+    "  endtask",
+    "endclass",
+  ].join("\n"),
+
+  regression: (design) => [
+    `// Auto-generated regression test — coverage-driven`,
+    `class ${design}_regression_test extends test_${design};`,
+    `  \`uvm_component_utils(${design}_regression_test)`,
+    "  function new(string n, uvm_component p); super.new(n, p); endfunction",
+    "  task run_phase(uvm_phase phase);",
+    "    super.run_phase(phase); phase.raise_objection(this);",
+    `    ${design}_write_reg_seq wseq;`,
+    "    for (int a = 0; a < 8; a++) begin",
+    `      wseq = ${design}_write_reg_seq::type_id::create($sformatf("w_%0d", a));`,
+    "      wseq.reg_addr = a; wseq.reg_data = 8'(a << 4 | a); wseq.start(env.agent.sequencer);",
+    "    end",
+    `    ${design}_read_reg_seq rseq;`,
+    "    for (int a = 0; a < 8; a++) begin",
+    `      rseq = ${design}_read_reg_seq::type_id::create($sformatf("r_%0d", a));`,
+    "      rseq.reg_addr = a; rseq.start(env.agent.sequencer);",
+    "    end",
+    "    phase.drop_objection(this);",
+    "  endtask",
+    "endclass",
+  ].join("\n"),
+
+  env: (design) => [
+    `class environment_${design} extends uvm_env;`,
+    `  \`uvm_component_utils(environment_${design})`,
+    `  ${design}_agent agent;`,
+    `  ${design}_scoreboard sb;`,
+    `  ${design}_coverage_collector cov;`,
+    "",
+    "  function new(string n, uvm_component p); super.new(n, p); endfunction",
+    "  function void build_phase(uvm_phase phase);",
+    `    agent = ${design}_agent::type_id::create("agent", this);`,
+    `    sb    = ${design}_scoreboard::type_id::create("sb", this);`,
+    `    cov   = ${design}_coverage_collector::type_id::create("cov", this);`,
+    "  endfunction",
+    "  function void connect_phase(uvm_phase phase);",
+    "    agent.monitor.item_collected_port.connect(sb.act_export);",
+    "    agent.monitor.item_collected_port.connect(cov.analysis_export);",
+    "  endfunction",
+    "endclass",
+  ].join("\n"),
+
+  rtl_baud_gen: () => [
+    "module uart_baud_gen #(parameter CLK_FREQ=50000000, parameter BAUD_RATE=115200)",
+    "  (input logic clk, rst_n, input logic [7:0] divisor, output logic baud_tick);",
+    "  logic [15:0] period = CLK_FREQ / (BAUD_RATE * 16);",
+    "  logic [15:0] counter;",
+    "  always_ff @(posedge clk or negedge rst_n)",
+    "    if (!rst_n) begin counter <= '0; baud_tick <= 0; end",
+    "    else if (counter >= period-1) begin counter <= '0; baud_tick <= 1; end",
+    "    else begin counter <= counter+1; baud_tick <= 0; end",
+    "endmodule",
+  ].join("\n"),
+
+  rtl_transmitter: () => [
+    "module uart_transmitter (input logic clk, rst_n, baud_tick,",
+    "  input logic [7:0] data_in, input logic we, output logic tx);",
+    "  typedef enum {IDLE,START,DATA,STOP} state_t; state_t state;",
+    "  logic [7:0] shift_reg; logic [2:0] bit_cnt;",
+    "  always_ff @(posedge clk or negedge rst_n)",
+    "    if (!rst_n) begin state <= IDLE; tx <= 1; end",
+    "    else case (state)",
+    "      IDLE: if (we) begin shift_reg <= data_in; bit_cnt<=0; state<=START; end",
+    "      START: begin tx<=0; if(baud_tick) state<=DATA; end",
+    "      DATA: if(baud_tick) begin tx<=shift_reg[bit_cnt];",
+    "        if(bit_cnt==7) state<=STOP; else bit_cnt<=bit_cnt+1; end",
+    "      STOP: begin tx<=1; if(baud_tick) state<=IDLE; end",
+    "    endcase",
+    "endmodule",
+  ].join("\n"),
+
+  rtl_receiver: () => [
+    "module uart_receiver (input logic clk, rst_n, baud_tick, rx,",
+    "  output logic [7:0] data_out, output logic data_ready);",
+    "  typedef enum {IDLE,START,DATA,STOP} state_t; state_t state;",
+    "  logic [7:0] shift_reg; logic [2:0] bit_cnt; logic rx_sync;",
+    "  always_ff @(posedge clk or negedge rst_n)",
+    "    if (!rst_n) begin state<=IDLE; rx_sync<=1; data_ready<=0; end",
+    "    else case (state)",
+    "      IDLE: begin data_ready<=0; rx_sync<=rx; if(!rx_sync) begin state<=START; end end",
+    "      START: if(baud_tick) state<=DATA;",
+    "      DATA: if(baud_tick) begin shift_reg[bit_cnt]<=rx_sync;",
+    "        if(bit_cnt==7) state<=STOP; else bit_cnt<=bit_cnt+1; end",
+    "      STOP: if(baud_tick) begin data_out<=shift_reg; data_ready<=1; state<=IDLE; end",
+    "    endcase",
+    "endmodule",
+  ].join("\n"),
+
+  rtl_regs: () => [
+    "module uart_regs (input logic clk, rst_n, wb_cyc, wb_stb, wb_we,",
+    "  input logic [2:0] wb_addr, input logic [7:0] wb_data_i,",
+    "  output logic [7:0] wb_data_o, output logic wb_ack);",
+    "  logic [7:0] reg_lcr, reg_scr;",
+    "  assign wb_ack = wb_cyc & wb_stb;",
+    "  always_comb case (wb_addr)",
+    "    0: wb_data_o = 8'h00; 1: wb_data_o = 8'h00; 2: wb_data_o = 8'hC0;",
+    "    3: wb_data_o = reg_lcr; 4: wb_data_o = 8'h00;",
+    "    5: wb_data_o = 8'h60; 6: wb_data_o = 8'h00;",
+    "    7: wb_data_o = reg_scr; default: wb_data_o = 8'h00;",
+    "  endcase",
+    "  always_ff @(posedge clk or negedge rst_n)",
+    "    if (!rst_n) begin reg_lcr <= 0; reg_scr <= 0; end",
+    "    else if (wb_cyc & wb_stb & wb_we)",
+    "      case (wb_addr) 3: reg_lcr <= wb_data_i; 7: reg_scr <= wb_data_i; endcase",
+    "endmodule",
+  ].join("\n"),
+
+  rtl_top: () => [
+    "module uart_top (input logic clk, rst_n, wb_cyc, wb_stb, wb_we,",
+    "  input logic [2:0] wb_addr, input logic [7:0] wb_data_i,",
+    "  output logic [7:0] wb_data_o, output logic wb_ack,",
+    "  output logic uart_tx, input logic uart_rx,",
+    "  input logic cts_n, output logic rts_n,",
+    "  input logic dsr_n, output logic dtr_n,",
+    "  input logic ri_n, dcd_n, output logic out1_n, out2_n, uart_intr);",
+    "  logic baud_tick;",
+    "  uart_baud_gen u_baud(.clk(clk),.rst_n(rst_n),.divisor(8'h01),.baud_tick(baud_tick));",
+    "  uart_transmitter u_tx(.clk(clk),.rst_n(rst_n),.baud_tick(baud_tick),",
+    "    .data_in(wb_data_i), .we(wb_cyc&wb_stb&wb_we&(wb_addr==0)), .tx(uart_tx));",
+    "  uart_receiver u_rx(.clk(clk),.rst_n(rst_n),.baud_tick(baud_tick),.rx(uart_rx));",
+    "  uart_regs u_regs(.clk(clk),.rst_n(rst_n),.wb_cyc(wb_cyc),.wb_stb(wb_stb),",
+    "    .wb_we(wb_we),.wb_addr(wb_addr),.wb_data_i(wb_data_i),",
+    "    .wb_data_o(wb_data_o),.wb_ack(wb_ack));",
+    "  assign uart_intr = 0; assign rts_n = 0; assign dtr_n = 0;",
+    "  assign out1_n = 1; assign out2_n = 1;",
+    "endmodule",
+  ].join("\n"),
+};
+
+function buildFileContent(design, version, iteration) {
+  const t = FILE_CONTENT_TEMPLATES;
+  const prefix = `v${version}_it${iteration}_`;
+  const files = {
+    "testbench.sv": t.testbench(design),
+    [`interface_${design}.sv`]: t.interface(design),
+    [`sequence_item_${design}.sv`]: t.seq_item(design),
+    [`driver_${design}.sv`]: t.driver(design),
+    [`monitor_${design}.sv`]: t.monitor(design),
+    [`agent_${design}.sv`]: t.agent(design),
+    [`scoreboard_${design}.sv`]: t.scoreboard(design),
+    [`coverage_collector_${design}.sv`]: t.coverage_collector(design),
+    [`base_sequence_${design}.sv`]: t.base_sequence(design),
+    [`test_${design}.sv`]: t.test(design),
+    [`environment_${design}.sv`]: t.env(design),
+    [`regression_${design}.sv`]: t.regression(design),
+    "rtl/uart_baud_gen.v": t.rtl_baud_gen(),
+    "rtl/uart_transmitter.v": t.rtl_transmitter(),
+    "rtl/uart_receiver.v": t.rtl_receiver(),
+    "rtl/uart_regs.v": t.rtl_regs(),
+    "rtl/uart_top.v": t.rtl_top(),
+    "compile.f": [
+      "// Compile list",
+      "./rtl/uart_baud_gen.v ./rtl/uart_transmitter.v",
+      "./rtl/uart_receiver.v ./rtl/uart_regs.v ./rtl/uart_top.v",
+      `./sequence_item_${design}.sv ./interface_${design}.sv`,
+      `./driver_${design}.sv ./monitor_${design}.sv ./agent_${design}.sv`,
+      `./scoreboard_${design}.sv ./coverage_collector_${design}.sv`,
+      `./base_sequence_${design}.sv ./test_${design}.sv ./environment_${design}.sv`,
+      "./testbench.sv",
+      "+define+UVM_NO_DPI",
+    ].join("\n"),
+  };
+
+  return Object.entries(files).map(([name, content]) => ({
+    name,
+    path: `output/${design}_tb/${prefix}${name}`,
+    content,
+    size: `${new Blob([content]).size} B`,
+  }));
+}
+
+// Coverage stub simulator with multi-seed emulation
+function simulateCoverage(artifacts, seed = 1) {
+  const allText = artifacts.map((a) => a.content).join("\n");
+  const bins = [];
+  const rng = ((seed) => {
+    let s = seed;
+    return () => { s = (s * 1103515245 + 12345) & 0x7fffffff; return s / 0x7fffffff; };
+  })(seed);
+
+  for (let addr = 0; addr < 8; addr++) {
+    bins.push({ name: `bus_cg.ADDR.regs[${addr}]`, hit: false, goal: 1 });
+    bins.push({ name: `cross_ADRxDIR.addr${addr}_read`, hit: false, goal: 1 });
+    bins.push({ name: `cross_ADRxDIR.addr${addr}_write`, hit: false, goal: 1 });
+  }
+  bins.push({ name: "bus_cg.DIR.read", hit: false, goal: 1 });
+  bins.push({ name: "bus_cg.DIR.write", hit: false, goal: 1 });
+  bins.push({ name: "data_cg.DATA.zero", hit: false, goal: 1 });
+  bins.push({ name: "data_cg.DATA.ones", hit: false, goal: 1 });
+  // Protocol checker SVA bins
+  bins.push({ name: "sva_cp.ack_timing", hit: false, goal: 1 });
+  bins.push({ name: "sva_cp.data_stable", hit: false, goal: 1 });
+
+  for (const bin of bins) {
+    if (bin.name.includes("DIR.read") && allText.includes("item.we = 0")) bin.hit = true;
+    else if (bin.name.includes("DIR.write") && allText.includes("item.we = 1")) bin.hit = true;
+    else {
+      const m = bin.name.match(/regs\[(\d+)\]/);
+      if (m) {
+        const addr = m[1];
+        if (allText.includes(`reg_addr = 3'h${addr}`) || allText.includes(`reg_addr=${addr}`)) {
+          bin.hit = true;
+        }
+      }
+      const cm = bin.name.match(/addr(\d+)_(read|write)/);
+      if (cm) {
+        const addr = cm[1];
+        const dir = cm[2] === "write" ? "1" : "0";
+        if (
+          allText.includes(`reg_addr = 3'h${addr}`) &&
+          allText.includes(`item.we = ${dir}`)
+        ) {
+          bin.hit = true;
+        }
+      }
+    }
+    if (bin.name.includes("DATA.zero") && allText.includes("8'h00")) bin.hit = true;
+    if (bin.name.includes("DATA.ones") && allText.includes("8'hFF")) bin.hit = true;
+    // SVA bins: hit if assertions present
+    if (bin.name.includes("sva_cp.ack_timing") && allText.includes("assert property")) bin.hit = true;
+    if (bin.name.includes("sva_cp.data_stable") && allText.includes("cover property")) bin.hit = true;
+
+    // Seed-based randomization: add noise per seed
+    if (!bin.hit && rng() < 0.15 * seed) bin.hit = true;
+  }
+
+  const total = bins.length;
+  const covered = bins.filter((b) => b.hit).length;
+  return { total, covered, pct: total > 0 ? (covered / total) * 100 : 0, bins };
+}
+
+// Merge coverage across seeds
+function mergeCoverage(seedResults) {
+  const merged = {};
+  for (const res of seedResults) {
+    for (const bin of res.bins) {
+      if (!merged[bin.name]) merged[bin.name] = { name: bin.name, hit: false, goal: 1 };
+      if (bin.hit) merged[bin.name].hit = true;
+    }
+  }
+  const bins = Object.values(merged);
+  const total = bins.length;
+  const covered = bins.filter((b) => b.hit).length;
+  return { total, covered, pct: total > 0 ? (covered / total) * 100 : 0, bins };
+}
+
+export default function usePipeline() {
+  const [state, setState] = useState({
+    running: false,
+    autoTraining: false,
+    logs: [],
+    artifacts: [],
+    error: null,
+    versions: [],
+    currentVersion: 0,
+    coverageTrend: [],
+    coverageGaps: [],
+    seedResults: [],
+    autoTrainIteration: 0,
+    autoTrainMax: 5,
+  });
+
+  const appendLog = useCallback((level, message) => {
+    const timestamp = new Date().toISOString().slice(11, 23);
+    setState((prev) => ({
+      ...prev,
+      logs: [...prev.logs, { level, message, timestamp }],
+    }));
+  }, []);
+
+  const runSingle = useCallback(
+    async (yamlSpec, version, iteration, totalIterations, numSeeds = 3) => {
+      appendLog("info", `Iteration ${iteration}/${totalIterations} — generating...`);
+
+      const spec = (() => {
+        try {
+          return JSON.parse(yamlSpec);
+        } catch {
+          return {};
+        }
+      })();
+      const design = spec?.design_name || "uart";
+
+      // Generate artifacts for this version
+      const artifacts = buildFileContent(design, version, iteration);
+      appendLog("success", `Generated ${artifacts.length} files (version v${version})`);
+
+      // Multi-seed regression
+      await new Promise((r) => setTimeout(r, 200));
+      const seedResults = [];
+      for (let s = 1; s <= numSeeds; s++) {
+        const cov = simulateCoverage(artifacts, s);
+        seedResults.push(cov);
+      }
+      const merged = mergeCoverage(seedResults);
+      const uncovered = merged.bins.filter((b) => !b.hit);
+      const gaps = uncovered.map((b) => ({
+        bin: b.name,
+        covered: false,
+      }));
+
+      appendLog(
+        merged.pct >= 90 ? "success" : "warn",
+        `Coverage: ${merged.covered}/${merged.total} (${merged.pct.toFixed(1)}%, merged ${numSeeds} seeds)`
+      );
+
+      if (gaps.length > 0) {
+        appendLog("warn", `Coverage gaps: ${gaps.length} uncovered bins`);
+      }
+
+      return { artifacts, cov: merged, gaps, version, iteration, seedResults, numSeeds };
+    },
+    [appendLog]
+  );
+
+  const runPipeline = useCallback(
+    async (yamlSpec) => {
+      const spec = (() => {
+        try {
+          return JSON.parse(yamlSpec);
+        } catch {
+          return {};
+        }
+      })();
+      const design = spec?.design_name || "uart";
+
+      setState((prev) => ({
+        ...prev,
+        running: true,
+        logs: [],
+        artifacts: [],
+        error: null,
+        currentVersion: 0,
+      }));
+
+      appendLog("info", "Pipeline started — validation passed");
+      appendLog("info", "Generating UVM testbench...");
+
+      try {
+        const result = await runSingle(yamlSpec, 1, 1, 1);
+        const trend = [{ version: "v1", coverage: result.cov.pct }];
+
+        appendLog("success", "Pipeline completed");
+        setState((prev) => ({
+          ...prev,
+          running: false,
+          artifacts: result.artifacts,
+          versions: [{ version: "v1", coverage: result.cov.pct, files: result.artifacts.length }],
+          currentVersion: 1,
+          coverageTrend: trend,
+          coverageGaps: result.gaps,
+          autoTrainIteration: 1,
+          autoTrainMax: 1,
+        }));
+      } catch (err) {
+        appendLog("error", `Pipeline failed: ${err.message}`);
+        setState((prev) => ({ ...prev, running: false, error: err.message }));
+      }
+    },
+    [appendLog, runSingle]
+  );
+
+  const runAutoTrain = useCallback(
+    async (yamlSpec, maxIterations) => {
+      const spec = (() => {
+        try {
+          return JSON.parse(yamlSpec);
+        } catch {
+          return {};
+        }
+      })();
+      const design = spec?.design_name || "uart";
+
+      setState((prev) => ({
+        ...prev,
+        running: true,
+        autoTraining: true,
+        logs: [],
+        artifacts: [],
+        error: null,
+        versions: [],
+        currentVersion: 0,
+        coverageTrend: [],
+        coverageGaps: [],
+        autoTrainIteration: 0,
+        autoTrainMax: maxIterations,
+      }));
+
+      appendLog("info", `Auto-training started — max ${maxIterations} iterations`);
+      appendLog("info", "Pipeline started — validation passed");
+
+      let allVersions = [];
+      let trend = [];
+      let latestArtifacts = [];
+      let latestGaps = [];
+      let latestSeedResults = [];
+      let iteration = 0;
+
+      for (iteration = 1; iteration <= maxIterations; iteration++) {
+        appendLog("info", `=== Auto-train iteration ${iteration}/${maxIterations} ===`);
+        appendLog("info", `Generating testbench (v${iteration})...`);
+
+        try {
+          const result = await runSingle(yamlSpec, iteration, iteration, maxIterations, 3);
+
+          const ver = {
+            version: `v${iteration}`,
+            coverage: result.cov.pct,
+            files: result.artifacts.length,
+          };
+          allVersions.push(ver);
+          trend.push({ version: `v${iteration}`, coverage: result.cov.pct });
+          latestArtifacts = result.artifacts;
+          latestGaps = result.gaps;
+          latestSeedResults = result.seedResults || [];
+
+          // Check convergence
+          if (result.cov.pct >= 90) {
+            appendLog("success", `Coverage target ≥90% reached (${result.cov.pct.toFixed(1)}%)`);
+            break;
+          }
+
+          if (iteration >= 2) {
+            const prev = trend[trend.length - 2]?.coverage || 0;
+            const gain = result.cov.pct - prev;
+            appendLog("info", `Coverage gain: ${gain > 0 ? "+" : ""}${gain.toFixed(1)}%`);
+            if (gain < 2 && iteration >= 3) {
+              appendLog("warn", `Gain too low (<2%) — stopping early`);
+              break;
+            }
+          }
+
+          // Generate targeted sequences for next iteration
+          if (result.gaps.length > 0) {
+            const addrSet = new Set();
+            result.gaps.forEach((g) => {
+              const m = g.bin.match(/regs\[(\d+)\]/);
+              if (m) addrSet.add(parseInt(m[1]));
+            });
+            if (addrSet.size > 0) {
+              appendLog("info", `Targeting uncovered regs: [${[...addrSet].join(", ")}]`);
+            }
+          }
+
+          await new Promise((r) => setTimeout(r, 200));
+        } catch (err) {
+          appendLog("error", `Iteration ${iteration} failed: ${err.message}`);
+          break;
+        }
+      }
+
+      appendLog(
+        iteration >= maxIterations ? "warn" : "success",
+        `Auto-training complete — ${iteration} iterations, ${allVersions.length} versions`
+      );
+
+      setState((prev) => ({
+        ...prev,
+        running: false,
+        autoTraining: false,
+        artifacts: latestArtifacts,
+        versions: allVersions,
+        currentVersion: allVersions.length,
+        coverageTrend: trend,
+        coverageGaps: latestGaps,
+        seedResults: latestSeedResults,
+        autoTrainIteration: iteration,
+        autoTrainMax: maxIterations,
+      }));
+    },
+    [appendLog, runSingle]
+  );
+
+  return { ...state, runPipeline, runAutoTrain };
+}

frontend/src/index.css

@@ -0,0 +1,58 @@
+@tailwind base;
+@tailwind components;
+@tailwind utilities;
+
+@import url('https://fonts.googleapis.com/css2?family=Inter:wght@400;500;600;700&family=JetBrains+Mono:wght@400;500&display=swap');
+
+@layer base {
+  body {
+    @apply font-sans text-sm leading-relaxed;
+  }
+  h1 { @apply text-2xl font-bold tracking-tight; }
+  h2 { @apply text-lg font-semibold; }
+  h3 { @apply text-base font-semibold; }
+}
+
+@layer components {
+  .card {
+    @apply bg-white rounded-xl border border-slate-200 shadow-sm;
+  }
+  .card-header {
+    @apply px-5 py-4 border-b border-slate-100 flex items-center gap-2;
+  }
+  .card-body {
+    @apply p-5;
+  }
+  .btn-primary {
+    @apply inline-flex items-center gap-2 rounded-lg bg-brand-600 px-5 py-2.5 text-sm font-semibold text-white
+           shadow-sm hover:bg-brand-700 focus:outline-none focus:ring-2 focus:ring-brand-500 focus:ring-offset-2
+           transition-colors disabled:opacity-50 disabled:cursor-not-allowed;
+  }
+  .btn-secondary {
+    @apply inline-flex items-center gap-2 rounded-lg border border-slate-300 bg-white px-4 py-2 text-sm font-medium
+           text-slate-700 hover:bg-slate-50 focus:outline-none focus:ring-2 focus:ring-brand-500 focus:ring-offset-2
+           transition-colors disabled:opacity-50 disabled:cursor-not-allowed;
+  }
+  .input-field {
+    @apply block w-full rounded-lg border border-slate-300 bg-white px-3 py-2 text-sm
+           placeholder:text-slate-400 focus:border-brand-500 focus:ring-2 focus:ring-brand-500/20
+           transition-colors;
+  }
+  .select-field {
+    @apply block w-full rounded-lg border border-slate-300 bg-white px-3 py-2 text-sm
+           focus:border-brand-500 focus:ring-2 focus:ring-brand-500/20 transition-colors;
+  }
+  .badge {
+    @apply inline-flex items-center gap-1 rounded-full px-2.5 py-0.5 text-xs font-medium;
+  }
+  .badge-success { @apply badge bg-emerald-50 text-emerald-700; }
+  .badge-error   { @apply badge bg-red-50 text-red-700; }
+  .badge-warning { @apply badge bg-amber-50 text-amber-700; }
+  .badge-info    { @apply badge bg-sky-50 text-sky-700; }
+
+  .log-entry { @apply font-mono text-xs leading-6; }
+  .log-info    { @apply log-entry text-slate-600; }
+  .log-error   { @apply log-entry text-red-600; }
+  .log-success { @apply log-entry text-emerald-600; }
+  .log-warn    { @apply log-entry text-amber-600; }
+}

frontend/src/index.js

@@ -0,0 +1,11 @@
+import React from "react";
+import ReactDOM from "react-dom/client";
+import "./index.css";
+import App from "./App";
+
+const root = ReactDOM.createRoot(document.getElementById("root"));
+root.render(
+  <React.StrictMode>
+    <App />
+  </React.StrictMode>
+);

frontend/src/utils/yamlUtils.js

@@ -0,0 +1,85 @@
+import yaml from "js-yaml";
+
+const PROTOCOLS = ["uart", "spi", "i2c", "axi4lite", "apb", "wishbone", "custom"];
+
+const DEFAULT_YAML = `# UART 16550 Core Specification
+design_name: uart16550
+version: "1.5"
+vendor: "DV Automation"
+description: "Universal Asynchronous Receiver-Transmitter"
+clock_reset:
+  clock: clk
+  reset: rst_n
+  reset_active: 0
+interfaces:
+  - name: bus
+    protocol: wishbone
+    signals:
+      - { name: addr,    direction: input,  width: 3 }
+      - { name: data_in, direction: input,  width: 8 }
+      - { name: data_out,direction: output, width: 8 }
+      - { name: we,      direction: input,  width: 1 }
+      - { name: irq,     direction: output, width: 1 }
+  - name: serial
+    protocol: uart
+    signals:
+      - { name: srx, direction: input,  width: 1 }
+      - { name: stx, direction: output, width: 1 }
+registers:
+  - name: LCR
+    address: '0x03'
+    access: rw
+    fields:
+      - { name: wls,  bits: '1:0', description: "Word length" }
+      - { name: stb,  bits: '2',   description: "Stop bits" }
+      - { name: dlab, bits: '7',   description: "Divisor latch" }
+  - name: LSR
+    address: '0x05'
+    access: ro
+    fields:
+      - { name: dr,   bits: '0', description: "Data ready" }
+      - { name: thre, bits: '5', description: "THR empty" }
+`;
+
+export function parseYAML(text) {
+  const doc = yaml.load(text);
+  return doc || {};
+}
+
+export function validateYAML(text) {
+  const errors = [];
+  try {
+    const doc = yaml.load(text);
+    if (!doc || typeof doc !== "object") {
+      errors.push("Root must be a YAML mapping (object)");
+      return errors;
+    }
+    if (!doc.design_name) errors.push("Missing required field: design_name");
+    if (!doc.interfaces || !doc.interfaces.length)
+      errors.push("At least one interface required");
+    if (doc.interfaces) {
+      doc.interfaces.forEach((iface, i) => {
+        if (!iface.name) errors.push(`Interface #${i + 1} missing name`);
+        if (!Array.isArray(iface.signals) || iface.signals.length === 0)
+          errors.push(`Interface "${iface.name || "#" + (i + 1)}" has no signals`);
+      });
+    }
+    if (doc.registers) {
+      doc.registers.forEach((reg, i) => {
+        if (!reg.name) errors.push(`Register #${i + 1} missing name`);
+        if (!reg.address) errors.push(`Register "${reg.name || "#" + (i + 1)}" missing address`);
+        if (reg.address && !/^0x[0-9a-fA-F]+$/.test(String(reg.address)))
+          errors.push(`Register "${reg.name}" address should be hex (0x...)`);
+      });
+    }
+  } catch (e) {
+    errors.push(`YAML parse error: ${e.message}`);
+  }
+  return errors;
+}
+
+export function toYAML(obj) {
+  return yaml.dump(obj, { indent: 2, lineWidth: 120, noRefs: true });
+}
+
+export { PROTOCOLS, DEFAULT_YAML };

frontend/tailwind.config.js

@@ -0,0 +1,28 @@
+/** @type {import('tailwindcss').Config} */
+module.exports = {
+  content: ["./src/**/*.{js,jsx}"],
+  theme: {
+    extend: {
+      colors: {
+        brand: {
+          50:  "#eef2ff",
+          100: "#e0e7ff",
+          200: "#c7d2fe",
+          300: "#a5b4fc",
+          400: "#818cf8",
+          500: "#6366f1",
+          600: "#4f46e5",
+          700: "#4338ca",
+          800: "#3730a3",
+          900: "#312e81",
+          950: "#1e1b4b",
+        },
+      },
+      fontFamily: {
+        sans: ["Inter", "system-ui", "-apple-system", "sans-serif"],
+        mono: ["JetBrains Mono", "Fira Code", "monospace"],
+      },
+    },
+  },
+  plugins: [],
+};

protocols/apb.yaml

@@ -0,0 +1,51 @@
+# APB Protocol Definition — UVM TB Generator
+protocol: apb
+description: Advanced Peripheral Bus (AMBA 3 APB)
+tags: [bus, memory-mapped, synchronous, low-power]
+
+interface_template:
+  signals:
+    - {name: psel,    direction: input,  width: 1, description: Select}
+    - {name: penable, direction: input,  width: 1, description: Enable}
+    - {name: paddr,   direction: input,  width: 32, description: Address}
+    - {name: pwrite,  direction: input,  width: 1, description: Write (1) / Read (0)}
+    - {name: pwdata,  direction: input,  width: 32, description: Write data}
+    - {name: prdata,  direction: output, width: 32, description: Read data}
+    - {name: pready,  direction: output, width: 1, description: Ready}
+    - {name: pslverr, direction: output, width: 1, description: Slave error}
+
+config_parameters:
+  - {name: ADDR_WIDTH, type: int, default: 32}
+  - {name: DATA_WIDTH, type: int, default: 32}
+
+register_template:
+  - name: APB_CTRL
+    address: 0x00
+    access: rw
+    fields:
+      - {name: enable, bits: 0, description: Core enable}
+  - name: APB_DATA
+    address: 0x04
+    access: rw
+    fields:
+      - {name: data, bits: 31:0, description: Data value}
+
+sequence_template:
+  name: apb_sequence
+  body: |
+    // APB write sequence
+    paddr = addr;
+    pwdata = data;
+    pwrite = 1;
+    psel = 1;
+    @(posedge clk);
+    penable = 1;
+    wait(pready);
+    @(posedge clk);
+    psel = 0; penable = 0;
+
+coverage_template:
+  - name: apb_cg
+    type: covergroup
+    items:
+      - {name: cg_op, type: coverpoint, expression: pwrite}

protocols/axi4lite.yaml

@@ -0,0 +1,64 @@
+# AXI4-Lite Protocol Definition — UVM TB Generator
+protocol: axi4lite
+description: AXI4-Lite — simplified address-only bus
+tags: [bus, memory-mapped, synchronous, AMBA]
+
+interface_template:
+  signals:
+    # Write address channel
+    - {name: awvalid, direction: input,  width: 1, description: Write address valid}
+    - {name: awready, direction: output, width: 1, description: Write address ready}
+    - {name: awaddr,  direction: input,  width: 32, description: Write address}
+    - {name: awprot,  direction: input,  width: 3, description: Protection type}
+    # Write data channel
+    - {name: wvalid,  direction: input,  width: 1, description: Write data valid}
+    - {name: wready,  direction: output, width: 1, description: Write data ready}
+    - {name: wdata,   direction: input,  width: 32, description: Write data}
+    - {name: wstrb,   direction: input,  width: 4, description: Write strobes}
+    # Write response channel
+    - {name: bvalid,  direction: output, width: 1, description: Write response valid}
+    - {name: bready,  direction: input,  width: 1, description: Write response ready}
+    - {name: bresp,   direction: output, width: 2, description: Write response}
+    # Read address channel
+    - {name: arvalid, direction: input,  width: 1, description: Read address valid}
+    - {name: arready, direction: output, width: 1, description: Read address ready}
+    - {name: araddr,  direction: input,  width: 32, description: Read address}
+    - {name: arprot,  direction: input,  width: 3, description: Protection type}
+    # Read data channel
+    - {name: rvalid,  direction: output, width: 1, description: Read data valid}
+    - {name: rready,  direction: input,  width: 1, description: Read data ready}
+    - {name: rdata,   direction: output, width: 32, description: Read data}
+    - {name: rresp,   direction: output, width: 2, description: Read response}
+
+config_parameters:
+  - {name: ADDR_WIDTH, type: int, default: 32, enum: [12, 16, 32]}
+  - {name: DATA_WIDTH, type: int, default: 32, enum: [32, 64]}
+
+register_template:
+  - name: AXI_CTRL
+    address: 0x0000
+    access: rw
+    fields:
+      - {name: enable,  bits: 0, description: Core enable}
+      - {name: irq_en,  bits: 1, description: Interrupt enable}
+  - name: AXI_STATUS
+    address: 0x0004
+    access: ro
+    fields:
+      - {name: ready,   bits: 0, description: Core ready}
+      - {name: error,   bits: 1, description: Error detected}
+
+sequence_template:
+  name: axi4lite_sequence
+  body: |
+    // AXI4-Lite read-modify-write sequence
+    drv.axi_read_reg(base_addr + offset, read_data);
+    read_data[field] = value;
+    drv.axi_write_reg(base_addr + offset, read_data);
+
+coverage_template:
+  - name: axi_cg
+    type: covergroup
+    items:
+      - {name: cg_resp, type: coverpoint, expression: {bresp, rresp}}
+      - {name: cg_addr, type: coverpoint, expression: {awaddr, araddr}}

protocols/i2c.yaml

@@ -0,0 +1,61 @@
+# I2C Protocol Definition — UVM TB Generator
+protocol: i2c
+description: Inter-Integrated Circuit
+tags: [serial, synchronous, multi-master, open-drain]
+
+interface_template:
+  signals:
+    - {name: scl, direction: inout, width: 1, description: Serial clock line}
+    - {name: sda, direction: inout, width: 1, description: Serial data line}
+
+config_parameters:
+  - {name: SLAVE_ADDR, type: int, default: 0x50, minimum: 0x00, maximum: 0x7F, description: 7-bit slave address}
+  - {name: CLK_FREQ,   type: int, default: 100000, description: I2C bus frequency (Hz)}
+  - {name: ADDR_WIDTH, type: int, default: 7, enum: [7, 10], description: Addressing mode}
+
+register_template:
+  - name: CR      # Control Register
+    address: 0x00
+    access: rw
+    fields:
+      - {name: enable,    bits: 0, description: I2C core enable}
+      - {name: irq_en,    bits: 1, description: Interrupt enable}
+      - {name: addr_mode, bits: 2, description: 0=7bit, 1=10bit}
+  - name: ADR     # Slave Address Register
+    address: 0x04
+    access: rw
+    fields:
+      - {name: addr, bits: 9:0, description: Slave address}
+  - name: DR      # Data Register
+    address: 0x08
+    access: rw
+    fields:
+      - {name: data, bits: 7:0, description: I2C data byte}
+  - name: SR      # Status Register
+    address: 0x0C
+    access: ro
+    fields:
+      - {name: busy,    bits: 0, description: Bus busy}
+      - {name: rx_ack,  bits: 1, description: Receive acknowledge}
+      - {name: tx_rdy,  bits: 2, description: TX ready}
+      - {name: rx_rdy,  bits: 3, description: RX ready}
+      - {name: arb_lost,bits: 4, description: Arbitration lost}
+      - {name: nack,    bits: 5, description: No acknowledge received}
+
+sequence_template:
+  name: i2c_sequence
+  body: |
+    // I2C write sequence
+    drv.write_reg(ADR, slave_addr);
+    drv.write_reg(CR, {1'b1, enable});
+    foreach (tx_data[i]) begin
+      drv.write_reg(DR, tx_data[i]);
+      drv.wait_for_field(SR, tx_rdy, 1);
+    end
+
+coverage_template:
+  - name: i2c_cg
+    type: covergroup
+    items:
+      - {name: cg_addr,  type: coverpoint, expression: slave_addr}
+      - {name: cg_dir,   type: coverpoint, expression: {read, write}}

protocols/spi.yaml

@@ -0,0 +1,57 @@
+# SPI Protocol Definition — UVM TB Generator
+protocol: spi
+description: Serial Peripheral Interface
+tags: [serial, synchronous, full-duplex, master-slave]
+
+interface_template:
+  signals:
+    - {name: sclk,  direction: input,  width: 1, description: Serial clock}
+    - {name: mosi,  direction: input,  width: 1, description: Master out slave in}
+    - {name: miso,  direction: output, width: 1, description: Master in slave out}
+    - {name: ss_n,  direction: input,  width: 1, description: Slave select (active-low)}
+
+config_parameters:
+  - {name: CPOL,       type: int, default: 0, enum: [0, 1],   description: Clock polarity}
+  - {name: CPHA,       type: int, default: 0, enum: [0, 1],   description: Clock phase}
+  - {name: DATA_WIDTH, type: int, default: 8, enum: [4, 8, 16, 32], description: Data width}
+  - {name: MSB_FIRST,  type: bool, default: true, description: MSB-first transfer}
+
+register_template:
+  - name: CR0     # Control Register 0
+    address: 0x00
+    access: rw
+    fields:
+      - {name: div,       bits: 7:0,  description: Clock divider}
+      - {name: cpol,      bits: 8,    description: Clock polarity}
+      - {name: cpha,      bits: 9,    description: Clock phase}
+      - {name: data_width,bits: 15:12,description: Data width minus 1}
+  - name: DR      # Data Register
+    address: 0x04
+    access: rw
+    fields:
+      - {name: data, bits: 15:0, description: SPI data}
+  - name: SR      # Status Register
+    address: 0x08
+    access: ro
+    fields:
+      - {name: busy,  bits: 0, description: Transfer in progress}
+      - {name: rxf,   bits: 1, description: RX FIFO full}
+      - {name: txe,   bits: 2, description: TX FIFO empty}
+
+sequence_template:
+  name: spi_sequence
+  body: |
+    // SPI transmit sequence
+    cr0 = {cpol, cpha, div};
+    drv.write_reg(CR0, cr0);
+    foreach (tx_data[i]) begin
+      drv.write_reg(DR, tx_data[i]);
+      drv.wait_for_field(SR, busy, 0);
+    end
+
+coverage_template:
+  - name: spi_cg
+    type: covergroup
+    items:
+      - {name: cg_mode,  type: coverpoint, expression: {cpol, cpha}}
+      - {name: cg_width, type: coverpoint, expression: data_width}

protocols/uart.yaml

@@ -0,0 +1,119 @@
+# UART Protocol Definition — UVM TB Generator
+# Reference: 16550 / NS16C550 compatible
+protocol: uart
+description: Universal Asynchronous Receiver-Transmitter
+tags: [serial, asynchronous, full-duplex]
+
+interface_template:
+  signals:
+    - {name: srx,     direction: input,  width: 1,  description: Serial receive}
+    - {name: stx,     direction: output, width: 1,  description: Serial transmit}
+    - {name: cts_n,   direction: input,  width: 1,  description: Clear to send (active-low)}
+    - {name: rts_n,   direction: output, width: 1,  description: Request to send (active-low)}
+
+baud_rates: [9600, 19200, 38400, 57600, 115200, 230400, 460800]
+
+config_parameters:
+  - {name: DATA_BITS, type: int, default: 8, enum: [5, 6, 7, 8]}
+  - {name: STOP_BITS, type: int, default: 1, enum: [1, 2]}
+  - {name: PARITY,    type: string, default: "none", enum: [none, even, odd, mark, space]}
+
+register_template:
+  - name: RBR     # Receiver Buffer Register
+    address: 0x00
+    access: ro
+    fields:
+      - {name: rbr_data, bits: 7:0, access: ro, description: Received data byte}
+  - name: THR     # Transmitter Holding Register
+    address: 0x00
+    access: wo
+    fields:
+      - {name: thr_data, bits: 7:0, access: wo, description: Transmit data byte}
+  - name: IER     # Interrupt Enable Register
+    address: 0x01
+    access: rw
+    fields:
+      - {name: erbfi, bits: 0, description: Enable RX data available interrupt}
+      - {name: etbei, bits: 1, description: Enable TX holding register empty interrupt}
+      - {name: elsi,  bits: 2, description: Enable RX line status interrupt}
+      - {name: edssi, bits: 3, description: Enable modem status interrupt}
+  - name: IIR     # Interrupt Identification Register
+    address: 0x02
+    access: ro
+    fields:
+      - {name: int_id,   bits: 3:0, description: Interrupt type identifier}
+      - {name: fifos_en, bits: 7:6, description: FIFO enable status}
+  - name: FCR     # FIFO Control Register
+    address: 0x02
+    access: wo
+    fields:
+      - {name: fifo_en,   bits: 0, description: Enable FIFOs}
+      - {name: rclr,      bits: 1, description: Clear RX FIFO}
+      - {name: tclr,      bits: 2, description: Clear TX FIFO}
+      - {name: dma_mode,  bits: 3, description: DMA mode select}
+      - {name: rx_trigger,bits: 7:6, description: RX FIFO trigger level}
+  - name: LCR     # Line Control Register
+    address: 0x03
+    access: rw
+    fields:
+      - {name: wls,  bits: 1:0, description: Word length select}
+      - {name: stb,  bits: 2,   description: Stop bits}
+      - {name: pen,  bits: 3,   description: Parity enable}
+      - {name: eps,  bits: 4,   description: Even parity select}
+      - {name: sp,   bits: 5,   description: Stick parity}
+      - {name: bc,   bits: 6,   description: Break control}
+      - {name: dlab, bits: 7,   description: Divisor latch access bit}
+  - name: MCR     # Modem Control Register
+    address: 0x04
+    access: rw
+    fields:
+      - {name: dtr,  bits: 0, description: Data Terminal Ready}
+      - {name: rts,  bits: 1, description: Request To Send}
+      - {name: out1, bits: 2, description: Output 1}
+      - {name: out2, bits: 3, description: Output 2}
+      - {name: loop, bits: 4, description: Loopback mode enable}
+  - name: LSR     # Line Status Register
+    address: 0x05
+    access: ro
+    fields:
+      - {name: dr,   bits: 0, description: Data Ready}
+      - {name: oe,   bits: 1, description: Overrun Error}
+      - {name: pe,   bits: 2, description: Parity Error}
+      - {name: fe,   bits: 3, description: Framing Error}
+      - {name: bi,   bits: 4, description: Break Interrupt}
+      - {name: thre, bits: 5, description: TX Holding Register Empty}
+      - {name: temt, bits: 6, description: Transmitter Empty}
+      - {name: err,  bits: 7, description: Error in RX FIFO}
+  - name: MSR     # Modem Status Register
+    address: 0x06
+    access: ro
+    fields:
+      - {name: dcts, bits: 0, description: Delta Clear To Send}
+      - {name: ddsr, bits: 1, description: Delta Data Set Ready}
+      - {name: teri, bits: 2, description: Trailing Edge Ring Indicator}
+      - {name: ddcd, bits: 3, description: Delta Data Carrier Detect}
+      - {name: cts,  bits: 4, description: Clear To Send}
+      - {name: dsr,  bits: 5, description: Data Set Ready}
+      - {name: ri,   bits: 6, description: Ring Indicator}
+      - {name: dcd,  bits: 7, description: Data Carrier Detect}
+  - name: SCR     # Scratch Register
+    address: 0x07
+    access: rw
+    fields:
+      - {name: scratch, bits: 7:0, description: Scratch value}
+
+sequence_template:
+  name: uart_sequence
+  body: |
+    // UART transmit sequence
+    repeat (num_bytes) begin
+      drv.write_reg(THR, data_q.pop_front());
+      drv.wait_for_field(LSR, thre, 1);
+    end
+
+coverage_template:
+  - name: uart_cg
+    type: covergroup
+    items:
+      - {name: cg_baud,   type: coverpoint, expression: baud_rate, bins: [9600, 19200, 115200]}
+      - {name: cg_frame,  type: coverpoint, expression: {data_bits, stop_bits, parity}}

protocols/wishbone.yaml

@@ -0,0 +1,48 @@
+# Wishbone Protocol Definition — UVM TB Generator
+protocol: wishbone
+description: Wishbone B4 bus interface
+tags: [bus, memory-mapped, synchronous, pipelined]
+
+interface_template:
+  signals:
+    - {name: cyc,  direction: input,  width: 1, description: Cycle start}
+    - {name: stb,  direction: input,  width: 1, description: Strobe}
+    - {name: we,   direction: input,  width: 1, description: Write enable}
+    - {name: adr,  direction: input,  width: 32, description: Address bus}
+    - {name: dat_i,direction: input,  width: 32, description: Write data}
+    - {name: dat_o,direction: output, width: 32, description: Read data}
+    - {name: ack,  direction: output, width: 1, description: Acknowledge}
+    - {name: err,  direction: output, width: 1, description: Error}
+    - {name: rty,  direction: output, width: 1, description: Retry}
+
+config_parameters:
+  - {name: ADDR_WIDTH, type: int, default: 32}
+  - {name: DATA_WIDTH, type: int, default: 32, enum: [8, 16, 32, 64]}
+  - {name: GRANULARITY,type: string, default: "byte", enum: [byte, word]}
+
+register_template:
+  - name: WB_CTRL
+    address: 0x00
+    access: rw
+    fields:
+      - {name: enable, bits: 0, description: Core enable}
+  - name: WB_STATUS
+    address: 0x04
+    access: ro
+    fields:
+      - {name: ready, bits: 0, description: Core ready}
+
+sequence_template:
+  name: wishbone_sequence
+  body: |
+    // Wishbone classic write sequence
+    adr = addr; dat_i = data; we = 1;
+    cyc = 1; stb = 1;
+    wait(ack);
+    cyc = 0; stb = 0;
+
+coverage_template:
+  - name: wb_cg
+    type: covergroup
+    items:
+      - {name: cg_op, type: coverpoint, expression: we}

pyproject.toml

@@ -0,0 +1,61 @@
+[build-system]
+requires = ["setuptools>=68.0", "wheel"]
+build-backend = "setuptools.backends._legacy:_Backend"
+
+[project]
+name = "uvm-tb-generator"
+version = "0.3.0"
+description = "Industry-grade UVM Testbench Generator with protocol libraries, schema validation, and CI/CD"
+readme = "README.md"
+license = {text = "MIT"}
+requires-python = ">=3.10"
+authors = [
+    {name = "DV Automation Team"},
+]
+keywords = ["uvm", "testbench", "verification", "systemverilog", "eda", "automation"]
+classifiers = [
+    "Development Status :: 4 - Beta",
+    "Intended Audience :: Developers",
+    "License :: OSI Approved :: MIT License",
+    "Programming Language :: Python :: 3",
+    "Programming Language :: Python :: 3.10",
+    "Programming Language :: Python :: 3.11",
+    "Programming Language :: Python :: 3.12",
+    "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+]
+dependencies = [
+    "pyyaml>=6.0",
+    "jinja2>=3.0",
+    "pydantic>=2.0",
+]
+
+[project.optional-dependencies]
+dev = [
+    "pytest>=7.0",
+    "pytest-cov>=4.0",
+    "flake8>=7.0",
+    "black>=24.0",
+    "yamllint>=1.35",
+    "jsonschema>=4.0",
+    "build>=1.0",
+]
+mlflow = ["mlflow>=2.0"]
+
+[project.urls]
+Repository = "https://github.com/your-org/uvm-tb-generator"
+Documentation = "https://github.com/your-org/uvm-tb-generator/docs"
+
+[project.scripts]
+uvmgen = "src.main:main"
+
+[tool.pytest.ini_options]
+testpaths = ["tests"]
+addopts = "-v --tb=short"
+
+[tool.coverage.run]
+source = ["src"]
+omit = ["*/tests/*"]
+
+[tool.flake8]
+max-line-length = 120
+extend-ignore = ["E203", "W503"]

render.yaml

@@ -0,0 +1,30 @@
+# Render.com deployment — free tier, single service
+# Steps:
+#   1. Push repo to GitHub
+#   2. Go to https://dashboard.render.com/select-repo
+#   3. Connect this repo — Render auto-reads this file
+#   4. Deploy (zero config)
+
+services:
+  - type: web
+    name: uvm-tb-generator
+    runtime: python
+    region: oregon
+    plan: free
+    buildCommand: |
+      pip install -r requirements.txt
+      cd frontend && npm ci && npm run build && cd ..
+    startCommand: gunicorn src.api.server:app --worker-class uvicorn.workers.UvicornWorker --bind 0.0.0.0:$PORT --workers 1 --timeout 120
+    envVars:
+      - key: PYTHONUNBUFFERED
+        value: "1"
+      - key: LOG_LEVEL
+        value: info
+      - key: UVMGEN_OUTPUT_DIR
+        value: /var/data/uvmgen_output
+    healthCheckPath: /api/health
+    autoDeploy: true
+    disk:
+      name: uvmgen-data
+      mountPath: /var/data
+      sizeGB: 1

requirements-dev.txt

@@ -0,0 +1,2 @@
+pytest>=7.0
+pytest-cov>=4.0

requirements.txt

@@ -0,0 +1,6 @@
+pyyaml>=6.0
+jinja2>=3.0
+pydantic>=2.0
+fastapi>=0.115.0
+uvicorn[standard]>=0.34.0
+gunicorn>=23.0

setup.cfg

@@ -0,0 +1,25 @@
+[metadata]
+name = uvm-tb-generator
+version = 0.2.0
+description = ML-style UVM Testbench Generator
+author = DV Automation Team
+license = MIT
+
+[options]
+packages = find:
+python_requires = >=3.10
+install_requires =
+    pyyaml>=6.0
+    jinja2>=3.0
+    pydantic>=2.0
+
+[options.extras_require]
+dev =
+    pytest>=7.0
+    pytest-cov>=4.0
+mlflow =
+    mlflow>=2.0
+
+[options.entry_points]
+console_scripts =
+    uvmgen = src.main:main

src/api/server.py

@@ -0,0 +1,260 @@
+"""
+FastAPI backend for UVM TB Generator.
+Serves both the REST API and the React frontend from a single process
+for free-tier deployment (Render, Fly.io, PythonAnywhere).
+"""
+
+from __future__ import annotations
+
+import logging
+import os
+import traceback
+from contextlib import asynccontextmanager
+from pathlib import Path
+from typing import List, Optional
+
+from fastapi import FastAPI, HTTPException
+from fastapi.middleware.cors import CORSMiddleware
+from fastapi.responses import FileResponse, HTMLResponse, JSONResponse
+from pydantic import BaseModel, Field
+
+from src.config import ConfigLoader
+from src.exceptions import UVMGenError
+from src.pipeline import TBPipeline
+
+logger = logging.getLogger("uvmgen")
+logger.setLevel(logging.INFO)
+
+# ── Find frontend build directory ─────────────────────────────────
+HERE = Path(__file__).resolve().parent
+PROJECT_ROOT = HERE.parent.parent
+FRONTEND_BUILD = PROJECT_ROOT / "frontend" / "build"
+
+# ── Request / Response models ─────────────────────────────────────
+
+class PipelineRequest(BaseModel):
+    spec_yaml: str = Field(..., description="YAML or .core specification content")
+    design_name: str = Field(default="unnamed")
+    auto_train: bool = Field(default=False)
+    max_iterations: int = Field(default=5, ge=1, le=50)
+    coverage_target: float = Field(default=90.0, ge=0, le=100)
+    num_seeds: int = Field(default=3, ge=1, le=20)
+    overwrite: bool = Field(default=False)
+
+
+class HealthResponse(BaseModel):
+    status: str = "ok"
+    version: str = "0.3.0"
+    api_version: str = "v1"
+    simulators: List[str] = ["stub", "icarus"]
+
+
+class VersionInfo(BaseModel):
+    version: str
+    coverage: float
+    files: int
+    iteration: int
+
+
+class PipelineResponse(BaseModel):
+    design_name: str
+    status: str
+    versions: List[VersionInfo]
+    coverage_trend: list
+    coverage_gaps: list
+    artifacts: list
+    total_files: int
+    iterations: int
+    simulator: str
+
+
+# ── Pipeline singleton ─────────────────────────────────────────────
+
+pipeline_instance: Optional[TBPipeline] = None
+
+
+@asynccontextmanager
+async def lifespan(app: FastAPI):
+    global pipeline_instance
+    logger.info("UVM TB Generator starting...")
+    pipeline_instance = TBPipeline()
+    yield
+    logger.info("UVM TB Generator shutting down...")
+
+
+app = FastAPI(title="UVM TB Generator", version="0.3.0", lifespan=lifespan)
+
+app.add_middleware(
+    CORSMiddleware,
+    allow_origins=["*"],
+    allow_credentials=True,
+    allow_methods=["*"],
+    allow_headers=["*"],
+)
+
+
+# ── Exception handlers ─────────────────────────────────────────────
+
+@app.exception_handler(UVMGenError)
+async def uvmgen_error_handler(request, exc: UVMGenError):
+    return JSONResponse(status_code=exc.status_code, content=exc.to_dict())
+
+
+@app.exception_handler(Exception)
+async def generic_error_handler(request, exc: Exception):
+    logger.error("Unhandled: %s\n%s", exc, traceback.format_exc())
+    return JSONResponse(
+        status_code=500,
+        content={"error": "INTERNAL_ERROR", "message": str(exc)},
+    )
+
+
+# ── API Routes ─────────────────────────────────────────────────────
+
+@app.get("/api/health", response_model=HealthResponse)
+async def health_check():
+    return HealthResponse()
+
+
+@app.get("/api/versions")
+async def list_versions():
+    if not pipeline_instance:
+        raise HTTPException(503, "Pipeline not initialized")
+    trend = pipeline_instance.registry.coverage_trend()
+    return {"versions": trend}
+
+
+@app.post("/api/run-pipeline", response_model=PipelineResponse)
+async def run_pipeline(req: PipelineRequest):
+    global pipeline_instance
+    if not pipeline_instance:
+        pipeline_instance = TBPipeline()
+
+    try:
+        import tempfile, os as _os
+        with tempfile.NamedTemporaryFile(mode="w", suffix=".yaml", delete=False, encoding="utf-8") as f:
+            f.write(req.spec_yaml)
+            spec_path = f.name
+
+        pipeline_instance.cfg.auto_train.enabled = req.auto_train
+        pipeline_instance.cfg.auto_train.max_iterations = req.max_iterations
+        pipeline_instance.cfg.auto_train.coverage_target = req.coverage_target
+        pipeline_instance.cfg.auto_train.num_seeds = req.num_seeds
+        pipeline_instance.cfg.generation.overwrite = req.overwrite
+
+        result = pipeline_instance.run(spec_path)
+
+        try:
+            _os.unlink(spec_path)
+        except OSError:
+            pass
+
+        analysis = result.get("coverage_analysis") or {}
+        gaps = [{"bin": g["bin"], "addr": g.get("addr"), "dir": g.get("dir")}
+                for g in (analysis.get("gaps") or [])]
+
+        versions = []
+        for t in (result.get("coverage_trend") or []):
+            if isinstance(t, dict):
+                versions.append(VersionInfo(
+                    version=t.get("version", "v0"),
+                    coverage=float(t.get("coverage", 0)),
+                    files=t.get("files", 0),
+                    iteration=t.get("iteration", 0),
+                ))
+
+        artifacts = [
+            {"name": Path(p).name, "path": p}
+            for p in result.get("generated_files", {}).values()
+        ]
+
+        return PipelineResponse(
+            design_name=result.get("design_name", "unknown"),
+            status="passed" if result.get("passed") else "failed",
+            versions=versions,
+            coverage_trend=result.get("coverage_trend") or [],
+            coverage_gaps=gaps,
+            artifacts=artifacts,
+            total_files=len(artifacts),
+            iterations=result.get("auto_train_iterations", 0),
+            simulator=result.get("simulator", "stub"),
+        )
+    except UVMGenError:
+        raise
+    except Exception as e:
+        logger.error("Pipeline failed: %s", e)
+        raise HTTPException(500, detail=str(e))
+
+
+@app.post("/api/validate-spec")
+async def validate_spec(req: PipelineRequest):
+    try:
+        import tempfile, os as _os, yaml
+        with tempfile.NamedTemporaryFile(mode="w", suffix=".yaml", delete=False, encoding="utf-8") as f:
+            f.write(req.spec_yaml)
+            spec_path = f.name
+
+        loader = ConfigLoader()
+        spec, _ = loader.load(spec_path)
+        from src.data.validators import SpecValidator
+        validator = SpecValidator()
+        vr = validator.validate(spec, strict=True)
+        try:
+            _os.unlink(spec_path)
+        except OSError:
+            pass
+        return {"valid": bool(vr), "design_name": spec.design_name,
+                "errors": vr if vr else [], "registers": len(spec.registers),
+                "interfaces": len(spec.interfaces)}
+    except Exception as e:
+        raise HTTPException(422, detail=str(e))
+
+
+# ── Serve frontend (single deploy) ─────────────────────────────────
+
+_IS_BUILT = FRONTEND_BUILD.exists()
+if _IS_BUILT:
+    logger.info("Serving frontend from %s", FRONTEND_BUILD)
+
+from fastapi.responses import HTMLResponse
+
+
+@app.get("/", include_in_schema=False)
+@app.get("/index.html", include_in_schema=False)
+async def serve_index():
+    if _IS_BUILT:
+        index = FRONTEND_BUILD / "index.html"
+        if index.exists():
+            return FileResponse(str(index))
+    return HTMLResponse("<h1>UVM TB Generator API</h1><p>Frontend not built. Run <code>cd frontend && npm run build</code></p>")
+
+
+@app.get("/static/{rest_of_path:path}", include_in_schema=False)
+async def serve_static(rest_of_path: str):
+    if not _IS_BUILT:
+        return JSONResponse(404, {"error": "Not found"})
+    file_path = FRONTEND_BUILD / "static" / rest_of_path
+    if file_path.exists() and file_path.is_file():
+        return FileResponse(str(file_path))
+    return JSONResponse(404, {"error": "Not found"})
+
+
+@app.get("/{full_path:path}", include_in_schema=False)
+async def serve_spa(full_path: str):
+    if full_path.startswith("api/") or full_path.startswith("docs") or full_path.startswith("openapi"):
+        return JSONResponse(status_code=404, content={"error": "Not found"})
+    if _IS_BUILT:
+        file_path = FRONTEND_BUILD / full_path
+        if file_path.exists() and file_path.is_file():
+            return FileResponse(str(file_path))
+        index = FRONTEND_BUILD / "index.html"
+        if index.exists():
+            return FileResponse(str(index))
+    return JSONResponse(404, {"error": "Not found"})
+
+
+# ── Direct execution ───────────────────────────────────────────────
+
+if __name__ == "__main__":
+    import uvicorn
+    uvicorn.run("src.api.server:app", host="0.0.0.0", port=8000, reload=True)

src/config.py

@@ -0,0 +1,175 @@
+# src/config.py — Central configuration with Pydantic validation
+
+from __future__ import annotations
+
+import os
+from pathlib import Path
+from typing import Dict, List, Optional, Any
+
+from pydantic import BaseModel, Field
+import yaml
+
+
+# ── Data Models ──────────────────────────────────────────────────────────────
+
+class SignalDef(BaseModel):
+    name: str
+    direction: str = Field(pattern=r"^(input|output|inout)$")
+    width: Optional[int] = 1
+
+class InterfaceDef(BaseModel):
+    name: str
+    signals: List[SignalDef] = Field(min_length=1)
+
+class FieldDef(BaseModel):
+    name: str
+    bits: str
+    description: Optional[str] = None
+
+class RegisterDef(BaseModel):
+    name: str
+    address: str
+    fields: List[FieldDef] = []
+    description: Optional[str] = None
+    access: Optional[str] = None
+    size: Optional[int] = None
+    reset_value: Optional[str] = None
+    volatile: bool = False
+
+class ClockResetDef(BaseModel):
+    clock: str = "clk"
+    reset: str = "rst_n"
+    reset_active: int = Field(default=0, ge=0, le=1)
+
+class DesignSpec(BaseModel):
+    design_name: str = Field(min_length=1, pattern=r"^[a-zA-Z_][a-zA-Z0-9_]*$")
+    clock_reset: ClockResetDef = ClockResetDef()
+    interfaces: List[InterfaceDef] = Field(min_length=1)
+    registers: List[RegisterDef] = []
+    protocol: str = Field(default="", pattern=r"^(uart|spi|i2c|axi4lite|apb|wishbone|)$")
+
+
+# ── Pipeline / Engine Config ─────────────────────────────────────────────────
+
+class LoggingConfig(BaseModel):
+    level: str = Field(default="INFO", pattern=r"^(DEBUG|INFO|WARNING|ERROR)$")
+    file: Optional[str] = None
+    format: str = "%(asctime)s | %(levelname)-8s | %(name)s | %(message)s"
+
+class EvaluationConfig(BaseModel):
+    enabled: bool = True
+    metrics: List[str] = ["completeness", "syntax_validity", "coverage_readiness"]
+    threshold: float = Field(default=0.7, ge=0.0, le=1.0)
+
+class TrackingConfig(BaseModel):
+    enabled: bool = False
+    backend: str = Field(default="local", pattern=r"^(local|mlflow)$")
+    experiment_name: Optional[str] = None
+    tracking_uri: Optional[str] = None
+
+class GenerationConfig(BaseModel):
+    templates_dir: str = "src/generation/templates"
+    output_dir: str = "output"
+    overwrite: bool = False
+    strict_validation: bool = True
+    iteration: int = Field(default=0, ge=0)
+
+class AutoTrainConfig(BaseModel):
+    enabled: bool = False
+    max_iterations: int = Field(default=5, ge=1, le=50)
+    coverage_target: float = Field(default=90.0, ge=0.0, le=100.0)
+    coverage_gain_min: float = Field(default=2.0, ge=0.0, description="Min % gain per iteration to continue")
+    simulator: str = Field(default="stub", pattern=r"^(stub|icarus|vcs|questa)$")
+    sim_timeout: int = Field(default=300, ge=10)
+    num_seeds: int = Field(default=3, ge=1, le=20, description="Number of regression seeds per iteration")
+    generate_regression_test: bool = True
+
+class PipelineConfig(BaseModel):
+    generation: GenerationConfig = GenerationConfig()
+    evaluation: EvaluationConfig = EvaluationConfig()
+    tracking: TrackingConfig = TrackingConfig()
+    logging: LoggingConfig = LoggingConfig()
+    auto_train: AutoTrainConfig = AutoTrainConfig()
+
+
+# ── Config Loader ────────────────────────────────────────────────────────────
+
+class ConfigLoader:
+    """Hierarchical config loader with env override support.
+
+    Load order (later overrides earlier):
+        1. Base defaults
+        2. <env>.yaml (e.g. configs/production.yaml)
+        3. Environment variables (UVMGEN_* prefix)
+    """
+
+    ENV_PREFIX = "UVMGEN_"
+
+    def __init__(self, root: Optional[str] = None):
+        self.root = Path(root or os.getcwd())
+
+    def load(self, spec_path: str, pipeline_path: Optional[str] = None) -> tuple[DesignSpec, PipelineConfig]:
+        design_spec = self._load_design_spec(spec_path)
+        pipeline_cfg = self._load_pipeline(pipeline_path)
+        self._apply_env_overrides(pipeline_cfg)
+        return design_spec, pipeline_cfg
+
+    def _load_design_spec(self, path: str) -> DesignSpec:
+        from src.data.preprocessor import SpecPreprocessor
+        from src.data.core_parser import CoreParser
+
+        ext = Path(path).suffix.lower()
+        if ext == ".core":
+            raw = CoreParser().parse(Path(path).read_text(encoding="utf-8"))
+        else:
+            raw = self._read_yaml(path)
+            raw = SpecPreprocessor().preprocess(raw)
+        return DesignSpec(**raw)
+
+    def _load_pipeline(self, path: Optional[str] = None) -> PipelineConfig:
+        base = PipelineConfig()
+        if path and Path(path).exists():
+            overrides = self._read_yaml(path)
+            base = self._deep_merge(base, overrides)
+        return base
+
+    def _apply_env_overrides(self, cfg: PipelineConfig) -> None:
+        prefix = self.ENV_PREFIX
+        for key, val in os.environ.items():
+            if key.startswith(prefix):
+                parts = key[len(prefix):].lower().split("__")
+                target = cfg
+                for part in parts[:-1]:
+                    target = getattr(target, part, None)
+                    if target is None:
+                        break
+                else:
+                    last = parts[-1]
+                    if hasattr(target, last):
+                        setattr(target, last, self._coerce(val, type(getattr(target, last))))
+
+    @staticmethod
+    def _read_yaml(path: str) -> dict:
+        with open(path, "r") as f:
+            return yaml.safe_load(f)
+
+    @staticmethod
+    def _coerce(val: str, typ: type) -> Any:
+        if typ is bool:
+            return val.lower() in ("1", "true", "yes")
+        if typ is int:
+            return int(val)
+        if typ is float:
+            return float(val)
+        return val
+
+    @staticmethod
+    def _deep_merge(base: PipelineConfig, overrides: dict) -> PipelineConfig:
+        import json
+        base_dict = json.loads(base.model_dump_json())
+        for k, v in overrides.items():
+            if k in base_dict and isinstance(base_dict[k], dict) and isinstance(v, dict):
+                base_dict[k].update(v)
+            else:
+                base_dict[k] = v
+        return PipelineConfig(**base_dict)

src/data/collector.py

@@ -0,0 +1,40 @@
+# src/data/collector.py — Collect specs from multiple sources (YAML, JSON, DB)
+
+from __future__ import annotations
+
+import json
+from pathlib import Path
+from typing import Dict, List, Optional, Any
+
+import yaml
+
+
+class SpecCollector:
+    """Collects raw design specifications from various sources."""
+
+    SUPPORTED_EXTENSIONS = {".yaml", ".yml", ".json"}
+
+    def __init__(self, source_paths: Optional[List[str]] = None):
+        self.source_paths = source_paths or []
+
+    def collect(self) -> List[Dict[str, Any]]:
+        specs: List[Dict[str, Any]] = []
+        for path in self.source_paths:
+            p = Path(path)
+            if p.is_file() and p.suffix in self.SUPPORTED_EXTENSIONS:
+                specs.append(self._read_file(p))
+            elif p.is_dir():
+                for f in sorted(p.glob("*.*")):
+                    if f.suffix in self.SUPPORTED_EXTENSIONS:
+                        specs.append(self._read_file(f))
+        return specs
+
+    def collect_from_database(self, connection_string: str, query: str) -> List[Dict[str, Any]]:
+        raise NotImplementedError("Database collector — implement for your ORM / DB backend")
+
+    @staticmethod
+    def _read_file(path: Path) -> Dict[str, Any]:
+        with open(path, "r") as f:
+            if path.suffix in (".yaml", ".yml"):
+                return yaml.safe_load(f)
+            return json.load(f)

src/data/core_parser.py

@@ -0,0 +1,117 @@
+# src/data/core_parser.py — FuseSoC .core file parser
+
+from __future__ import annotations
+
+from typing import Any, Dict, List, Optional
+
+import yaml
+
+from src.data.preprocessor import SpecPreprocessor
+
+
+class CoreParser:
+    """Parses FuseSoC .core files into the internal DesignSpec-compatible dict.
+
+    The .core format (YAML) describes IP cores with:
+      - name / version / description
+      - parameters
+      - interfaces (each with signals, type, bus standard)
+      - registers (address, access, fields with bit positions)
+      - clock_reset
+      - filesets, targets
+    """
+
+    ACCESS_MAP = {
+        "ro": "read-only",
+        "wo": "write-only",
+        "rw": "read-write",
+        "rc": "read-clear",
+        "rs": "read-set",
+        "w1c": "write-1-to-clear",
+    }
+
+    def parse(self, content: str) -> Dict[str, Any]:
+        raw = yaml.safe_load(content)
+        spec: Dict[str, Any] = {}
+
+        spec["design_name"] = self._extract_name(raw)
+        spec["clock_reset"] = self._extract_clock_reset(raw)
+        spec["interfaces"] = self._extract_interfaces(raw)
+        spec["registers"] = self._extract_registers(raw)
+        spec["parameters"] = self._extract_parameters(raw)
+
+        return SpecPreprocessor().preprocess(spec)
+
+    @staticmethod
+    def _extract_name(raw: Dict[str, Any]) -> str:
+        name = raw.get("name", "unknown")
+        if isinstance(name, str):
+            return name.strip().lower()
+        return "unknown"
+
+    @staticmethod
+    def _extract_clock_reset(raw: Dict[str, Any]) -> Dict[str, Any]:
+        cr = raw.get("clock_reset")
+        if cr:
+            return {
+                "clock": cr.get("clock", "clk"),
+                "reset": cr.get("reset", "rst_n"),
+                "reset_active": cr.get("reset_active", 0),
+            }
+        return {"clock": "clk", "reset": "rst_n", "reset_active": 0}
+
+    @staticmethod
+    def _extract_interfaces(raw: Dict[str, Any]) -> List[Dict[str, Any]]:
+        interfaces = raw.get("interfaces", [])
+        result: List[Dict[str, Any]] = []
+        for iface in interfaces:
+            entry: Dict[str, Any] = {
+                "name": iface.get("name", "bus"),
+                "signals": [],
+            }
+            for sig in iface.get("signals", []):
+                entry["signals"].append({
+                    "name": sig.get("name", "sig"),
+                    "direction": sig.get("direction", "input"),
+                    "width": sig.get("width", 1),
+                })
+            result.append(entry)
+        return result
+
+    @staticmethod
+    def _extract_registers(raw: Dict[str, Any]) -> List[Dict[str, Any]]:
+        registers = raw.get("registers", [])
+        result: List[Dict[str, Any]] = []
+        seen = set()
+        for reg in registers:
+            name = reg.get("name", f"reg_{len(result)}")
+            if name in seen:
+                name = f"{name}_{len(result)}"
+            seen.add(name)
+
+            entry: Dict[str, Any] = {
+                "name": name,
+                "address": reg.get("address", "0x00"),
+                "description": reg.get("description", ""),
+                "access": reg.get("access", "rw"),
+                "fields": [],
+            }
+            for fld in reg.get("fields", []):
+                entry["fields"].append({
+                    "name": fld.get("name", "field"),
+                    "bits": fld.get("bits", "0"),
+                    "description": fld.get("description", ""),
+                })
+            result.append(entry)
+        return result
+
+    @staticmethod
+    def _extract_parameters(raw: Dict[str, Any]) -> Dict[str, Any]:
+        params = raw.get("parameters", {})
+        return {k: v.get("default") if isinstance(v, dict) else v for k, v in params.items()}
+
+
+def parse_core_file(path: str) -> Dict[str, Any]:
+    """Convenience: read .core file and return DesignSpec-compatible dict."""
+    with open(path, "r") as f:
+        return CoreParser().parse(f.read())

src/data/preprocessor.py

@@ -0,0 +1,81 @@
+from __future__ import annotations
+
+import re
+from typing import Any, Dict, List, Optional
+
+
+PROTOCOL_SIGNATURES = {
+    "uart": {"tx", "rx", "baud"},
+    "spi": {"mosi", "miso", "sclk", "ss_n", "cs"},
+    "i2c": {"scl", "sda"},
+    "axi4lite": {"awvalid", "awready", "arvalid", "arready",
+                  "wvalid", "wready", "rvalid", "rready",
+                  "bvalid", "bready"},
+    "apb": {"psel", "penable", "paddr", "pwrite", "pready"},
+    "wishbone": {"wb_cyc", "wb_stb", "wb_we", "wb_ack", "wb_addr"},
+}
+
+
+class SpecPreprocessor:
+    def preprocess(self, raw: Dict[str, Any]) -> Dict[str, Any]:
+        raw = self._normalise_names(raw)
+        raw = self._default_clock_reset(raw)
+        raw = self._expand_signals(raw)
+        raw = self._validate_address_formats(raw)
+        raw = self._detect_protocol(raw)
+        return raw
+
+    @staticmethod
+    def _normalise_names(raw: Dict[str, Any]) -> Dict[str, Any]:
+        if "design_name" in raw:
+            raw["design_name"] = re.sub(r"[^a-zA-Z0-9_]", "_", raw["design_name"]).lower()
+        return raw
+
+    @staticmethod
+    def _default_clock_reset(raw: Dict[str, Any]) -> Dict[str, Any]:
+        raw.setdefault("clock_reset", {"clock": "clk", "reset": "rst_n", "reset_active": 0})
+        return raw
+
+    @staticmethod
+    def _expand_signals(raw: Dict[str, Any]) -> Dict[str, Any]:
+        for iface in raw.get("interfaces", []):
+            for sig in iface.get("signals", []):
+                sig.setdefault("width", 1)
+        return raw
+
+    @staticmethod
+    def _validate_address_formats(raw: Dict[str, Any]) -> Dict[str, Any]:
+        for reg in raw.get("registers", []):
+            addr = reg.get("address", "0x00")
+            if not isinstance(addr, str) or not addr.startswith("0x"):
+                reg["address"] = f"0x{int(addr):02X}" if isinstance(addr, int) else f"0x{addr}"
+            for field in reg.get("fields", []):
+                bits = field.get("bits")
+                if bits is not None and not isinstance(bits, str):
+                    field["bits"] = str(bits)
+        return raw
+
+    @staticmethod
+    def _detect_protocol(raw: Dict[str, Any]) -> Dict[str, Any]:
+        signal_names = set()
+        for iface in raw.get("interfaces", []):
+            for sig in iface.get("signals", []):
+                signal_names.add(sig.get("name", "").lower())
+
+        if raw.get("protocol"):
+            return raw
+
+        detected = None
+        rank = 0
+        for proto, sigs in PROTOCOL_SIGNATURES.items():
+            matches = sum(1 for kw in sigs if any(kw in s for s in signal_names))
+            if matches > rank:
+                rank = matches
+                detected = proto
+
+        if detected and rank >= 2:
+            raw["protocol"] = detected
+        elif not raw.get("protocol"):
+            raw["protocol"] = "wishbone"
+
+        return raw