Spaces:
Sleeping
Sleeping
Sai Kumar Taraka commited on
Commit ·
3452708
1
Parent(s): 06c49cc
Fix Pydantic validation: coerce int→str for reset/reset_value, str→int for width
Browse files- src/config.py +26 -7
src/config.py
CHANGED
|
@@ -14,16 +14,23 @@ import yaml
|
|
| 14 |
|
| 15 |
class SignalDef(BaseModel):
|
| 16 |
name: str
|
| 17 |
-
direction: str = Field(pattern=r"^(input|output|inout)$")
|
| 18 |
-
width:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 19 |
|
| 20 |
class InterfaceDef(BaseModel):
|
| 21 |
-
name: str
|
| 22 |
signals: List[SignalDef] = Field(min_length=1)
|
| 23 |
-
|
| 24 |
-
class FieldDef(BaseModel):
|
| 25 |
-
name: str
|
| 26 |
-
bits: str
|
| 27 |
description: Optional[str] = None
|
| 28 |
access: Optional[str] = None
|
| 29 |
reset: Optional[str] = None
|
|
@@ -35,6 +42,9 @@ class FieldDef(BaseModel):
|
|
| 35 |
if "width" in data and "bits" not in data:
|
| 36 |
w = data.pop("width")
|
| 37 |
data["bits"] = str(w) if isinstance(w, int) else w
|
|
|
|
|
|
|
|
|
|
| 38 |
return data
|
| 39 |
|
| 40 |
class RegisterDef(BaseModel):
|
|
@@ -47,6 +57,15 @@ class RegisterDef(BaseModel):
|
|
| 47 |
reset_value: Optional[str] = None
|
| 48 |
volatile: bool = False
|
| 49 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 50 |
class ClockResetDef(BaseModel):
|
| 51 |
clock: str = "clk"
|
| 52 |
reset: str = "rst_n"
|
|
|
|
| 14 |
|
| 15 |
class SignalDef(BaseModel):
|
| 16 |
name: str
|
| 17 |
+
direction: str = Field(default="inout", pattern=r"^(input|output|inout)$")
|
| 18 |
+
width: int = Field(default=1, ge=1)
|
| 19 |
+
description: Optional[str] = None
|
| 20 |
+
|
| 21 |
+
@model_validator(mode="before")
|
| 22 |
+
@classmethod
|
| 23 |
+
def coerce_width(cls, data):
|
| 24 |
+
if isinstance(data, dict) and "width" in data and isinstance(data["width"], str):
|
| 25 |
+
try:
|
| 26 |
+
data["width"] = int(data["width"])
|
| 27 |
+
except ValueError:
|
| 28 |
+
pass
|
| 29 |
+
return data
|
| 30 |
|
| 31 |
class InterfaceDef(BaseModel):
|
| 32 |
+
name: str = "bus"
|
| 33 |
signals: List[SignalDef] = Field(min_length=1)
|
|
|
|
|
|
|
|
|
|
|
|
|
| 34 |
description: Optional[str] = None
|
| 35 |
access: Optional[str] = None
|
| 36 |
reset: Optional[str] = None
|
|
|
|
| 42 |
if "width" in data and "bits" not in data:
|
| 43 |
w = data.pop("width")
|
| 44 |
data["bits"] = str(w) if isinstance(w, int) else w
|
| 45 |
+
if "reset" in data and isinstance(data["reset"], (int, float)):
|
| 46 |
+
val = int(data["reset"])
|
| 47 |
+
data["reset"] = str(val) if val == 0 else f"'h{val:X}" if val > 9 else str(val)
|
| 48 |
return data
|
| 49 |
|
| 50 |
class RegisterDef(BaseModel):
|
|
|
|
| 57 |
reset_value: Optional[str] = None
|
| 58 |
volatile: bool = False
|
| 59 |
|
| 60 |
+
@model_validator(mode="before")
|
| 61 |
+
@classmethod
|
| 62 |
+
def coerce_types(cls, data):
|
| 63 |
+
if isinstance(data, dict):
|
| 64 |
+
if "reset_value" in data and isinstance(data["reset_value"], (int, float)):
|
| 65 |
+
val = int(data["reset_value"])
|
| 66 |
+
data["reset_value"] = str(val) if val == 0 else f"'h{val:X}" if val > 9 else str(val)
|
| 67 |
+
return data
|
| 68 |
+
|
| 69 |
class ClockResetDef(BaseModel):
|
| 70 |
clock: str = "clk"
|
| 71 |
reset: str = "rst_n"
|