vkenbeek/verilog-wavedrom
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Nellyw888/RTL-Coder_small
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Nellyw888/RTL-Coder_7b_reasoning
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Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb
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Nellyw888/VeriReason-RTL-Coder_7b_reasoning_tb_simple
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AbiralArch/hardware-cvdp-problems
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AbiralArch/verilog-training-data
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AbiralArch/autovcoder-datasets
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AbiralArch/hardware-cvdp-examples
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AbiralArch/hardware-verilogeval-v2
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AbiralArch/hardware-shailja-vgen
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AbiralArch/hardware-cvdp-complete
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sungyub/codev-r1-verl
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Arrakark/scalared_guidelines
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HPAI-BSC/NotSoTiny-25-12
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Ani-DNN/Verify-Verilog
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NOKHAB-Lab/LLM_4_Verilog
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weiber2002/ICRTL
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HPAI-BSC/NotSoTiny-25-12-CVDP
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xxrjun/rtllm-variants
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mcc311/haven-hdl-benchmark
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architect-ubc-capstone/rtl-augmented
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architect-ubc-capstone/rtl-augmented-v2
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architect-ubc-capstone/rtl-augmented-v3
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VN-26/rtl-llm-dataset
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Adel9st/Verilog-Turkish-Dataset
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muratkarahan/verilogeval-v1-qwen-base-results
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muratkarahan/verilogeval-v1-codev-qwen-v2-results
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muratkarahan/verilogeval-v1-codev-qw-7b-results
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