{"sample_i": "BTFLV-tt07-subleq-fram-cpu", "topmodule": "tt_um_btflv_subleq", "code": "`default_nettype none\n\nmodule tt_um_btflv_subleq (\n\tinput  wire [7:0] ui_in  , // Dedicated inputs\n\toutput wire [7:0] uo_out , // Dedicated outputs\n\tinput  wire [7:0] uio_in , // IOs: Input path\n\toutput wire [7:0] uio_out, // IOs: Output path\n\toutput wire [7:0] uio_oe , // IOs: Enable path (active high: 0=input, 1=output)\n\tinput  wire       ena    , // always 1 when the design is powered, so you can ignore it\n\tinput  wire       clk    , // clock\n\tinput  wire       rst_n    // reset_n - low to reset\n);\n\n\tassign in_miso = ui_in[0];\n\n\tassign uio_out     = data;\n\tassign uio_oe      = 8'b11111111;\n\tassign uo_out[0]   = out_mosi;\n\tassign uo_out[1]   = out_sck;\n\tassign uo_out[2]   = out_cs;\n\tassign uo_out[3]   = tx;\n\tassign uo_out[4]   = ctx;\n\tassign uo_out[7:5] = 3'b111;\n\n\tassign char_out     = data_a[7:0];\n\tassign char_valid   = char_output_flag;\n\tassign result       = data_b - data_a;\n\n\treg signed [15:0] ir_a, ir_b, ir_c;\n\treg signed [15:0] data_a, data_b;\n\treg        [ 5:0] state, next_state;\n\treg        [ 7:0] data            ;\n\treg        [15:0] pc              ;\n\treg               char_output_flag;\n\treg               halted_reg      ;\n\treg signed [15:0] data_to_ram     ;\n\treg               ram_we          ;\n\treg        [15:0] ram_addr        ;\n\treg               tx_start        ;\n\treg               ramstart        ;\n\n\twire               ramdone      ;\n\twire        [ 7:0] char_out     ;\n\twire               char_valid   ;\n\twire        [15:0] data_from_ram;\n\twire               tx_busy      ;\n\twire               ctx          ;\n\twire               tx           ;\n\twire signed [15:0] result       ;\n\twire               in_miso      ;\n\twire               out_mosi     ;\n\twire               out_sck      ;\n\twire               out_cs       ;\n\n\tSPI_FRAM_Interface ram (\n\t\t.clk     (clk          ),\n\t\t.rst_n   (rst_n        ),\n\t\t.addr    (ram_addr     ),\n\t\t.spi_miso(in_miso      ),\n\t\t.spi_mosi(out_mosi     ),\n\t\t.spi_sck (out_sck      ),\n\t\t.spi_cs  (out_cs       ),\n\t\t.data_in (data_to_ram  ),\n\t\t.we      (ram_we       ),\n\t\t.start   (ramstart     ),\n\t\t.done    (ramdone      ),\n\t\t.data_out(data_from_ram)\n\t);\n\n\tUART_Credits CreditsTX (\n\t\t.clk  (clk  ),\n\t\t.rst_n(rst_n),\n\t\t.tx   (ctx  )\n\t);\n\n\tUART_Transmitter uart_tx (\n\t\t.clk     (clk     ),\n\t\t.rst_n   (rst_n   ),\n\t\t.tx_start(tx_start),\n\t\t.tx_data (char_out),\n\t\t.tx      (tx      ),\n\t\t.tx_busy (tx_busy )\n\t);\n\n\tlocalparam START\t = 6'd0,\n\t\tFETCH_A0  = 6'd1,\n\t\tFETCH_A1  = 6'd2,\n\t\tFETCH_A2  = 6'd3,\n\t\tFETCH_B0  = 6'd4,\n\t\tFETCH_B1  = 6'd5,\n\t\tFETCH_B2  = 6'd6,\n\t\tFETCH_C0  = 6'd7,\n\t\tFETCH_C1  = 6'd8,\n\t\tFETCH_C2  = 6'd9,\n\t\tDECODE_A0 = 6'd10,\n\t\tDECODE_A1 = 6'd11,\n\t\tDECODE_A2 = 6'd12,\n\t\tDECODE_B0 = 6'd13,\n\t\tDECODE_B1 = 6'd14,\n\t\tDECODE_B2 = 6'd15,\n\t\tWRITE_B0 = 6'd16,\n\t\tWRITE_B1 = 6'd17,\n\t\tWRITE_B2 = 6'd18,\n\t\tHALT     = 6'd19;\n\n\n\n\talways @(posedge clk or negedge rst_n) begin\n\t\tif (!rst_n)\n\t\t\tstate <= START;\n\t\telse\n\t\t\tstate <= next_state;\n\tend\n\n\talways @(posedge clk or negedge rst_n) begin\n\t\tif (!rst_n) begin\n\t\t\tpc               <= 15'd0;\n\t\t\tir_a             <= 16'b0;\n\t\t\tir_b             <= 16'b0;\n\t\t\tir_c             <= 16'b0;\n\t\t\tdata_a           <= 16'b0;\n\t\t\tdata_b           <= 16'b0;\n\t\t\tchar_output_flag <= 1'b0;\n\t\t\thalted_reg       <= 1'b0;\n\t\t\tdata_to_ram      <= 16'b0;\n\t\t\tram_addr         <= 15'b0;\n\t\t\tram_we           <= 1'b0;\n\t\tend else begin\n\t\t\tcase (state)\n\n\t\t\t\tSTART : begin\n\t\t\t\t\tram_addr <= pc;\n\t\t\t\t\tramstart <= 1'b1;\n\t\t\t\tend\n\n\t\t\t\t// Fetch A B C\n\t\t\t\tFETCH_A0 : begin\n\t\t\t\t\tram_addr <= pc;\n\t\t\t\t\tramstart <= 1'b1;\n\t\t\t\tend\n\n\t\t\t\tFETCH_A1 : begin\n\t\t\t\t\tramstart <= 1'b0;\n\t\t\t\tend\n\n\t\t\t\tFETCH_A2 : begin\n\t\t\t\t\tir_a <= data_from_ram;\n\t\t\t\tend\n\n\t\t\t\tFETCH_B0 : begin\n\t\t\t\t\tram_addr <= pc + 1;\n\t\t\t\t\tramstart <= 1'b1;\n\t\t\t\tend\n\n\t\t\t\tFETCH_B1 : begin\n\t\t\t\t\tramstart <= 1'b0;\n\t\t\t\tend\n\n\t\t\t\tFETCH_B2 : begin\n\t\t\t\t\tir_b <= data_from_ram;\n\t\t\t\tend\n\n\t\t\t\tFETCH_C0 : begin\n\t\t\t\t\tram_addr <= pc + 2;\n\t\t\t\t\tramstart <= 1'b1;\n\t\t\t\tend\n\n\t\t\t\tFETCH_C1 : begin\n\t\t\t\t\tramstart <= 1'b0;\n\t\t\t\tend\n\n\t\t\t\tFETCH_C2 : begin\n\t\t\t\t\tir_c <= data_from_ram;\n\t\t\t\tend\n\n\t\t\t\t// Decode A B\n\t\t\t\tDECODE_A0 : begin\n\t\t\t\t\tram_addr <= ir_a;\n\t\t\t\t\tramstart <= 1'b1;\n\t\t\t\tend\n\n\t\t\t\tDECODE_A1 : begin\n\t\t\t\t\tramstart <= 1'b0;\n\t\t\t\tend\n\n\t\t\t\tDECODE_A2 : begin\n\t\t\t\t\tdata_a <= data_from_ram;\n\t\t\t\tend\n\n\t\t\t\tDECODE_B0 : begin\n\t\t\t\t\tif(ir_b == -1) begin\n\t\t\t\t\t\tchar_output_flag <= 1'b1;\n\t\t\t\t\t\tdata             <= char_out;\n\t\t\t\t\t\tram_addr         <= 16'b0;\n\t\t\t\t\t\tramstart         <= 1'b1;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tram_addr <= ir_b;\n\t\t\t\t\t\tramstart <= 1'b1;\n\t\t\t\t\tend\n\t\t\t\t\tif(ir_c < 0) begin\n\t\t\t\t\t\thalted_reg <= 1'b1;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tDECODE_B1 : begin\n\t\t\t\t\tramstart         <= 1'b0;\n\t\t\t\t\tchar_output_flag <= 1'b0;\n\t\t\t\tend\n\n\t\t\t\tDECODE_B2 : begin\n\t\t\t\t\tif(ir_b == -1) begin\n\t\t\t\t\t\tdata_b <= 16'b0;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tdata_b <= data_from_ram;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\t// Write B-A to address B\n\t\t\t\tWRITE_B0 : begin\n\t\t\t\t\tif(ir_b == -1) begin\n\t\t\t\t\t\tram_addr <= 16'b0;\n\t\t\t\t\t\tramstart <= 1'b1;\n\t\t\t\t\t\tram_we   <= 1'b0;\n\t\t\t\t\tend else begin\n\t\t\t\t\t\tram_addr    <= ir_b;\n\t\t\t\t\t\tramstart    <= 1'b1;\n\t\t\t\t\t\tram_we      <= 1'b1;\n\t\t\t\t\t\tdata_to_ram <= result;\n\t\t\t\t\tend\n\t\t\t\tend\n\n\t\t\t\tWRITE_B1 : begin\n\t\t\t\t\tramstart <= 1'b0;\n\t\t\t\tend\n\n\t\t\t\tWRITE_B2 : begin\n\t\t\t\t\tpc     <= (result > 0 || ir_b == -1) ? pc + 3 : ir_c;\n\t\t\t\t\tram_we <= 1'b0;\n\t\t\t\tend\n\n\t\t\t\tHALT : begin\n\t\t\t\t\thalted_reg <= 1'b1;\n\t\t\t\tend\n\n\t\t\tendcase\n\t\tend\n\tend\n\n\talways @(*) begin\n\t\tif(halted_reg)\n\t\t\tnext_state = HALT;\n\t\telse\n\t\t\tcase (state)\n\t\t\t\tSTART     : next_state = FETCH_A0;\n\t\t\t\tFETCH_A0  : next_state = FETCH_A1;\n\t\t\t\tFETCH_A1  : next_state = ramdone ? FETCH_A2 : FETCH_A1;\n\t\t\t\tFETCH_A2  : next_state = FETCH_B0;\n\t\t\t\tFETCH_B0  : next_state = FETCH_B1;\n\t\t\t\tFETCH_B1  : next_state = ramdone ? FETCH_B2 : FETCH_B1;\n\t\t\t\tFETCH_B2  : next_state = FETCH_C0;\n\t\t\t\tFETCH_C0  : next_state = FETCH_C1;\n\t\t\t\tFETCH_C1  : next_state = ramdone ? FETCH_C2 : FETCH_C1;\n\t\t\t\tFETCH_C2  : next_state = DECODE_A0;\n\t\t\t\tDECODE_A0 : next_state = DECODE_A1;\n\t\t\t\tDECODE_A1 : next_state = ramdone ? DECODE_A2 : DECODE_A1;\n\t\t\t\tDECODE_A2 : next_state = DECODE_B0;\n\t\t\t\tDECODE_B0 : next_state = DECODE_B1;\n\t\t\t\tDECODE_B1 : next_state = ramdone ? DECODE_B2 : DECODE_B1;\n\t\t\t\tDECODE_B2 : next_state = !tx_busy ? WRITE_B0 : DECODE_B2;\n\t\t\t\tWRITE_B0  : next_state = WRITE_B1;\n\t\t\t\tWRITE_B1  : next_state = ramdone ? WRITE_B2 : WRITE_B1;\n\t\t\t\tWRITE_B2  : next_state = FETCH_A0;\n\t\t\t\tHALT      : next_state = HALT;\n\t\t\tendcase\n\tend\n\n\talways @(posedge clk or negedge rst_n) begin\n\t\tif (!rst_n) begin\n\t\t\ttx_start <= 1'b0;\n\t\tend else begin\n\t\t\tif (char_valid && !tx_busy) begin\n\t\t\t\ttx_start <= 1'b1;\n\t\t\tend else begin\n\t\t\t\ttx_start <= 1'b0;\n\t\t\tend\n\t\tend\n\tend\n\nendmodule\n\n\nmodule SPI_FRAM_Interface (\n    input  wire            clk     ,\n    input  wire            rst_n   ,\n    input                  spi_miso,\n    output      reg        spi_mosi,\n    output      reg        spi_sck ,\n    output      reg        spi_cs  ,\n    input  wire     [15:0] addr    ,\n    input  wire     [15:0] data_in ,\n    input  wire            we      ,\n    input  wire            start   ,\n    output      reg [15:0] data_out,\n    output      reg        done\n);\n\n    assign write_data_l = data_in[7:0];\n    assign write_data_h = data_in[15:8];\n    assign address      = (addr[14:0] << 1)  + !hbyte;\n    assign write_enable = we;\n\n    reg [7:0] temp_data  ;\n    reg [4:0] state      ;\n    reg [4:0] bit_counter;\n    reg [5:0] spi_clk    ;\n    reg       clk_out    ;\n    reg       hbyte      ;\n\n    wire [ 7:0] write_data_l;\n    wire [ 7:0] write_data_h;\n    wire        write_enable;\n    wire [15:0] address     ;\n\n    parameter CMD_READ  = 8'h03;\n    parameter CMD_WRITE = 8'h02;\n    parameter CMD_WREN  = 8'h06;\n    parameter CMD_WRDI  = 8'h04;\n\n    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            spi_clk <= 6'd0;\n            clk_out <= 1'b0;\n        end else begin\n            if (spi_clk == 6'd7) begin\n                spi_clk <= 6'd0;\n                clk_out <= ~clk_out;\n            end else begin\n                spi_clk <= spi_clk + 1;\n            end\n        end\n    end\n\n    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            spi_cs      <= 1;\n            spi_sck     <= 0;\n            spi_mosi    <= 0;\n            state       <= 0;\n            bit_counter <= 0;\n            hbyte       <= 0;\n        end else begin\n            case (state)\n                0 : begin\n                    done <= 0;\n                    if (start && write_enable) begin\n                        state    <= 6;\n                        spi_mosi <= CMD_WREN[7];\n                    end else if (start || hbyte) begin\n                        state    <= 1;\n                        spi_cs   <= 0;\n                        spi_mosi <= 0;\n                        spi_sck  <= 0;\n                    end\n                end\n                1 : begin // Send read command\n                    if (bit_counter < 8) begin\n                        spi_mosi <= CMD_READ[7 - bit_counter];\n                        spi_sck  <= ~spi_sck;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        spi_mosi    <= address[15];\n                        spi_sck     <= 0;\n                        state       <= 2;\n                    end\n                end\n                2 : begin // Send address (16 bits)\n                    if (bit_counter < 16) begin\n                        spi_mosi <= address[15 - bit_counter];\n                        spi_sck  <= ~spi_sck;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        spi_mosi    <= 0;\n                        spi_sck     <= 0;\n                        state       <= 3;\n                    end\n                end\n                3 : begin // Wait\n                    if (bit_counter < 8) begin\n                        bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        state       <= 4;\n                    end\n                end\n                4 : begin // Read data byte\n                    if (bit_counter < 8) begin\n                        spi_sck <= ~spi_sck;\n                        if (~spi_sck) temp_data[7 - bit_counter] <= spi_miso;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        if(hbyte)\n                            begin\n                                data_out[15:8] <= temp_data;\n                            end\n                        else\n                            begin\n                                data_out[7:0] <= temp_data;\n                            end\n                        bit_counter <= 0;\n                        spi_mosi    <= 0;\n                        spi_sck     <= 0;\n                        state       <= 5;\n                        hbyte       <= ~hbyte;\n                    end\n                end\n                5 : begin // End communication\n                    spi_cs <= 1;\n                    if(hbyte)\n                        begin\n                            state <= 0;\n                        end\n                    else\n                        begin\n                            state <= 16;\n                        end\n                end\n                6 : begin // Send Write Enable (WREN) command\n                    spi_cs <= 0;\n                    if (bit_counter < 8) begin\n                        spi_mosi <= CMD_WREN[7 - bit_counter];\n                        spi_sck  <= ~spi_sck;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        spi_mosi    <= 0;\n                        spi_sck     <= 0;\n                        state       <= 7;\n                    end\n                end\n                7 : begin // End WREN command\n                    spi_cs <= 1;\n                    state  <= 8;\n                end\n                8 : begin // Wait\n                    if (bit_counter < 8) begin\n                        bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        state       <= 9;\n                        spi_mosi    <= CMD_WRITE[7];\n                    end\n                end\n                9 : begin // Send write command\n                    spi_cs <= 0;\n                    if (bit_counter < 8) begin\n                        spi_mosi <= CMD_WRITE[7 - bit_counter];\n                        spi_sck  <= ~spi_sck;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        spi_mosi    <= address[15];\n                        spi_sck     <= 0;\n                        state       <= 10;\n                    end\n                end\n                10 : begin // Send address (16 bits) for writing\n                    if (bit_counter < 16) begin\n                        spi_mosi <= address[15 - bit_counter];\n                        spi_sck  <= ~spi_sck;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        spi_sck     <= 0;\n                        state       <= 11;\n                        if(hbyte) begin\n                            spi_mosi <= write_data_h[7];\n                        end else begin\n                            spi_mosi <= write_data_l[7];\n                        end\n                    end\n                end\n                11 : begin // Write data byte\n                    if (bit_counter < 8) begin\n                        if(hbyte) begin\n                            spi_mosi <= write_data_h[7 - bit_counter];\n                        end else begin\n                            spi_mosi <= write_data_l[7 - bit_counter];\n                        end\n                        spi_sck <= ~spi_sck;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        spi_mosi    <= 0;\n                        spi_sck     <= 0;\n                        state       <= 12;\n                        hbyte       <= ~hbyte;\n                    end\n                end\n                12 : begin // End write communication\n                    spi_cs <= 1;\n                    state  <= 13;\n                end\n                13 : begin // Wait\n                    if (bit_counter < 8) begin\n                        bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        state       <= 14;\n                        spi_mosi    <= CMD_WRDI[7];\n                    end\n                end\n                14 : begin // Send Write Disable (WRDI) command\n                    spi_cs <= 0;\n                    if (bit_counter < 8) begin\n                        spi_mosi <= CMD_WRDI[7 - bit_counter];\n                        spi_sck  <= ~spi_sck;\n                        if (!spi_sck) bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        spi_mosi    <= 0;\n                        spi_sck     <= 0;\n                        state       <= 15;\n                    end\n                end\n                15 : begin // End WRDI command\n                    spi_cs <= 1;\n                    if(hbyte)\n                        begin\n                            state <= 6;\n                        end\n                    else\n                        begin\n                            state <= 16;\n                        end\n                end\n                16 : begin // Wait\n                    if (bit_counter < 8) begin\n                        bit_counter <= bit_counter + 1;\n                    end else begin\n                        bit_counter <= 0;\n                        state       <= 0;\n                        done        <= 1;\n                    end\n                end\n            endcase\n        end\n    end\nendmodule\n\n\nmodule UART_Credits (\n    input  wire     clk  ,\n    input  wire     rst_n,\n    output      reg tx\n);\n\n    reg [ 1:0] state              = INIT       ;\n    reg [31:0] clk_counter        = 0          ;\n    reg [ 3:0] bit_counter        = 0          ;\n    reg [ 3:0] char_counter       = 0          ;\n    reg [ 7:0] tx_shift_reg       = 8'b11111111;\n    reg [31:0] idle_counter       = 0          ;\n    reg [ 7:0] MESSAGE     [0:10]              ;\n\n    parameter CLK_FREQ   = 10000000; // 10 MHz\n    parameter BAUD_RATE  = 115200  ; // 115200 baud\n    parameter BIT_PERIOD = 87      ; // CLK_FREQ / BAUD_RATE\n    parameter BIT_COUNT  = 10      ; // 1 start bit, 8 data bits, 1 stop bit\n    parameter IDLE_COUNT = 8700    ; // Delay\n\n    localparam [7:0] CHAR_P     = 8'd80 ;\n    localparam [7:0] CHAR_h     = 8'd104;\n    localparam [7:0] CHAR_i     = 8'd105;\n    localparam [7:0] CHAR_l     = 8'd108;\n    localparam [7:0] CHAR_i2    = 8'd105;\n    localparam [7:0] CHAR_p     = 8'd112;\n    localparam [7:0] CHAR_space = 8'd32 ;\n    localparam [7:0] CHAR_M     = 8'd77 ;\n    localparam [7:0] CHAR_o     = 8'd111;\n    localparam [7:0] CHAR_h2    = 8'd104;\n    localparam [7:0] CHAR_r     = 8'd114;\n\n    localparam INIT = 0, IDLE = 1, START = 2, TRANSMIT = 3;\n\n    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            clk_counter  <= 0;\n            bit_counter  <= 0;\n            char_counter <= 0;\n            tx_shift_reg <= 8'b11111111;\n            idle_counter <= 0;\n            tx           <= 1'b1;\n            state        <= INIT;\n        end else begin\n            case (state)\n                INIT : begin\n                    MESSAGE[0]  <= CHAR_P;\n                    MESSAGE[1]  <= CHAR_h;\n                    MESSAGE[2]  <= CHAR_i;\n                    MESSAGE[3]  <= CHAR_l;\n                    MESSAGE[4]  <= CHAR_i2;\n                    MESSAGE[5]  <= CHAR_p;\n                    MESSAGE[6]  <= CHAR_space;\n                    MESSAGE[7]  <= CHAR_M;\n                    MESSAGE[8]  <= CHAR_o;\n                    MESSAGE[9]  <= CHAR_h2;\n                    MESSAGE[10] <= CHAR_r;\n                    state       <= START;\n                end\n                IDLE : begin\n                    if (idle_counter < IDLE_COUNT) begin\n                        idle_counter <= idle_counter + 1;\n                    end else begin\n                        idle_counter <= 0;\n                        state        <= START;\n                    end\n                end\n                START : begin\n                    char_counter <= 0;\n                    tx_shift_reg <= MESSAGE[0];\n                    state        <= TRANSMIT;\n                end\n                TRANSMIT : begin\n                    if (clk_counter < BIT_PERIOD) begin\n                        clk_counter <= clk_counter + 1;\n                    end else begin\n                        clk_counter <= 0;\n                        if (bit_counter < BIT_COUNT) begin\n                            bit_counter <= bit_counter + 1;\n                            case (bit_counter)\n                                0 : tx <= 1'b0;\n                                1 : tx <= tx_shift_reg[0];\n                                2 : tx <= tx_shift_reg[1];\n                                3 : tx <= tx_shift_reg[2];\n                                4 : tx <= tx_shift_reg[3];\n                                5 : tx <= tx_shift_reg[4];\n                                6 : tx <= tx_shift_reg[5];\n                                7 : tx <= tx_shift_reg[6];\n                                8 : tx <= tx_shift_reg[7];\n                                9 : tx <= 1'b1;\n                            endcase\n                        end else begin\n                            bit_counter <= 0;\n                            if (char_counter < 10) begin\n                                char_counter <= char_counter + 1;\n                                tx_shift_reg <= MESSAGE[char_counter + 1];\n                            end else begin\n                                char_counter <= 0;\n                                state        <= IDLE;\n                            end\n                        end\n                    end\n                end\n            endcase\n        end\n    end\nendmodule\n\n\nmodule UART_Transmitter (\n    input  wire           clk     ,\n    input  wire           rst_n   ,\n    input  wire           tx_start,\n    input  wire     [7:0] tx_data ,\n    output      reg       tx      ,\n    output      reg       tx_busy\n);\n\n    reg [15:0] baud_counter;\n    reg [ 3:0] bit_counter ;\n    reg [ 7:0] shift_reg   ;\n    reg        transmitting;\n\n    localparam CLK_FREQ   = 10000000; // 10 MHz\n    localparam BAUD_RATE  = 115200  ; // 115200 baud\n    localparam BIT_PERIOD = 87      ; // CLK_FREQ / BAUD_RATE\n\n    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            tx           <= 1'b1;\n            tx_busy      <= 1'b0;\n            transmitting <= 1'b0;\n            baud_counter <= 0;\n            bit_counter  <= 0;\n            shift_reg    <= 0;\n        end else begin\n            if (tx_start && !transmitting) begin\n                transmitting <= 1'b1;\n                tx_busy      <= 1'b1;\n                shift_reg    <= tx_data;\n                bit_counter  <= 0;\n                baud_counter <= 0;\n                tx           <= 1'b0;\n            end else if (transmitting) begin\n                if (baud_counter < BIT_PERIOD - 1) begin\n                    baud_counter <= baud_counter + 1;\n                end else begin\n                    baud_counter <= 0;\n                    if (bit_counter < 8) begin\n                        tx          <= shift_reg[0];\n                        shift_reg   <= shift_reg >> 1;\n                        bit_counter <= bit_counter + 1;\n                    end else if (bit_counter == 8) begin\n                        tx          <= 1'b1;\n                        bit_counter <= bit_counter + 1;\n                    end else begin\n                        tx_busy      <= 1'b0;\n                        transmitting <= 1'b0;\n                        bit_counter  <= 0;\n                    end\n                end\n            end\n        end\n    end\nendmodule\n", "mask_idx": {"conditional_statement": [[15596, 15827], [20025, 20374], [9848, 10073], [22057, 22379], [8805, 9247], [5314, 6317]], "blocking_assignment": [[5884, 5929], [6150, 6172], [6288, 6306], [5429, 5451], [5606, 5649]], "module_program_interface_instantiation": [[1761, 2124], [2127, 2205], [2208, 2375]], "always_construct": [[7986, 16230], [5294, 6322], [2910, 5291]], "case_statement": [[17841, 20466], [8272, 16210], [3322, 5280], [5361, 6317], [19289, 19911]], "ansi_port_declaration": [[414, 449], [20709, 20738], [6812, 6844], [6738, 6770]], "continuous_assign": [[7033, 7068], [747, 775], [7073, 7109], [720, 745]], "parameter_declaration": [[16931, 16972], [7517, 7545], [7583, 7611], [7550, 7578], [7484, 7512], [16854, 16926], [16793, 16849]], "nonblocking_assignment": [[4890, 4907], [6393, 6410], [18032, 18054], [5082, 5099], [8331, 8341], [17946, 17968], [11156, 11167], [4988, 5008]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1761, 2124], [2127, 2205], [2208, 2375]], "continuous_assign": [[509, 535], [538, 564], [566, 599], [601, 631], [633, 662], [664, 692], [694, 718], [720, 745], [747, 775], [778, 812], [814, 853], [855, 893], [7033, 7068], [7073, 7109], [7114, 7164], [7169, 7194]], "blocking_assignment": [[5332, 5350], [5390, 5412], [5429, 5451], [5468, 5511], [5528, 5550], [5567, 5589], [5606, 5649], [5666, 5688], [5705, 5727], [5744, 5787], [5804, 5827], [5844, 5867], [5884, 5929], [5946, 5969], [5986, 6009], [6026, 6071], [6088, 6133], [6150, 6172], [6189, 6232], [6249, 6271], [6288, 6306]], "nonblocking_assignment": [[2856, 2871], [2882, 2902], [2978, 3004], [3008, 3034], [3038, 3064], [3068, 3094], [3098, 3124], [3128, 3154], [3158, 3183], [3187, 3212], [3216, 3242], [3246, 3272], [3276, 3301], [3359, 3374], [3380, 3397], [3452, 3467], [3473, 3490], [3526, 3543], [3579, 3601], [3637, 3656], [3662, 3679], [3715, 3732], [3768, 3790], [3826, 3845], [3851, 3868], [3904, 3921], [3957, 3979], [4034, 4051], [4057, 4074], [4111, 4128], [4165, 4189], [4253, 4278], [4285, 4314], [4321, 4347], [4354, 4379], [4406, 4423], [4430, 4447], [4487, 4506], [4552, 4577], [4583, 4608], [4672, 4688], [4715, 4739], [4841, 4859], [4866, 4883], [4890, 4907], [4934, 4954], [4961, 4981], [4988, 5008], [5015, 5037], [5082, 5099], [5135, 5188], [5194, 5209], [5241, 5260], [6393, 6410], [6469, 6486], [6509, 6526], [7700, 7716], [7729, 7745], [7824, 7840], [7857, 7877], [7921, 7944], [8069, 8086], [8099, 8116], [8129, 8146], [8159, 8176], [8189, 8206], [8219, 8236], [8331, 8341], [8419, 8433], [8458, 8482], [8562, 8576], [8601, 8615], [8640, 8654], [8679, 8693], [8856, 8894], [8919, 8940], [8979, 9010], [9070, 9087], [9112, 9139], [9164, 9181], [9206, 9223], [9392, 9430], [9455, 9476], [9515, 9546], [9606, 9623], [9648, 9665], [9690, 9707], [9732, 9749], [9899, 9930], [9990, 10007], [10032, 10049], [10209, 10229], [10268, 10307], [10346, 10377], [10513, 10541], [10669, 10696], [10753, 10770], [10795, 10812], [10837, 10854], [10879, 10896], [10921, 10943], [11055, 11067], [11156, 11167], [11279, 11291], [11422, 11434], [11506, 11544], [11569, 11590], [11629, 11660], [11720, 11737], [11762, 11779], [11804, 11821], [11846, 11863], [11974, 11986], [12007, 12019], [12145, 12176], [12236, 12253], [12278, 12295], [12320, 12348], [12461, 12473], [12545, 12584], [12609, 12630], [12669, 12700], [12760, 12777], [12802, 12829], [12854, 12871], [12896, 12914], [13096, 13134], [13159, 13180], [13219, 13250], [13310, 13327], [13352, 13369], [13394, 13412], [13481, 13509], [13577, 13605], [13839, 13881], [13949, 13991], [14044, 14064], [14103, 14134], [14194, 14211], [14236, 14253], [14278, 14295], [14320, 14338], [14363, 14385], [14504, 14516], [14537, 14550], [14677, 14708], [14768, 14785], [14810, 14828], [14853, 14880], [15009, 15021], [15093, 15131], [15156, 15177], [15216, 15247], [15307, 15324], [15349, 15366], [15391, 15408], [15433, 15451], [15563, 15575], [15664, 15675], [15787, 15799], [15954, 15985], [16045, 16062], [16087, 16104], [16129, 16146], [17585, 17603], [17616, 17634], [17647, 17665], [17678, 17706], [17719, 17737], [17750, 17771], [17784, 17805], [17903, 17925], [17946, 17968], [17989, 18011], [18032, 18054], [18075, 18098], [18119, 18141], [18162, 18188], [18209, 18231], [18252, 18274], [18295, 18318], [18339, 18361], [18382, 18403], [18534, 18567], [18627, 18645], [18670, 18692], [18787, 18805], [18826, 18853], [18874, 18899], [19033, 19064], [19124, 19141], [19229, 19260], [19344, 19355], [19392, 19414], [19451, 19473], [19510, 19532], [19569, 19591], [19628, 19650], [19687, 19709], [19746, 19768], [19805, 19827], [19864, 19875], [19979, 19996], [20086, 20119], [20152, 20194], [20270, 20288], [20321, 20342], [21111, 21132], [21145, 21166], [21179, 21200], [21213, 21231], [21244, 21262], [21275, 21293], [21382, 21403], [21420, 21441], [21458, 21482], [21499, 21517], [21534, 21552], [21569, 21590], [21713, 21746], [21798, 21816], [21888, 21916], [21941, 21971], [21996, 22027], [22109, 22129], [22154, 22185], [22245, 22266], [22291, 22312], [22337, 22355]], "case_statement": [[3322, 5280], [5361, 6317], [8272, 16210], [17841, 20466], [19289, 19911]], "conditional_statement": [[2841, 2902], [2957, 5286], [4226, 4456], [4462, 4515], [4645, 4748], [4814, 5046], [5314, 6317], [6372, 6539], [6431, 6533], [7670, 7972], [7781, 7960], [8039, 16222], [8362, 8717], [8512, 8717], [8805, 9247], [8965, 9010], [9340, 9773], [9501, 9546], [9848, 10073], [10158, 10967], [10254, 10307], [10332, 10377], [10437, 10728], [11088, 11319], [11455, 11887], [11615, 11660], [12094, 12372], [12494, 12938], [12655, 12700], [13044, 13657], [13205, 13250], [13437, 13633], [13744, 14409], [13795, 14019], [14089, 14134], [14626, 14904], [15042, 15475], [15202, 15247], [15596, 15827], [15903, 16170], [17555, 20478], [18473, 18716], [18973, 20426], [19166, 20402], [20025, 20374], [21081, 22427], [21329, 22415], [21612, 22415], [21652, 22399], [21837, 22379], [22057, 22379]], "always_construct": [[2794, 2907], [2910, 5291], [5294, 6322], [6325, 6544], [7617, 7980], [7986, 16230], [17502, 20486], [21028, 22435]], "parameter_declaration": [[7484, 7512], [7517, 7545], [7550, 7578], [7583, 7611], [16694, 16736], [16741, 16788], [16793, 16849], [16854, 16926], [16931, 16972]], "ansi_port_declaration": [[52, 98], [100, 147], [149, 194], [196, 242], [244, 323], [325, 412], [414, 449], [451, 503], [6590, 6622], [6627, 6659], [6664, 6696], [6701, 6733], [6738, 6770], [6775, 6807], [6812, 6844], [6849, 6881], [6886, 6918], [6923, 6955], [6960, 6992], [6997, 7024], [16269, 16291], [16296, 16318], [16323, 16341], [20529, 20560], [20565, 20596], [20601, 20632], [20637, 20668], [20673, 20704], [20709, 20738]]}}
{"sample_i": "JamesTimothyMeech-TT07-LFSR", "topmodule": "tt_um_lfsr", "code": "/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_lfsr (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n    wire rst = ! rst_n;\n    assign uio_oe = 8'b00000000;\n    assign uio_out = 8'b00000000;\n    assign uo_out[7:3] = 5'b00000;\n\n    wb_lfsr wb_lfsr(\n      .i_clk(clk), \n      .i_reset(rst), \n      .i_wb_cyc(uio_in[0]), \n      .i_wb_stb(uio_in[1]), \n      .i_wb_we(uio_in[2]), \n      .i_wb_addr(uio_in[5:3]), \n      .i_wb_data(ui_in), \n      .o_wb_stall(uo_out[0]),\n      .o_wb_data(uo_out[1]),\n      .o_wb_ack(uo_out[2])\n);\n\nendmodule\n\n\nmodule linear_feedback_shift_register(out, clock, reset, seed, load_seed);\n\toutput reg out;\n\tinput [31:0] seed;\n\tinput load_seed;\n\tinput reset;\n\tinput clock;\n\twire [31:0] flip_flop_outputs;\n\twire [31:0] flip_flop_inputs;\n\twire feedback1, feedback2, feedback3;\n\tflip_flop flip_flop_instance[31:0] (flip_flop_outputs, clock, reset, flip_flop_inputs);\n\tone_bit_mux muxes[31:0] (flip_flop_inputs, load_seed, seed, {flip_flop_outputs[30:0], feedback3});\n\txor feedback_gate_one(feedback1, flip_flop_outputs[6], flip_flop_outputs[31]);\n\txor feedback_gate_two(feedback2, feedback1, flip_flop_outputs[5]);\n\txor feedback_gate_three(feedback3, feedback2, flip_flop_outputs[1]);\n\tassign out = feedback3;\nendmodule\n\nmodule flip_flop(out, clock, reset, in);\n\tinput clock;\n\tinput reset;\n\tinput in;\n\toutput reg out;\n\talways @(posedge clock or posedge reset)\n\tbegin\n\n\tif (reset)\n\t\tout = 0;\n\telse\n\t\tout = in;\n\tend\nendmodule\n\nmodule one_bit_mux(out, control, input_a, input_b);\n\toutput reg out;\n\tinput control, input_a, input_b;\n\twire not_control;\n\talways @(control or not_control or input_a or input_b)\n\t\tout = (control & input_a) | (not_control & input_b);\n\t\tnot (not_control, control);\nendmodule\n\n\nmodule wb_lfsr(i_clk, i_reset, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, o_wb_stall, o_wb_data, o_wb_ack);\n\tinput i_clk;\n\tinput i_reset;\n\tinput i_wb_cyc;\n\tinput i_wb_stb;\n\tinput i_wb_we;\n\tinput [2:0] i_wb_addr;\n\tinput[7:0] i_wb_data;\n\n\toutput reg o_wb_stall;\n\toutput reg o_wb_ack;\n\toutput reg o_wb_data;\n\n\treg [31:0] seed;\n    reg lfsr_reset;\n\treg load_seed;\n\twire lfsr_out;\n\n\tlinear_feedback_shift_register FLSR_instance(lfsr_out, i_clk, lfsr_reset, seed, load_seed);\n\n\tassign\to_wb_stall = 1'b0;\n\n\talways @(posedge i_clk)\n\tif ((i_wb_stb)&&(i_wb_we)&&(!o_wb_stall)&&(i_wb_cyc))\n\tbegin\n\t\tcase (i_wb_addr)\n\t\t\t3'b000 :\tseed[7:0] <= i_wb_data;\n\t\t\t3'b001 :\tseed[15:8] <= i_wb_data;\n\t\t\t3'b010 :\tseed[23:16] <= i_wb_data;\n\t\t\t3'b011 :\tseed[31:24] <= i_wb_data;\n\t\t\t3'b100 :\n\t\t\tbegin\n\t\t\t    lfsr_reset <= i_wb_data[0];\n        \t\tload_seed <= i_wb_data[1];\n        \tend\n\t\t\tdefault:\tseed <= 0;\n\t\tendcase\n\tend\n\n\talways @(posedge i_clk)\n\tif ((i_wb_stb)&&(!i_wb_we)&&(!o_wb_stall)&&(i_wb_cyc))\n\tbegin\n        o_wb_data <= lfsr_out;\n\tend\n\n\tinitial\to_wb_ack = 1'b0;\n\n\talways @(posedge i_clk)\n\tif (i_reset) begin\n\t\to_wb_ack <= 1'b0;\n\tend else\n\t\to_wb_ack <= ((i_wb_stb) && (!o_wb_stall));\n\nendmodule\n", "mask_idx": {"conditional_statement": [[2762, 3134], [1898, 1937], [3314, 3407], [3162, 3259]], "blocking_assignment": [[1911, 1919], [3270, 3286], [1928, 1937], [2134, 2186]], "module_program_interface_instantiation": [[742, 1033], [2615, 2706], [1308, 1395]], "always_construct": [[3289, 3407], [2737, 3134], [3137, 3259], [2077, 2186]], "case_statement": [[2825, 3129]], "ansi_port_declaration": [[553, 606], [1779, 1790], [1104, 1121]], "continuous_assign": [[672, 701], [706, 736], [639, 667]], "nonblocking_assignment": [[3365, 3407], [3109, 3119], [2927, 2952]]}, "all_mask_idx": {"module_program_interface_instantiation": [[742, 1033], [1308, 1395], [1397, 1495], [2615, 2706]], "continuous_assign": [[639, 667], [672, 701], [706, 736], [1715, 1738], [2709, 2734]], "blocking_assignment": [[1911, 1919], [1928, 1937], [2134, 2186], [3270, 3286]], "nonblocking_assignment": [[2854, 2877], [2890, 2914], [2927, 2952], [2965, 2990], [3019, 3046], [3057, 3083], [3109, 3119], [3232, 3254], [3335, 3352], [3365, 3407]], "case_statement": [[2825, 3129]], "conditional_statement": [[1898, 1937], [2762, 3134], [3162, 3259], [3314, 3407]], "always_construct": [[1848, 1942], [2077, 2186], [2737, 3134], [3137, 3259], [3289, 3407]], "parameter_declaration": [], "ansi_port_declaration": [[126, 173], [178, 226], [231, 277], [282, 329], [334, 414], [419, 507], [512, 548], [553, 606], [1085, 1121], [1090, 1121], [1097, 1121], [1104, 1121], [1110, 1121], [1767, 1790], [1772, 1790], [1779, 1790], [1786, 1790], [1973, 2005], [1978, 2005], [1987, 2005], [1996, 2005], [2244, 2344], [2251, 2344], [2260, 2344], [2270, 2344], [2280, 2344], [2289, 2344], [2300, 2344], [2311, 2344], [2323, 2344], [2334, 2344]]}}
{"sample_i": "Kevomlml-tt07_chipusm_neural_network", "topmodule": "tt_um_neural_network", "code": "module machine (\n    input wire clk,\n    input wire reset,\n    input wire changes,\n    input wire finished,\n    output reg [1:0] state\n);\n\nparameter state_data_IN = 2'b00;\nparameter state_data_BUFF = 2'b01;\nparameter state_data_OUT = 2'b10;\n\n\n//Definir current_state y next_state\nreg [1:0] current_state, next_state;\n\nalways@(posedge clk) begin \n    if (reset)\n        current_state <= state_data_IN;\n    else\n        current_state <= next_state;\nend \n\nalways @(*) begin\n    next_state = current_state;\n    case (current_state)\n        state_data_IN: if (changes) begin\n                        next_state = state_data_BUFF;\n                        end\n        state_data_BUFF: if (changes) begin\n                        next_state = state_data_OUT;\n                        end\n        state_data_OUT: if (changes) begin\n                        next_state = state_data_BUFF;\n                        end else if (finished) begin\n                        next_state = state_data_IN; //show the results\n                        end\n        default: if (changes) begin\n                next_state=current_state;\n                end\n    endcase\nend\n\nalways@(posedge clk) begin \n    if (reset)\n        state <= state_data_IN;\n    else\n        state <= current_state;\nend \nendmodule\n\n\nmodule perceptron(\n    input [7:0] in0,\n    input [7:0] in1,\n    input [7:0] in2,\n    input [7:0] in3,\n\n    input [7:0] weight0, //aaa\n    input [7:0] weight1,\n    input [7:0] weight2,\n    input [7:0] weight3,\n    input [7:0] bias,\n    input [7:0] threshold,\n\n    output reg [7:0] out\n);\n\nreg [7:0] sum_p;\nreg [7:0] res;\n\nalways@(*)\nbegin\n    \n    sum_p=(in0<<weight0)+(in1<<weight1)+(in2<weight2)+(in3<<weight3)+bias;\n    res = sum_p - threshold;\n    if (res[7])\n        out = 8'b00000000;\n    else\n        out = sum_p;\nend\n\nendmodule\n\n\nmodule register_parameters(\n    input wire clk,\n    input wire reset,\n    input wire [7:0] data_in,\n    input [1:0] selector,\n\n    //output reg [7:0] th3,\n    output reg [7:0] b3,\n    output reg [7:0] w33,\n    output reg [7:0] w32,\n    output reg [7:0] w31,\n    output reg [7:0] w30,\n    //output reg [7:0] th2,\n    output reg [7:0] b2,\n    output reg [7:0] w23,\n    output reg [7:0] w22,\n    output reg [7:0] w21,\n    output reg [7:0] w20,\n    //output reg [7:0] th1,\n    output reg [7:0] b1,\n    output reg [7:0] w13,\n    output reg [7:0] w12,\n    output reg [7:0] w11,\n    output reg [7:0] w10,\n    //output reg [7:0] th0,\n    output reg [7:0] b0,\n    output reg [7:0] w03,\n    output reg [7:0] w02,\n    output reg [7:0] w01,\n    output reg [7:0] w00\n);\n\nalways @(posedge clk)\nbegin\n    if (reset) begin\n    w00<=8'd0;\n    w01<=8'd0;\n    w02<=8'd0;\n    w03<=8'd0;\n    b0<=8'd0;\n    //th0<=8'd0;\n    w10<=8'd0;\n    w11<=8'd0;\n    w12<=8'd0;\n    w13<=8'd0;\n    b1<=8'd0;\n    //th1<=8'd0;\n    w20<=8'd0;\n    w21<=8'd0;\n    w22<=8'd0;\n    w23<=8'd0;\n    b2<=8'd0;\n    //th2<=8'd0;\n    w30<=8'd0;\n    w31<=8'd0;\n    w32<=8'd0;\n    w33<=8'd0;\n    b3<=8'd0;\n    //th3<=8'd0;\n    end\n\n    else begin\n        case(selector)\n            2'b00   :   begin \n                        w00<=w00;\n                        w01<=w01;\n                        w02<=w02;\n                        w03<=w03;\n                        b0<=b0;\n                        //th0<=th0;\n                        w10<=w11;\n                        w11<=w11;\n                        w12<=w12;\n                        w13<=w13;\n                        b1<=b1;\n                        //th1<=th1;\n                        w20<=w21;\n                        w21<=w21;\n                        w22<=w22;\n                        w23<=w23;\n                        b2<=b2;\n                        //th2<=th2;\n                        w30<=w31;\n                        w31<=w31;\n                        w32<=w32;\n                        w33<=w33;\n                        b3<=b3;\n                        //th3<=th3;\n                        end\n            2'b01   :   begin \n                        w00<=w01;\n                        w01<=w02;\n                        w02<=w03;\n                        w03<=b0;\n                        //b0<=th0;\n                        b0<=w10;\n                        //th0<=w10;\n                        w10<=w11;\n                        w11<=w12;\n                        w12<=w13;\n                        w13<=b1;\n                        //b1<=th1;\n                        b1<=w20;\n                        //th1<=w20;\n                        w20<=w21;\n                        w21<=w22;\n                        w22<=w23;\n                        w23<=b2;\n                        //b2<=th2;\n                        b2<=w30;\n                        //th2<=w30;\n                        w30<=w31;\n                        w31<=w32;\n                        w32<=w33;\n                        w33<=b3;\n                        //b3<=th3;\n                        b3<=data_in;\n                        //th3<=data_in;\n                        end\n            2'b10   :   begin \n                        w00<=w00;\n                        w01<=w01;\n                        w02<=w02;\n                        w03<=w03;\n                        b0<=b0;\n                        //th0<=th0;\n                        w10<=w11;\n                        w11<=w11;\n                        w12<=w12;\n                        w13<=w13;\n                        b1<=b1;\n                        //th1<=th1;\n                        w20<=w21;\n                        w21<=w21;\n                        w22<=w22;\n                        w23<=w23;\n                        b2<=b2;\n                        //th2<=th2;\n                        w30<=w31;\n                        w31<=w31;\n                        w32<=w32;\n                        w33<=w33;\n                        b3<=b3;\n                        //th3<=th3;\n                        end\n            default :   begin \n                        w00<=w00;\n                        w01<=w01;\n                        w02<=w02;\n                        w03<=w03;\n                        b0<=b0;\n                        //th0<=th0;\n                        w10<=w11;\n                        w11<=w11;\n                        w12<=w12;\n                        w13<=w13;\n                        b1<=b1;\n                        //th1<=th1;\n                        w20<=w21;\n                        w21<=w21;\n                        w22<=w22;\n                        w23<=w23;\n                        b2<=b2;\n                        //th2<=th2;\n                        w30<=w31;\n                        w31<=w31;\n                        w32<=w32;\n                        w33<=w33;\n                        b3<=b3;\n                        //th3<=th3;\n                        end\n            endcase\n    end\nend\n    \nendmodule\n\n\nmodule shift_register_inputs(\n    input clk,rstn,\n    input [7:0] data_in,\n    input [1:0] selector,  // From the state machine. Determines where do the neuron inputs come From\n    //input [1:0] selector_output,\n    \n    // The outputs of the neurons0..3 are inputs to the shift register, so it can use them as inputs to the next layer\n    input [7:0] neuron0_output, // The output of the neuron0, is an input to the shift register \n    input [7:0] neuron1_output, // The output of the neuron1, is an input to the shift register\n    input [7:0] neuron2_output, // The output of the neuron2, is an input to the shift register\n    input [7:0] neuron3_output, // The output of the neuron3, is an input to the shift register\n\n    // These 4 outputs are the inputs0..3 to each neuron.\n    output reg [7:0] neuron_input0, // Input 0 for all neurons on the current layer\n    output reg [7:0] neuron_input1, // Input 1 for all neurons on the current layer\n    output reg [7:0] neuron_input2, // Input 2 for all neurons on the current layer\n    output reg [7:0] neuron_input3, // Input 3 for all neurons on the current layer\n\n    // Once all layers have passed, when we feed 4 new inputs to the network, the outputs of the network\n    // will appear here, from neuron3_output to neuron0_output\n    output reg [7:0] network_outputs\n);\n\n\n\n\nalways@(posedge clk)\nbegin\n\n    if(rstn) \n    begin\n        neuron_input0 <= 8'b00000000;\n        neuron_input1 <= 8'b00000000;\n        neuron_input2 <= 8'b00000000;\n        neuron_input3 <= 8'b00000000;\n        network_outputs <= 8'b00000000;\n    end\n\n    else\n    begin\n        case(selector)\n            2'b00   :   begin                                   // Receives new data\n                            neuron_input0 <= data_in;           // and pases it thorugh the neurons.\n                            neuron_input1 <= neuron_input0;\n                            neuron_input2 <= neuron_input1;\n                            neuron_input3 <= neuron_input2;\n                            network_outputs <= neuron_input3;\n\n                        end\n            2'b01   :   begin\n                            neuron_input0 <= neuron_input0;\n                            neuron_input1 <= neuron_input1;\n                            neuron_input2 <= neuron_input2;\n                            neuron_input3 <= neuron_input3;\n                            network_outputs <= network_outputs;\n                        end\n            2'b10   :   begin\n                            neuron_input0 <= neuron0_output;\n                            neuron_input1 <= neuron1_output;\n                            neuron_input2 <= neuron2_output;\n                            network_outputs <= network_outputs;\n                        end\n            default :   begin                               // The default state keeps everything as it was\n                            neuron_input0 <= neuron_input0;\n                            neuron_input1 <= neuron_input1;\n                            neuron_input2 <= neuron_input2;\n                            neuron_input3 <= neuron_input3;\n                            network_outputs <= network_outputs;\n                        end\n\n        endcase\n    end\n/*\n    begin\n        case(selector_output)\n            2'b00   :   begin  \n                            network_outputs <= neuron_input0;\n            end \n            2'b01   :   begin  \n                            network_outputs <= neuron_input1;\n            end \n            2'b10   :   begin  \n                            network_outputs <= neuron_input2;\n            end \n            2'b11   :   begin  \n                            network_outputs <= neuron_input3;\n            end \n            default: begin\n                    network_outputs <= network_outputs;\n            end\n        endcase\n    end\n    */\nend\n\nendmodule\n\n\nmodule tt_um_neural_network (\n    input wire clk,\n    input wire rst_n,\n    input wire [7:0] uio_in,\n    input wire [7:0] ui_in,\n    \n    output wire [7:0] uo_out,\n    output wire [7:0] uio_oe,\n    output wire [7:0] uio_out,\n\n    input wire ena\n);\nassign uio_oe = 0;\nassign uio_out = 0;    \n// Señales internas\nwire [1:0] state;\nwire [7:0] neuron_input0, neuron_input1, neuron_input2, neuron_input3;\nwire [7:0] neuron0_output, neuron1_output, neuron2_output, neuron3_output;\nwire [7:0] w00, w01, w02, w03, b0;\nwire [7:0] w10, w11, w12, w13, b1;\nwire [7:0] w20, w21, w22, w23, b2;\nwire [7:0] w30, w31, w32, w33, b3;\n\n// Instanciando los módulos\nmachine machine_inst (\n    .clk(clk),\n    .reset(~rst_n),\n    .changes(uio_in[1]),\n    .state(state),\n    .finished(uio_in[0])\n);\n\nshift_register_inputs shift_reg_inst (\n    .clk(clk),\n    .rstn(~rst_n),\n    .data_in(ui_in),\n    .selector(state),\n    //.selector_output(uio_in[1:0]),\n    .neuron0_output(neuron0_output),\n    .neuron1_output(neuron1_output),\n    .neuron2_output(neuron2_output),\n    .neuron3_output(neuron3_output),\n    .neuron_input0(neuron_input0),\n    .neuron_input1(neuron_input1),\n    .neuron_input2(neuron_input2),\n    .neuron_input3(neuron_input3),\n    .network_outputs(uo_out)\n);\n\nperceptron perceptron0 (\n    .in0(neuron_input0),\n    .in1(neuron_input1),\n    .in2(neuron_input2),\n    .in3(neuron_input3),\n    .weight0(w00),\n    .weight1(w01),\n    .weight2(w02),\n    .weight3(w03),\n    .bias(b0),\n    .threshold(8'd0),\n    .out(neuron0_output)\n);\n\nperceptron perceptron1 (\n    .in0(neuron_input0),\n    .in1(neuron_input1),\n    .in2(neuron_input2),\n    .in3(neuron_input3),\n    .weight0(w10),\n    .weight1(w11),\n    .weight2(w12),\n    .weight3(w13),\n    .bias(b1),\n    .threshold(8'd0),\n    .out(neuron1_output)\n);\n\nperceptron perceptron2 (\n    .in0(neuron_input0),\n    .in1(neuron_input1),\n    .in2(neuron_input2),\n    .in3(neuron_input3),\n    .weight0(w20),\n    .weight1(w21),\n    .weight2(w22),\n    .weight3(w23),\n    .bias(b2),\n    .threshold(8'd0),\n    .out(neuron2_output)\n);\n\nperceptron perceptron3 (\n    .in0(neuron_input0),\n    .in1(neuron_input1),\n    .in2(neuron_input2),\n    .in3(neuron_input3),\n    .weight0(w30),\n    .weight1(w31),\n    .weight2(w32),\n    .weight3(w33),\n    .bias(b3),\n    .threshold(8'd0),\n    .out(neuron3_output)\n);\n\nregister_parameters reg_params_inst (\n    .clk(clk),\n    .reset(~rst_n),\n    .data_in(ui_in),\n    .selector(state),\n    //.th3(th3),\n    .b3(b3),\n    .w33(w33),\n    .w32(w32),\n    .w31(w31),\n    .w30(w30),\n    //.th2(th2),\n    .b2(b2),\n    .w23(w23),\n    .w22(w22),\n    .w21(w21),\n    .w20(w20),\n    //.th1(th1),\n    .b1(b1),\n    .w13(w13),\n    .w12(w12),\n    .w11(w11),\n    .w10(w10),\n    //.th0(th0),\n    .b0(b0),\n    .w03(w03),\n    .w02(w02),\n    .w01(w01),\n    .w00(w00)\n);\n\nendmodule\n", "mask_idx": {"conditional_statement": [[1726, 1794], [350, 446], [2602, 6705]], "blocking_assignment": [[1622, 1692], [475, 502], [951, 997], [594, 623], [1746, 1764]], "module_program_interface_instantiation": [[12090, 12355], [11823, 12088], [11218, 11347]], "always_construct": [[2570, 6709], [1141, 1261], [8056, 10560], [453, 1139]], "case_statement": [[507, 1135], [3015, 6697], [8336, 9931]], "ansi_port_declaration": [[1864, 1881], [10804, 10818], [6771, 6776]], "continuous_assign": [[10841, 10864], [10822, 10840]], "parameter_declaration": [[172, 206], [207, 240], [139, 171]], "nonblocking_assignment": [[4779, 4787], [2668, 2678], [2911, 2921], [2744, 2754], [2926, 2936]]}, "all_mask_idx": {"module_program_interface_instantiation": [[11218, 11347], [11349, 11821], [11823, 12088], [12090, 12355], [12357, 12622], [12624, 12889], [12891, 13368]], "continuous_assign": [[10822, 10840], [10841, 10864]], "blocking_assignment": [[475, 502], [594, 623], [720, 748], [844, 873], [951, 997], [1078, 1103], [1622, 1692], [1697, 1721], [1746, 1764], [1782, 1794]], "nonblocking_assignment": [[369, 400], [418, 446], [1192, 1215], [1233, 1256], [2623, 2633], [2638, 2648], [2653, 2663], [2668, 2678], [2683, 2692], [2714, 2724], [2729, 2739], [2744, 2754], [2759, 2769], [2774, 2783], [2805, 2815], [2820, 2830], [2835, 2845], [2850, 2860], [2865, 2874], [2896, 2906], [2911, 2921], [2926, 2936], [2941, 2951], [2956, 2965], [3085, 3094], [3119, 3128], [3153, 3162], [3187, 3196], [3221, 3228], [3289, 3298], [3323, 3332], [3357, 3366], [3391, 3400], [3425, 3432], [3493, 3502], [3527, 3536], [3561, 3570], [3595, 3604], [3629, 3636], [3697, 3706], [3731, 3740], [3765, 3774], [3799, 3808], [3833, 3840], [3960, 3969], [3994, 4003], [4028, 4037], [4062, 4070], [4130, 4138], [4199, 4208], [4233, 4242], [4267, 4276], [4301, 4309], [4369, 4377], [4438, 4447], [4472, 4481], [4506, 4515], [4540, 4548], [4608, 4616], [4677, 4686], [4711, 4720], [4745, 4754], [4779, 4787], [4847, 4859], [4983, 4992], [5017, 5026], [5051, 5060], [5085, 5094], [5119, 5126], [5187, 5196], [5221, 5230], [5255, 5264], [5289, 5298], [5323, 5330], [5391, 5400], [5425, 5434], [5459, 5468], [5493, 5502], [5527, 5534], [5595, 5604], [5629, 5638], [5663, 5672], [5697, 5706], [5731, 5738], [5858, 5867], [5892, 5901], [5926, 5935], [5960, 5969], [5994, 6001], [6062, 6071], [6096, 6105], [6130, 6139], [6164, 6173], [6198, 6205], [6266, 6275], [6300, 6309], [6334, 6343], [6368, 6377], [6402, 6409], [6470, 6479], [6504, 6513], [6538, 6547], [6572, 6581], [6606, 6613], [8116, 8145], [8154, 8183], [8192, 8221], [8230, 8259], [8268, 8299], [8464, 8536], [8565, 8596], [8625, 8656], [8685, 8716], [8745, 8778], [8866, 8897], [8926, 8957], [8986, 9017], [9046, 9077], [9106, 9141], [9228, 9260], [9289, 9321], [9350, 9382], [9411, 9446], [9611, 9642], [9671, 9702], [9731, 9762], [9791, 9822], [9851, 9886]], "case_statement": [[507, 1135], [3015, 6697], [8336, 9931]], "conditional_statement": [[350, 446], [551, 651], [677, 776], [801, 1025], [907, 1025], [1043, 1123], [1173, 1256], [1726, 1794], [2602, 6705], [8088, 9939]], "always_construct": [[318, 451], [453, 1139], [1141, 1261], [1596, 1798], [2570, 6709], [8056, 10560]], "parameter_declaration": [[139, 171], [172, 206], [207, 240]], "ansi_port_declaration": [[21, 36], [41, 58], [63, 82], [87, 107], [112, 134], [1297, 1313], [1318, 1334], [1339, 1355], [1360, 1376], [1382, 1408], [1413, 1433], [1438, 1458], [1463, 1483], [1488, 1505], [1510, 1532], [1538, 1558], [1844, 1859], [1864, 1881], [1886, 1911], [1916, 1937], [1971, 1991], [1996, 2017], [2022, 2043], [2048, 2069], [2074, 2095], [2128, 2148], [2153, 2174], [2179, 2200], [2205, 2226], [2231, 2252], [2285, 2305], [2310, 2331], [2336, 2357], [2362, 2383], [2388, 2409], [2442, 2462], [2467, 2488], [2493, 2514], [2519, 2540], [2545, 2565], [6761, 6776], [6771, 6776], [6781, 6801], [6806, 6903], [7067, 7159], [7164, 7255], [7260, 7351], [7356, 7447], [7511, 7590], [7595, 7674], [7679, 7758], [7763, 7842], [8016, 8048], [10608, 10623], [10628, 10645], [10650, 10674], [10679, 10702], [10712, 10737], [10742, 10767], [10772, 10798], [10804, 10818]]}}
{"sample_i": "KosugiSubaru-tt07-td4cpu", "topmodule": "tt_um_TD4_Assy_KosugiSubaru", "code": "module tt_um_TD4_Assy_KosugiSubaru (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // will go high when the design is enabled\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\nwire [7:0] data;\nwire [3:0] port_i, port_o, addres, ALU_to_reg, sel_to_ALU, regA_to_sel, regB_to_sel, load, op, im;\nwire [1:0] select;\nwire carry, cf, co_from_pc;\n\nreg [3:0] uio_oe_reg;\n\nassign uio_oe [4] = 1'b0;\nassign uio_out [4] = 1'b0;\nassign uio_oe [7:5] = 3'b111;\nassign uio_oe [3:0] = uio_oe_reg [3:0];\n\nassign port_i [3:0] = uio_in [3:0];\nassign uio_out [3:0] = port_o [3:0];\n\nassign uo_out [3:0] = addres[3:0];\nassign data [7:0] = ui_in [7:0];\nassign op = data[7:4], im = data[3:0];\n\nassign uo_out [4] = cf;\nassign uo_out [7:5] = ALU_to_reg [2:0];\nassign uio_out [5] = ALU_to_reg [3];\nassign uio_out [7:6] = select [1:0];\n\nalways @(uio_in [4]) begin\n    if (uio_in [4] == 1'b0) begin\n        uio_oe_reg [3:0] <= 4'b0000;\n    end else if (uio_in [4] == 1'b1) begin\n        uio_oe_reg [3:0] <= 4'b1111;\n    end\nend\n\nregister_ff_4bit reg_A (.in(ALU_to_reg), .out(regA_to_sel), .ld(~load [0]), .clk(clk), .rst(rst_n));\nregister_ff_4bit reg_B (.in(ALU_to_reg), .out(regB_to_sel), .ld(~load[1]), .clk(clk), .rst(rst_n));\nregister_ff_4bit OUT   (.in(ALU_to_reg), .out(port_o), .ld(~load [2]), .clk(clk), .rst(rst_n));\n\nALU_adder_4bit ALU0    (.in_a(sel_to_ALU), .in_b(im), .out(ALU_to_reg), .ci(1'b0), .co(carry));\n\npc       pc0  (.in(ALU_to_reg), .out(addres), .ld(~load [3]), .clk(clk), .rst(rst_n), .co(co_from_pc));\n\ndecoder  dec0 (.op(op), .c_n(~cf), .s(select), .ld_n(load));\n\nselector sel0 (.in_a(regA_to_sel), .in_b(regB_to_sel), .in_c(port_i), .in_d(4'b0000), .s(select), .out(sel_to_ALU));\n\nff_1bit  cf0  (.in(carry), .out(cf), .clk(clk), .rst(rst_n), .pr(1'b1));\n\nendmodule\n\n\nmodule register_ff_4bit(in, out, ld, clk, rst);\n    input [3:0] in;\n    input ld, clk, rst;\n    output [3:0] out;\n\n    reg [3:0] out;\n    always @(posedge clk or negedge rst) begin\n        if (rst ==1'b0) begin\n            out <= 4'b0000;\n        end else begin \n            if (ld == 1'b1) begin\n                out <= in;\n            end else if (ld == 1'b0) begin\n                out <= out;\n            end\n        end\n    end\nendmodule\n\nmodule ff_1bit(in, out, clk, rst, pr);\n    input in;\n    input clk, rst, pr;\n    output out;\n\n    reg out;\n    always @(posedge clk or negedge rst) begin\n        if (rst == 1'b0) begin\n            out <= 0;\n        end else begin\n            if (pr == 1'b0) begin\n                out <= 1;\n            end else begin\n                out <= in;\n            end\n        end\n    end\nendmodule\n\nmodule pc(in, out, ld, clk, rst, co);\n    input [3:0] in;\n    input ld, clk, rst;\n    output [3:0] out;\n    output co;\n\n    reg [3:0] out;\n    reg co;\n    always @(posedge clk or negedge rst) begin\n        if (rst == 1'b0) begin\n            out <= 4'b0000;\n            co <= 1'b0;\n        end else if (out == 4'b1111) begin\n            co <= 1'b1;\n        end else begin\n            if (ld == 1'b1) begin\n                out <= in;\n            end else if (ld == 1'b0) begin\n                out <= out + 4'b0001;\n            end\n        end\n    end\nendmodule\n\nmodule ALU_adder_4bit(in_a, in_b, out, ci, co);\n    input [3:0] in_a, in_b;\n    input ci;\n    output [3:0] out;\n    output co;\n\n    reg [3:0] out;\n    reg co;\n    always @(in_a or in_b or ci) begin\n        {co, out} <= in_a + in_b + ci;\n    end\nendmodule\n\nmodule decoder(op, c_n, s, ld_n);\n    input [3:0] op;\n    input c_n;\n    output [1:0] s;\n    output [3:0] ld_n;\n\n    reg [1:0] s;\n    reg [3:0] ld_n;\n    always @(op or c_n) begin\n        s [1] <= op[1];\n        s [0] <= op[0] | op[3];\n        ld_n[0] <= op[2] | op[3];\n        ld_n[1] <= op[3] | ~(op[2] & 1 & 1);\n        ld_n[2] <= ~(1 & ~(op[2] & 1 & 1) & op[3]);\n        ld_n[3] <= ~(op[2] & op[3] & (op[0] | c_n));\n    end\nendmodule\n\nmodule selector(in_a, in_b, in_c, in_d, s, out);\n    input [3:0] in_a, in_b, in_c, in_d;\n    input [1:0] s;\n    output [3:0] out;\n\n    reg [3:0] out; \n    always @(in_a or in_b or in_c or in_d or s) begin\n        case (s)\n            2'b00: out <= in_a;\n            2'b01: out <= in_b;\n            2'b10: out <= in_c;\n            2'b11: out <= in_d;\n            default: out <= 4'bxxxx;\n        endcase\n    end\nendmodule\n", "mask_idx": {"conditional_statement": [[2701, 2910], [3228, 3470], [2286, 2519]], "module_program_interface_instantiation": [[1532, 1627], [2011, 2083], [1726, 1829], [1831, 1891]], "always_construct": [[1140, 1329], [3085, 3478], [3900, 4173], [4340, 4595]], "case_statement": [[4398, 4587]], "ansi_port_declaration": [[2568, 2577], [2958, 2967], [4219, 4233], [2949, 2967]], "continuous_assign": [[1025, 1064], [1102, 1138], [819, 854]], "nonblocking_assignment": [[4490, 4502], [4069, 4112], [3696, 3726]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1331, 1431], [1432, 1531], [1532, 1627], [1629, 1724], [1726, 1829], [1831, 1891], [1893, 2009], [2011, 2083]], "continuous_assign": [[695, 720], [721, 747], [748, 777], [778, 817], [819, 854], [855, 891], [893, 927], [928, 960], [961, 999], [1001, 1024], [1025, 1064], [1065, 1101], [1102, 1138]], "blocking_assignment": [], "nonblocking_assignment": [[1209, 1237], [1289, 1317], [2320, 2335], [2410, 2420], [2480, 2491], [2736, 2745], [2819, 2828], [2872, 2882], [3171, 3186], [3199, 3210], [3266, 3277], [3351, 3361], [3421, 3442], [3696, 3726], [3934, 3949], [3958, 3981], [3990, 4015], [4024, 4060], [4069, 4112], [4121, 4165], [4426, 4438], [4458, 4470], [4490, 4502], [4522, 4534], [4556, 4571]], "case_statement": [[4398, 4587]], "conditional_statement": [[1171, 1325], [1251, 1325], [2286, 2519], [2372, 2507], [2442, 2507], [2701, 2910], [2781, 2898], [3136, 3470], [3228, 3470], [3313, 3458], [3383, 3458]], "always_construct": [[1140, 1329], [2235, 2527], [2650, 2918], [3085, 3478], [3653, 3734], [3900, 4173], [4340, 4595]], "parameter_declaration": [], "ansi_port_declaration": [[41, 88], [93, 141], [146, 192], [197, 244], [249, 329], [334, 404], [409, 445], [450, 503], [2121, 2144], [2125, 2144], [2130, 2144], [2134, 2144], [2139, 2144], [2554, 2577], [2558, 2577], [2563, 2577], [2568, 2577], [2573, 2577], [2940, 2967], [2944, 2967], [2949, 2967], [2953, 2967], [2958, 2967], [2963, 2967], [3512, 3537], [3518, 3537], [3524, 3537], [3529, 3537], [3533, 3537], [3761, 3779], [3765, 3779], [3770, 3779], [3773, 3779], [4201, 4233], [4207, 4233], [4213, 4233], [4219, 4233], [4225, 4233], [4228, 4233]]}}
{"sample_i": "NelsonSalvadorPinilla-tt07-PS_PWM_Modulator", "topmodule": "tt_um_PS_PWM", "code": "`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Design Name: Top \n// Module Name: Top\n// Project Name: TT05 Modulacion PS-PWM para 3L-FCC\n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule tt_um_PS_PWM(\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // will go high when the design is enabled\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n    \n    assign uio_oe = 8'b00000000; //todos input\n    assign uio_out = 8'b00000000;\n\n/**************** Conexiones ****************/   \n\n    wire RST;\n    assign RST= ~rst_n;\n\n    wire [5:0] d1;\n    wire [5:0] d2;\n    assign d1 = ui_in[5:0];\n    assign d2 = {ui_in[7:6], uio_in[3:0]};\n\n    wire CLK_SR;\n    wire Data_SR;\n    assign CLK_SR = uio_in[4];\n    assign Data_SR = uio_in[5];\n\n    wire CLK_INT;\n    wire CLK_EXT;\n    assign CLK_INT= clk;\n    assign CLK_EXT= uio_in[6];\n\n    wire PMOS1;      // Senal de control del transistor PMOS 1 \n    wire NMOS2;      // Senal de control del transistor NMOS 2 \n    wire PMOS2;     // Senal de control del transistor PMOS 2 \n    wire NMOS1;      // Senal de control del transistor NMOS 1 \n    wire CLK_OUTPUT;\n\n    \n/**************** ETAPA DE SHIFT REGISTER ****************/\nwire CLK_SELECTOR;\nwire [4:0] dt;\nwire [1:0] SELECTOR_SIGNAL_GENERATOR_1; // escoge el desfase que tendra la triangular 1\nwire [1:0] SELECTOR_SIGNAL_GENERATOR_2; // escoge el desfase que tendra la triangular 2\nwire ENABLE_OUTPUT;\n\nShift_Register Shift_Register_Inst(\n    CLK_SR,\n    RST,\n    Data_SR,\n    {ENABLE_OUTPUT, CLK_SELECTOR, SELECTOR_SIGNAL_GENERATOR_2[1],SELECTOR_SIGNAL_GENERATOR_2[0],SELECTOR_SIGNAL_GENERATOR_1[1],SELECTOR_SIGNAL_GENERATOR_1[0], dt[4], dt[3], dt[2], dt[1], dt[0]}\n);\n\n// El orden para meter los datos es (de primero a ultimo): \n// dt[0]\n// dt[1]\n// dt[2]\n// dt[3]\n// dt[4]\n// SELECTOR_SIGNAL_GENERATOR_1[0]\n// SELECTOR_SIGNAL_GENERATOR_1[1]\n// SELECTOR_SIGNAL_GENERATOR_2[0]\n// SELECTOR_SIGNAL_GENERATOR_2[1]\n// CLK_SELECTOR\n// ENABLE_OUTPUT\n\n/**************** ETAPA DE MUX CLK ****************/\n\nwire clk_in;\n\n// Si CLK_SELECTOR es 0 -> se usa clk del PLL, si es 1 -> se usa el clk del pin externo\nassign clk_in = CLK_SELECTOR ? CLK_EXT : CLK_INT;\nassign CLK_OUTPUT= clk;\n\n/**************** ETAPA DE TRIANGULARES ****************/\n\n// Fases de la triangular 1\nwire [5:0] triangular_1_0;\nSignal_Generator_0phase Signal_Generator_1_0phase_inst(\n    clk_in,\n    RST,\n    triangular_1_0\n);\n\nwire [5:0] triangular_1_90;\nSignal_Generator_90phase Signal_Generator_1_90phase_inst(\n    clk_in,\n    RST,\n    triangular_1_90\n);\n\nwire [5:0] triangular_1_180;\nSignal_Generator_180phase Signal_Generator_1_180phase_inst(\n    clk_in,\n    RST,\n    triangular_1_180\n);\n\nwire [5:0] triangular_1_270;\nSignal_Generator_270phase Signal_Generator_1_270phase_inst(\n    clk_in,\n    RST,\n    triangular_1_270\n);\n\n// Fases de la triangular 2\nwire [5:0] triangular_2_0;\nSignal_Generator_0phase Signal_Generator_2_0phase_inst(\n    clk_in,\n    RST,\n    triangular_2_0\n);\n\nwire [5:0] triangular_2_90;\nSignal_Generator_90phase Signal_Generator_2_90phase_inst(\n    clk_in,\n    RST,\n    triangular_2_90\n);\n\nwire [5:0] triangular_2_180;\nSignal_Generator_180phase Signal_Generator_2_180phase_inst(\n    clk_in,\n    RST,\n    triangular_2_180\n);\n\nwire [5:0] triangular_2_270;\nSignal_Generator_270phase Signal_Generator_2_270phase_inst(\n    clk_in,\n    RST,\n    triangular_2_270\n);\n\n/**************** ETAPA DE MUX Triangulares ****************/\n\n// Triangular 1\nreg [5:0] triangular_1;\nalways @(*) begin\n\n    // SELECTOR_SIGNAL_GENERATOR_2 selecciona la fase de la triangular_1\n    case(SELECTOR_SIGNAL_GENERATOR_1)           \n           2'd0  : triangular_1 = triangular_1_0;\n           2'd1  : triangular_1 = triangular_1_90;\n           2'd2  : triangular_1 = triangular_1_180;\n           2'd3  : triangular_1 = triangular_1_270;\n           default : triangular_1 = 0;\n       endcase\n\nend\n\n// Triangular 2\nreg [5:0] triangular_2;\nalways @(*) begin\n\n    // SELECTOR_SIGNAL_GENERATOR_2 selecciona la fase de la triangular_2\n    case(SELECTOR_SIGNAL_GENERATOR_2)           \n           2'd0  : triangular_2 = triangular_2_0;\n           2'd1  : triangular_2 = triangular_2_90;\n           2'd2  : triangular_2 = triangular_2_180;\n           2'd3  : triangular_2 = triangular_2_270;\n           default : triangular_2 = 0;\n       endcase\n\nend\n\n/**************** ETAPA DE COMPARACION ****************/\n\nwire Output_Comparison_1;\nComparator Comparator_Inst_1(\n    d1,\n    triangular_1,\n    Output_Comparison_1\n);\n\nwire Output_Comparison_2;\nComparator Comparator_Inst_2(\n    d2,\n    triangular_2,\n    Output_Comparison_2\n);\n\n/**************** ETAPA DE DEAD-TIME GENERATOR ****************/\n\nwire pmos1_int; \nDead_Time_Generator Dead_Time_Generator_inst_1(\n    clk_in,\n    dt,\n    Output_Comparison_1,\n    pmos1_int\n);\n\nwire Not_Output_Comparison_1;\nwire nmos2_int;\nassign Not_Output_Comparison_1 = ~Output_Comparison_1;\nDead_Time_Generator Dead_Time_Generator_inst_2(\n    clk_in,\n    dt,\n    Not_Output_Comparison_1,\n    nmos2_int\n);\n\nwire pmos2_int;\nDead_Time_Generator Dead_Time_Generator_inst_3(\n    clk_in,\n    dt,\n    Output_Comparison_2,\n    pmos2_int\n);\n\nwire Not_Output_Comparison_2;\nwire nmos1_int;\nassign Not_Output_Comparison_2 = ~Output_Comparison_2;\nDead_Time_Generator Dead_Time_Generator_inst_4(\n    clk_in,\n    dt,\n    Not_Output_Comparison_2,\n    nmos1_int\n);\n\n/**************** ETAPA DE MUX OUTPUT INTERNA ****************/\n\nwire PMOS1_prev, NMOS2_prev, PMOS2_prev, NMOS1_prev;\n\n// Si OUTPUT_SELECTOR_INTERNAL es 0 -> salidas vienen del modulador , si es 1 -> vienen offchip\nassign PMOS1_prev = ~pmos1_int; // TIENE EL NEGADOR POR EL PMOS\nassign NMOS2_prev = nmos2_int;\nassign PMOS2_prev = ~pmos2_int; // TIENE EL NEGADOR POR EL PMOS\nassign NMOS1_prev = nmos1_int;\n\n/**************** ETAPA ENABLE OUTPUTs ****************/\n\n// Si ENABLE_OUTPUT es 0 -> los 4 transistores cmos estan en corte, si es 1 -> las salidas de los 4 cmos viene dada segun su logica previa, \nassign PMOS1 = ENABLE_OUTPUT ? PMOS1_prev : 1; \nassign NMOS2 = ENABLE_OUTPUT ? NMOS2_prev : 0;\nassign PMOS2 = ENABLE_OUTPUT ? PMOS2_prev : 1;\nassign NMOS1 = ENABLE_OUTPUT ? NMOS1_prev : 0;\n\n    assign uo_out[0]= PMOS1;\n    assign uo_out[1]= NMOS2;\n    assign uo_out[2]= PMOS2;\n    assign uo_out[3]= NMOS1;\n    assign uo_out[4]= clk_in;\n    assign uo_out[7:5]= 3'b000;\n\nendmodule\n\n\nmodule Comparator(in1, in2, comparison);\n  parameter WIDTH_IN1 = 6;\n  parameter WIDTH_IN2 = 6;\n\n  input [WIDTH_IN1-1:0] in1;\n  input [WIDTH_IN2-1:0] in2;\n  output comparison;\n  reg comparison;\n \n  always @ (in1 or in2)\n  begin\n      comparison = (in1 >= in2);\n  end\nendmodule\n\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: POWERLAB, DEPARTAMENTO DE ELECTRONICA, UTFSM\n// Engineer: GONZALO CARRASCO REYES\n//\n// Create Date:    12:24:55 10/09/2007\n// Design Name:\n// Module Name:    Dead_Time_Geneartr\n// Project Name:\n// Target Devices:\n// Tool versions:\n// Description:\tEl modulo recibe una senal digital de 1 bit, y entrega la misma\n//\t\t\t\t\t\tsenal de entrada con un retardo en el canto de subida. Este\n//\t\t\t\t\t\tretardo llamado tiempo muerto, es configurable con una palabra\n//\t\t\t\t\t\tde 10 bits, que permite fijar tiempos en pasos de un periodo del \n//\t\t\t\t\t\treloj del reloj de 150MHz, que tambien debe recibir.\n//\n// Dependencies:\tDepende de una senal de reloj, la configuracion del tiempo\n//\t\t\t\t\t\tmuerto y de la senal de entrada.\n//\t\t\t\t\t\t\tclk\t- Entrada de 150MHz\n//\t\t\t\t\t\t\tdt\t\t- Tiempo muerto\n//\t\t\t\t\t\t\tgi\t\t- Senal de entrada\n//\n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule Dead_Time_Generator(clk, dt, gi, go);\n\n\t(* clock_signal = \"yes\" *)\n\tinput               \tclk;        //Reloj principal de 150MHz\n\tinput   \t[4:0]   \tdt;         //Configuracion de tiempos muertos\n\tinput               \tgi;         //Senal a retardar (tiempo muerto)\n\toutput reg          \tgo;         //Senal retardada (tiempo muerto)\n\t//----------------------------------------------------------------------------\n\t//Variables internas\n\twire             \t\tdt_end;    \t//Senal de fin del tiempo muerto\n\treg     [4:0]       \tcount_dt;   //Contador para el tiempo  muerto\n\t///////////////////////////////////////////////////////////////////////////////\n\t\n\t//Comparacion asincronica de el contador de tiempo muerto\n\tassign dt_end = ( count_dt >= dt ) ? 1 : 0;\n\t\n\t//Conteo para retardar el canto de subida, tiempo muerto\n\talways @(posedge clk) begin\n\t  if (gi == 0)\n\t\t\tcount_dt = 0;\n\t  else\n\t\t\tif (!dt_end)\n\t\t\t\t count_dt = count_dt + 1;\n\tend\n\t\n\t//----------------------------------------------------------------------------\n\t//Generacion de senal de salida\n\talways @(posedge clk)begin\n\t  if (gi == 0)\n\t\t\tgo = 0;\n\t  else\n\t\t\tif (dt_end)\n\t\t\t\t go = 1;\n\t\t\telse\n\t\t\t\t go = 0;\n\tend\n\t///////////////////////////////////////////////////////////////////////////////\nendmodule\n\n\n`timescale 1ns / 1ps\n\nmodule Shift_Register(\n  input wire CLK_SR,\n  input wire RST,\n  input wire data_in,\n  output wire [10:0] data_out\n);\n\n  reg [10:0] internal_data [0:10];\n  reg [3:0] shift_state;\n  integer i;\n  \n  always @(posedge CLK_SR or posedge RST) begin\n    if (RST) begin\n      // Reiniciar todas las variables internas a 0 cuando se activa el reset\n      for (i = 0; i < 5'd11; i = i + 1) begin\n        internal_data[i] <= 0;\n      end\n      shift_state <= 0;\n    end else \n        if (shift_state < 5'd11) begin\n          // Almacenar el valor de entrada en la variable interna correspondiente\n          internal_data[shift_state] <= data_in;\n          // Cambiar al siguiente estado del registro\n          shift_state <= shift_state + 1;\n        end\nend\nassign data_out[0] = internal_data[0]; // dt[0]\nassign data_out[1] = internal_data[1]; // dt[1]\nassign data_out[2] = internal_data[2]; // dt[2]\nassign data_out[3] = internal_data[3]; // dt[3] \nassign data_out[4] = internal_data[4]; // dt[4] \nassign data_out[5] = internal_data[5]; // SELECTOR_SIGNAL_GENERATOR_1[0]\nassign data_out[6] = internal_data[6]; // SELECTOR_SIGNAL_GENERATOR_1[1]\nassign data_out[7] = internal_data[7]; // SELECTOR_SIGNAL_GENERATOR_2[0]\nassign data_out[8] = internal_data[8]; // SELECTOR_SIGNAL_GENERATOR_2[1]\nassign data_out[9] = internal_data[9]; // OUTPUT_SELECTOR_EXTERNAL[0]\nassign data_out[10] = internal_data[10]; // OUTPUT_SELECTOR_EXTERNAL[1]\n\n \n\n\nendmodule\n\n\n`timescale 1ns / 1ps\n\nmodule Signal_Generator_0phase #(parameter WIDTH_TRIANG = 6)(\n    input clk,        // Reloj de entrada\n    input rst,        // Senal de reinicio\n    output reg [WIDTH_TRIANG-1:0] count // Salida triangular de 12 bits\n);\n\n//reg [WIDTH_TRIANG-1:0] count; // contador de 12 bits\nreg direction;\n\nalways @(posedge clk or posedge rst) begin\n    if (rst) begin\n        count <= 0;\n        direction <= 1;\n    end\n    else begin\n        if (direction) begin\n            if (count == 6'b111111) begin // 64 en binario\n                direction <= 0;\n                count <= 6'b111110 ; end \n            else\n                count <= count + 1;\n        end\n        else begin\n            if (count == 6'b000000) begin// 0 en binario\n                direction <= 1;\n                count <= 6'b000001; end\n            else\n                count <= count - 1;\n        end\n    end\nend\n\n//assign triangular_out = count;\n\nendmodule\n\n\n`timescale 1ns / 1ps\n\nmodule Signal_Generator_90phase #(parameter WIDTH_TRIANG = 6)(\n    input clk,        // Reloj de entrada\n    input rst,        // Senal de reinicio\n    output reg [WIDTH_TRIANG-1:0] count // Salida triangular de 12 bits\n);\n\n//reg [WIDTH_TRIANG-1:0] count; // contador de 12 bits\nreg direction;\n\nalways @(posedge clk or posedge rst) begin\n    if (rst) begin\n        count <= 6'b00011111;\n        direction <= 1;\n    end\n    else begin\n        if (direction) begin\n            if (count == 6'b111111) begin // 4095 en binario\n                direction <= 0;\n                count <= 6'b111110 ; end \n            else\n                count <= count + 1;\n        end\n        else begin\n            if (count == 6'b000000) begin// 0 en binario\n                direction <= 1;\n                count <= 6'b000001; end\n            else\n                count <= count - 1;\n        end\n    end\nend\n\n//assign triangular_out = count;\n\nendmodule\n\n\n`timescale 1ns / 1ps\n\nmodule Signal_Generator_180phase #(parameter WIDTH_TRIANG = 6)(\n    input clk,        // Reloj de entrada\n    input rst,        // Senal de reinicio\n    output reg [WIDTH_TRIANG-1:0] count // Salida triangular de 12 bits\n);\n\n//reg [WIDTH_TRIANG-1:0] count; // contador de 12 bits\nreg direction;\n\nalways @(posedge clk or posedge rst) begin\n    if (rst) begin\n        count <= 6'b111111;\n        direction <= 1;\n    end\n    else begin\n        if (direction) begin\n            if (count == 6'b111111) begin // 4095 en binario\n                direction <= 0;\n                count <= 6'b111110 ; end \n            else\n                count <= count + 1;\n        end\n        else begin\n            if (count == 6'b000000) begin// 0 en binario\n                direction <= 1;\n                count <= 6'b000001; end\n            else\n                count <= count - 1;\n        end\n    end\nend\n\n//assign triangular_out = count;\n\nendmodule\n\n\n`timescale 1ns / 1ps\n\nmodule Signal_Generator_270phase #(parameter WIDTH_TRIANG = 6)(\n    input clk,        // Reloj de entrada\n    input rst,        // Senal de reinicio\n    output reg [WIDTH_TRIANG-1:0] count // Salida triangular de 12 bits\n);\n\n//reg [WIDTH_TRIANG-1:0] count; // contador de 12 bits\nreg direction;\n\nalways @(posedge clk or posedge rst) begin\n    if (rst) begin\n        count <= 6'b00100000;\n        direction <= 0;\n    end\n    else begin\n        if (direction) begin\n            if (count == 6'b111111) begin // 4095 en binario\n                direction <= 0;\n                count <= 6'b111110 ; end \n            else\n                count <= count + 1;\n        end\n        else begin\n            if (count == 6'b000000) begin// 0 en binario\n                direction <= 1;\n                count <= 6'b000001; end\n            else\n                count <= count - 1;\n        end\n    end\nend\n\n//assign triangular_out = count;\n\nendmodule\n", "mask_idx": {"conditional_statement": [[11274, 11705], [9628, 10123], [12481, 12650], [13218, 13393], [12129, 12670]], "blocking_assignment": [[8962, 8975], [4633, 4665], [6976, 7002], [4034, 4064], [4687, 4704], [4241, 4258]], "module_program_interface_instantiation": [[2842, 2943], [3530, 3634], [3665, 3769], [5430, 5539], [5299, 5412], [3270, 3368]], "always_construct": [[12082, 12674], [13996, 14588], [6940, 7008], [11137, 11717], [9151, 9266]], "case_statement": [[3970, 4273], [4416, 4719]], "ansi_port_declaration": [[10951, 10989], [463, 510], [12812, 12849]], "continuous_assign": [[10732, 10803], [1225, 1251], [2575, 2598], [6504, 6550]], "parameter_declaration": [[12779, 12807], [10876, 10904], [6813, 6837], [6786, 6810], [11821, 11849], [13735, 13763]], "nonblocking_assignment": [[12359, 12384], [14332, 14351], [11461, 11480]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1826, 2092], [2714, 2812], [2842, 2943], [2974, 3078], [3109, 3213], [3270, 3368], [3398, 3499], [3530, 3634], [3665, 3769], [4810, 4892], [4920, 5002], [5087, 5196], [5299, 5412], [5430, 5539], [5642, 5755]], "continuous_assign": [[783, 825], [830, 859], [930, 949], [993, 1016], [1021, 1059], [1100, 1126], [1131, 1158], [1200, 1220], [1225, 1251], [2525, 2574], [2575, 2598], [5244, 5298], [5587, 5641], [5972, 6035], [6036, 6066], [6067, 6130], [6131, 6161], [6362, 6409], [6410, 6456], [6457, 6503], [6504, 6550], [6556, 6580], [6585, 6609], [6614, 6638], [6643, 6667], [6672, 6697], [6702, 6729], [8810, 8853], [10128, 10175], [10176, 10223], [10224, 10271], [10272, 10320], [10321, 10369], [10370, 10442], [10443, 10515], [10516, 10588], [10589, 10661], [10662, 10731], [10732, 10803]], "blocking_assignment": [[4034, 4064], [4084, 4115], [4135, 4167], [4187, 4219], [4241, 4258], [4480, 4510], [4530, 4561], [4581, 4613], [4633, 4665], [4687, 4704], [6976, 7002], [8962, 8975], [9005, 9029], [9197, 9204], [9233, 9240], [9254, 9261]], "nonblocking_assignment": [[9775, 9797], [9814, 9831], [9977, 10015], [10080, 10111], [11207, 11218], [11227, 11242], [11370, 11385], [11402, 11427], [11461, 11480], [11585, 11600], [11617, 11640], [11674, 11693], [12152, 12173], [12182, 12197], [12327, 12342], [12359, 12384], [12418, 12437], [12542, 12557], [12574, 12597], [12631, 12650], [13110, 13129], [13138, 13153], [13283, 13298], [13315, 13340], [13374, 13393], [13498, 13513], [13530, 13553], [13587, 13606], [14066, 14087], [14096, 14111], [14241, 14256], [14273, 14298], [14332, 14351], [14456, 14471], [14488, 14511], [14545, 14564]], "case_statement": [[3970, 4273], [4416, 4719]], "conditional_statement": [[8946, 9029], [8987, 9029], [9181, 9261], [9216, 9261], [9628, 10123], [9854, 10123], [11184, 11713], [11274, 11705], [11307, 11480], [11524, 11693], [12129, 12670], [12229, 12662], [12262, 12437], [12481, 12650], [13087, 13626], [13185, 13618], [13218, 13393], [13437, 13606], [14043, 14584], [14143, 14576], [14176, 14351], [14395, 14564]], "always_construct": [[3874, 4278], [4320, 4724], [6940, 7008], [8915, 9034], [9151, 9266], [9578, 10127], [11137, 11717], [12082, 12674], [13040, 13630], [13996, 14588]], "parameter_declaration": [[6786, 6810], [6813, 6837], [10876, 10904], [11821, 11849], [12779, 12807], [13735, 13763]], "ansi_port_declaration": [[307, 354], [359, 407], [412, 458], [463, 510], [515, 595], [600, 670], [675, 711], [716, 769], [6761, 6783], [6766, 6783], [6771, 6783], [8120, 8137], [8125, 8137], [8129, 8137], [8133, 8137], [9407, 9425], [9428, 9443], [9446, 9465], [9468, 9495], [10909, 10946], [10951, 10989], [10994, 11061], [11854, 11891], [11896, 11934], [11939, 12006], [12812, 12849], [12854, 12892], [12897, 12964], [13768, 13805], [13810, 13848], [13853, 13920]]}}
{"sample_i": "Revenantx86-tt07-tinytpu", "topmodule": "tt_um_revenantx86_tinytpu", "code": "/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_revenantx86_tinytpu \n(\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n  //\n  wire rst;\n  wire data_in_x;\n  wire data_in_y;\n  wire load_en;\n  wire init;\n  wire data_out_z;\n  wire tx_ready;\n  //\n  assign rst = ~rst_n;\n  //\n  /*\n    Assign IO\n  */\n  // Input Assign\n  assign data_in_x = ui_in[0];\n  assign data_in_y = ui_in[1];\n  assign load_en   = ui_in[2];\n  assign init      = ui_in[3];\n  // Output Assign\n  assign uo_out[0] = data_out_z;\n  assign uo_out[1] = tx_ready;\n  assign uo_out[2] = 0;\n  assign uo_out[3] = 0;\n  assign uo_out[4] = 0;\n  assign uo_out[5] = 0;\n  assign uo_out[6] = 0;\n  assign uo_out[7] = 0;\n  //\n  assign uio_oe = 8'b00;\n  assign uio_out = 8'b0;\n  //\n  tinytpu_top #(.D_W(8), .N(2), .WORD(2)) \n      tinytpu_top_inst (\n                          .clk(clk),\n                          .rst(rst),\n                          .data_in_x(data_in_x),\n                          .data_in_y(data_in_y),\n                          .load_en(load_en),\n                          .init(init),\n                          .data_out_z(data_out_z),\n                          .tx_ready(tx_ready)\n                       );\n\n\nendmodule\n\n\nmodule dff_mem #\n(\n    parameter D_W = 8, \n    parameter WORD = 8\n)\n(\n    input wire clk,\n    input wire rst,\n    // Read Logic\n    input wire rd_en,\n    input wire [$clog2(WORD)-1:0] addr,\n    // Write logic\n    input wire wr_en,\n    // IO\n    input wire [D_W-1:0] data_in,\n    output reg [D_W-1:0] data_out\n);\n//\n// Memory Array\nreg [D_W-1:0] mem [WORD-1:0];\n//\n// Write Logic\nalways @(posedge clk) begin\n    if(wr_en) begin\n        mem[addr] <= data_in;\n    end\nend\n\n// Read Logic\nalways @(*) begin\n    if(rd_en) begin\n        data_out <= mem[addr];  // Update output only if rd_en is high\n    end\n    else if(!rd_en) begin\n        data_out <= 0;  // Update output only if rd_en is high\n    end \n    else if(rst) begin\n        data_out <= 0;  // Optionally reset the output to 0 on reset\n    end\nend\n\n\nendmodule\n\nmodule input_control # \n(\n    parameter D_W = 8,\n    parameter N = 2,\n    parameter WORD = 8\n)\n(\n    input wire clk,\n    input wire rst,\n    input wire data_in_x,\n    input wire data_in_y,\n    input wire load_en,\n    input wire init,\n    output reg [(N*D_W)-1:0] out_x_flat,\n    output reg [(N*D_W)-1:0] out_y_flat,\n    output reg out_init\n);\n//\n/*\n    State Machine\n*/\n//enum {IDLE,LOAD,TRANSFER} STATE;\nlocalparam IDLE     = 2'b00;\nlocalparam LOAD     = 2'b01;\nlocalparam TRANSFER = 2'b10;\nreg [1:0] STATE;\n//\nwire [D_W-1:0] out_x [N-1:0];\nwire [D_W-1:0] out_y [N-1:0];\n/*\n    Generate Memory Block\n*/\nreg  [$clog2(WORD)-1:0] addr_x_ram     [N-1:0];\nreg                     rd_en_x_ram    [N-1:0];\nreg                     wr_en_x_ram    [N-1:0];\nreg  [D_W-1:0]          data_in_x_reg;\n//\nreg  [$clog2(WORD)-1:0] addr_y_ram     [N-1:0];\nreg                     rd_en_y_ram    [N-1:0];\nreg                     wr_en_y_ram    [N-1:0];\nreg  [D_W-1:0]          data_in_y_reg;\n//\ngenvar n;\ngenerate \n    for(n=0;n<N;n=n+1) begin\n        //Initalize memory X & Y\n        dff_mem #( .D_W(D_W), .WORD(WORD)) \n                mem_x (\n                        .clk(clk),\n                        .rst(rst),\n                        .addr(addr_x_ram[n]),\n                        .rd_en(rd_en_x_ram[n]),\n                        .wr_en(wr_en_x_ram[n]),\n                        .data_in(data_in_x_reg),\n                        .data_out(out_x[n])\n                    );\n        dff_mem #( .D_W(D_W), .WORD(WORD)) \n                mem_y (\n                        .clk(clk),\n                        .rst(rst),\n                        .addr(addr_y_ram[n]),\n                        .rd_en(rd_en_y_ram[n]),\n                        .wr_en(wr_en_y_ram[n]),\n                        .data_in(data_in_y_reg),\n                        .data_out(out_y[n])\n                    );\n    end\nendgenerate\n\nalways @(posedge clk) begin\n    if(rst) begin\n        STATE <= IDLE;\n        out_init <= 0; \n    end\n    else begin\n        case(STATE) \n        IDLE: begin\n            out_init <= 0; \n            if(load_en) \n                STATE <= LOAD;\n            else if(init)begin\n                out_init <= 1; \n                STATE <= TRANSFER;\n            end\n        end\n        LOAD: begin\n            if(!load_en)\n                STATE <= IDLE;\n        end\n        TRANSFER: begin\n            out_init <= 0; \n            if(rd_en_x_ram[N-1]) begin\n                STATE <= IDLE;\n            end\n        end\n        endcase\n    end\nend\n\n\nreg [$clog2(D_W)-1:0]       bit_counter;\nreg [$clog2(N)-1:0]         addr_counter;\nreg [$clog2(N)-1:0]         ram_counter;\n\ninteger i;\nalways @(posedge clk) begin\n    if(rst) begin\n        //\n        bit_counter   <= 0;\n        addr_counter  <= 0;\n        ram_counter   <= 0;\n        data_in_x_reg <= 0;\n        data_in_y_reg <= 0;\n        //\n        wr_en_x_ram[0] <= 0;\n        rd_en_x_ram[0] <= 0;\n        wr_en_y_ram[0] <= 0;\n        rd_en_y_ram[0] <= 0;\n        for(i=0;i<N;i=i+1) begin\n            // Reset X\n            addr_x_ram[i]  <= 0;\n            // Reset Y\n            addr_y_ram[i]  <= 0;                \n        end\n        //\n    end\n    else begin\n        case(STATE)\n            IDLE : begin\n                addr_counter <= 0;\n                // X Row\n                wr_en_x_ram[N-1] <= 0;\n                // Y Column\n                wr_en_y_ram[N-1] <= 0;\n            end\n            LOAD: begin\n                //\n                bit_counter <= bit_counter + 1;\n                // Load data for X row\n                wr_en_x_ram[ram_counter] <= 0;\n                data_in_x_reg <= {data_in_x,data_in_x_reg[D_W-1:1]};\n                //\n                // Load data for Y Column\n                wr_en_y_ram[ram_counter] <= 0;\n                data_in_y_reg <= {data_in_y,data_in_y_reg[D_W-1:1]};\n                //\n                if(bit_counter == D_W-1) begin\n                    // X Row\n                    wr_en_x_ram[ram_counter] <= 1;\n                    // Y Column\n                    wr_en_y_ram[ram_counter] <= 1;\n                end\n                //\n                if(wr_en_x_ram[ram_counter] == 1) begin\n                    // X Row\n                    addr_x_ram[ram_counter]  <= addr_x_ram[ram_counter] + 1;\n                    // X Row\n                    addr_y_ram[ram_counter]  <= addr_y_ram[ram_counter] + 1;\n                end\n                if(addr_x_ram[ram_counter] == N-1 && wr_en_x_ram[ram_counter]) begin\n                    // X Row & Y Row common ram word block counter\n                    ram_counter <= ram_counter + 1;\n                end\n            end\n            TRANSFER : begin\n                // X & Y Common \n                wr_en_x_ram[ram_counter] <= 0;\n                //\n                if(rd_en_x_ram[N-1]) begin\n                    rd_en_x_ram[0] <= 0;\n                    rd_en_y_ram[0] <= 0;\n                end\n                else begin // Initalize transfer\n                    rd_en_x_ram[0] <= 1;\n                    rd_en_y_ram[0] <= 1;\n                end\n                addr_counter <= addr_counter + 1;\n                // Assign updated addres X & Y\n                addr_x_ram[0] <= addr_counter;\n                addr_y_ram[0] <= addr_counter;\n            end\n        endcase\n    end\nend\n\n// Assign reading\ngenvar x;\nfor (x=1;x<N;x=x+1)\nbegin\n    always@(posedge clk)\n    begin\n        if (rst) begin\n            addr_x_ram[x]  <= 0; \n            rd_en_x_ram[x] <= 0;\n            // Assign for Y column \n            addr_y_ram[x] <= 0;\n            rd_en_y_ram[x] <= 0;\n        end\n        else if(STATE == TRANSFER || STATE == IDLE) begin\n            // Assign for X row\n            addr_x_ram[x]  <= addr_x_ram[x-1]; \n            rd_en_x_ram[x] <= rd_en_x_ram[x-1];\n            // Assign for Y column \n            addr_y_ram[x] <= addr_y_ram[x-1];\n            rd_en_y_ram[x] <= rd_en_y_ram[x-1];\n        end\n        //else if (STATE == IDLE) begin\n        //    rd_en_x_ram[N-1] <= 0;\n        //    rd_en_y_ram[N-1] <= 0;\n        //end\n    end\nend\n\n// Flatten output signal\ninteger r;\n// Packing the 2D array 'z' into the flat wire 'data_core_z_flat'\nalways @(*) begin\n    for (r = 0; r < N; r = r + 1) begin\n        // Compute the starting index of each signal in the flat wire\n        out_x_flat[(r+1)*D_W-1 -: D_W] = out_x[r];\n        out_y_flat[(r+1)*D_W-1 -: D_W] = out_y[r];\n    end\nend\nendmodule\n\nmodule mac #\n(\n    parameter D_W = 16\n)\n(   \n    input  wire               clk,         // Clock\n    input  wire               rst,         // reset\n    input  wire               init,        // Initalize first op\n    input  wire [D_W-1:0]     in_x,        // Input from X axis\n    input  wire [D_W-1:0]     in_y,        // Input from Y axis\n    output reg  [D_W-1:0]     out_x,       // x axis input passthrough\n    output reg  [D_W-1:0]     out_y,       // y axis input passthrough\n    output reg  [(2*D_W-1):0] out_z,       // Output for the sum\n    output reg                out_init     // Init passthrough\n);\n//\nalways @(posedge clk) begin\n    //\n    out_x <= in_x;\n    out_y <= in_y;\n    out_init <= init;\n    //\n    if(rst) begin                       // Reset\n        out_z <= 0;                     \n        out_y <= 0;\n        out_x <= 0;\n        out_init <= 0;\n    end\n    //\n    else if(init)\n        out_z <= in_x * in_y;           // Multiply & Override \n    //\n    else\n        out_z <= out_z + (in_x* in_y);  // Multiply & Accumulate\n    //\nend\n//\nendmodule\n\nmodule output_control #\n(\n    parameter D_W = 8,\n    parameter N = 2\n)\n(\n    // Global Signal\n    input  wire                   clk,\n    input  wire                   rst,\n    // Systolic Output\n    input  wire [(N*N*2*D_W)-1:0] core_out_z,\n    input  wire                   init, \n    // IO Output\n    output reg                    data_out_z,\n    output reg                    tx_ready\n);\n/*\n    STATE Machine\n*/\n//\nlocalparam IDLE = 1'b0;\nlocalparam TX   = 1'b1;\nreg        STATE;\n//enum {IDLE,TX} STATE;\n//\n// Counters\nreg [$clog2(2*D_W)-1:0] bit_counter;\nreg [$clog2(N)-1:0]     column_counter;\nreg [$clog2(N)-1:0]     row_counter;\n//\nwire [2*D_W-1:0]        data_tx_reg;\n//\n//\nassign data_tx_reg = core_out_z[(row_counter*N + column_counter)*2*D_W +: 2*D_W];\n//\nreg init_delay [N-1:0];\n//\nalways @(posedge clk) begin\n    if(rst) begin\n        STATE <= IDLE;\n    end\n    else begin\n        init_delay[0] <= init;\n        case(STATE) \n            IDLE: begin\n                if(init_delay[N-1])\n                    STATE <= TX;\n            end\n            TX: begin\n                if(row_counter == N-1 && column_counter == N-1 && bit_counter == 2*D_W-1) \n                    STATE <= IDLE;\n            end\n        endcase\n    end\nend\n\ninteger x,r,c;\nalways @(posedge clk) begin\n    //\n    if(rst) begin\n        //\n        bit_counter <= 0;\n        column_counter <= 0;\n        row_counter <= 0;\n        tx_ready <= 0;\n        //\n    end\n    //\n    else begin\n        case(STATE) \n            IDLE: begin\n                //\n                bit_counter     <= 0;\n                column_counter  <= 0;\n                row_counter     <= 0;\n                tx_ready        <= 0;\n                data_out_z      <= 0;\n                //        \n            end\n            TX: begin\n                //\n                tx_ready    <= 1;\n                bit_counter <= bit_counter + 1;\n                data_out_z  <=  data_tx_reg[bit_counter];\n                //\n                if(bit_counter == (2*D_W-1)) begin\n                    column_counter <= column_counter + 1;\n                    bit_counter    <= 0;\n                end\n                if(column_counter == N-1 && bit_counter == (2*D_W-1)) begin\n                    column_counter <= 0;\n                    row_counter   <= row_counter + 1;\n                end\n                //\n            end\n        endcase\n    end\nend\n\n// Assign delay counter\ngenvar i;\nfor (i=1;i<N;i=i+1) begin\n    always @(posedge clk) begin\n        init_delay[i] <= init_delay[i-1];\n    end\nend\n\nendmodule\n\nmodule systolic #\n(\n    parameter D_W = 8,\n    parameter N = 2\n)\n(\n    input   wire             clk,                   // Clock Input\n    input   wire             rst,                   // Reset cores & Regs\n    input   wire             init,                  // Init process\n    //input   wire [D_W-1:0]   x        [N-1:0],       // Row input\n    //input   wire [D_W-1:0]   y        [N-1:0],       // Column input\n    //output  reg  [2*D_W-1:0] z        [N-1:0][N-1:0] // MAC unit indv outputs\n    input wire [(N*D_W)-1:0] x_flat,  // Flat wire to hold the packed array\n    input wire [(N*D_W)-1:0] y_flat,  // Flat wire to hold the packed array\n    output reg [(N*N*2*D_W)-1:0] z_flat // Flat wire to hold the packed array\n);\n//\n// Initlize wires\n//\nwire [D_W-1:0]   in_x     [N-1:0][N-1:0];\nwire [D_W-1:0]   in_y     [N-1:0][N-1:0];\nwire [D_W-1:0]   out_x    [N-1:0][N-1:0];\nwire [D_W-1:0]   out_y    [N-1:0][N-1:0];\nwire [2*D_W-1:0] out_z    [N-1:0][N-1:0];\nwire             init_in  [N-1:0][N-1:0];\nwire             init_out [N-1:0][N-1:0];\n// wire assign to output\n//assign z = out_z;\n//\n// flatten-unflatten\nreg  [D_W-1:0]   x       [N-1:0];        // Row input\nreg  [D_W-1:0]   y       [N-1:0];        // Column input\nreg  [2*D_W-1:0] z       [N-1:0][N-1:0]; // MAC unit indv outputs\n//\n\ninteger r, c;\n// Assuming data_core_z_flat is already declared\nalways @(*) begin\n    for (r = 0; r < N; r = r + 1) begin\n        x[r] = x_flat[(r+1)*D_W-1 -: D_W];\n        y[r] = y_flat[(r+1)*D_W-1 -: D_W];\n        for (c = 0; c < N; c = c + 1) begin\n            // Compute the starting index of each signal in the flat wire\n            z_flat[((r * N + c) * (2 * D_W)) +: (2 * D_W)] = out_z[r][c];\n        end\n    end\nend\n//\n//initalize counter\n//\n// Initalize MAC module COL >> ROW\nassign init_in[0][0] = init;\n//\n// Loop Generate MAC matrix\ngenvar i,j,k;\ngenerate \n    //\n    for(i=0; i<N; i=i+1) begin\n        //\n        // Assign initialization wire to first row\n        if(i==0) begin\n            for(k=0; k<N-1;k++) begin\n                assign init_in[0][k+1] = init_out[0][k];\n            end \n        end\n        //\n        for(j=0; j<N; j = j + 1) begin\n            //\n            // Assign wires to mac modules\n            for(k=0;k<N-1;k=k+1) begin\n                assign in_x[i][k+1] = out_x[i][k];\n                assign in_y[k+1][j] = out_y[k][j];\n            end\n            //\n            // Asssign initalization signal to columns\n            if(i==0) begin\n                for (k=0;k<N-1;k++) begin\n                    assign init_in[k+1][j]=init_out[k][j];\n                end\n            end\n            //\n            // Input Columns & Row Assignment\n            if(j==0) assign in_x[i][0] = x[i];\n            if(i==0) assign in_y[0][j] = y[j];\n            //\n            mac #(.D_W(D_W)) mac_inst \n                (\n                    .clk      (clk),\n                    .rst      (rst),\n                    .init     (init_in[i][j]),\n                    .out_init (init_out[i][j]),\n                    .in_x     (in_x[i][j]),\n                    .in_y     (in_y[i][j]),\n                    .out_x    (out_x[i][j]),\n                    .out_y    (out_y[i][j]),\n                    .out_z    (out_z[i][j])\n                );\n            //\n        end\n    end\n    //\nendgenerate\n//\nendmodule\n\nmodule tinytpu_top #\n(\n    parameter D_W = 8,\n    parameter N = 2,\n    parameter WORD = 2\n)\n(\n    input  wire clk,\n    input  wire rst,\n    input  wire data_in_x,\n    input  wire data_in_y,\n    input  wire load_en,\n    input  wire init,\n    output wire data_out_z,\n    output reg  tx_ready\n);\n//\n// REG & WIRES\nwire [(N*D_W)-1:0]     out_x_flat;\nwire [(N*D_W)-1:0]     out_y_flat;\nwire [(N*N*2*D_W)-1:0] out_z_flat;\nwire out_init;\nreg tx_ready_reg;\n\nalways @(posedge clk) begin\n    tx_ready <= tx_ready_reg;\nend \n//wire  [D_W-1:0]   data_core_x  [N-1:0];\n//wire  [D_W-1:0]   data_core_y  [N-1:0];\n//wire  [2*D_W-1:0] data_core_z   [N-1:0][N-1:0];\n//\n/*\n    Input Control Module\n*/\ninput_control #(.D_W(D_W), .N(N), .WORD(WORD)) \n        input_control_inst (\n                        .clk(clk),\n                        .rst(rst),\n                        .data_in_x(data_in_x),\n                        .data_in_y(data_in_y),\n                        .load_en(load_en),\n                        .init(init),\n                        .out_x_flat(out_x_flat),\n                        .out_y_flat(out_y_flat),\n                        .out_init(out_init)\n                     );\n/*\n    Output Control Module\n*/\noutput_control #(.D_W(D_W), .N(N))\n        output_control_inst (\n                                .clk(clk),\n                                .rst(rst),\n                                .core_out_z(out_z_flat),\n                                .init(init),\n                                .data_out_z(data_out_z),\n                                .tx_ready(tx_ready_reg)\n                            );\n/*\n    Systolic Core\n*/\nsystolic #(.D_W(D_W), .N(N)) \n        systolic_inst (\n                        .clk(clk),\n                        .rst(rst),\n                        .init(out_init),\n                        .x_flat(out_x_flat),\n                        .y_flat(out_y_flat),\n                        .z_flat(out_z_flat)\n                      );\n//\n//\n//\nendmodule", "mask_idx": {"conditional_statement": [[9799, 9952], [10805, 11213], [6902, 7109], [4410, 5006], [4777, 4820]], "blocking_assignment": [[8785, 8827], [14156, 14217], [8836, 8878], [13948, 13982], [13991, 14025]], "module_program_interface_instantiation": [[1232, 1676], [15315, 15769], [3969, 4356], [17459, 17782]], "always_construct": [[2070, 2159], [16288, 16350], [4378, 5010], [5149, 7784], [7844, 8541], [10773, 11217], [12429, 12506]], "case_statement": [[4502, 4998], [11451, 12351], [5688, 7772], [10904, 11205]], "ansi_port_declaration": [[15957, 15973], [2648, 2669], [16032, 16052]], "continuous_assign": [[821, 849], [14303, 14331], [1124, 1145], [997, 1025]], "parameter_declaration": [[15888, 15904], [10008, 10026], [8921, 8939], [12547, 12565], [2581, 2599], [15909, 15927], [2560, 2576], [1738, 1756], [15865, 15883], [1714, 1733]], "nonblocking_assignment": [[11332, 11352], [6703, 6759], [11599, 11620]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1232, 1676], [3573, 3960], [3969, 4356], [15315, 15769], [16519, 17005], [17038, 17434], [17459, 17782]], "continuous_assign": [[751, 771], [821, 849], [852, 880], [883, 911], [914, 942], [964, 994], [997, 1025], [1028, 1049], [1052, 1073], [1076, 1097], [1100, 1121], [1124, 1145], [1148, 1169], [1177, 1199], [1202, 1224], [10661, 10742], [14303, 14331], [14564, 14604], [14797, 14831], [14848, 14882], [15058, 15096], [15215, 15240], [15262, 15287]], "blocking_assignment": [[8785, 8827], [8836, 8878], [13948, 13982], [13991, 14025], [14156, 14217]], "nonblocking_assignment": [[2126, 2147], [2221, 2283], [2326, 2380], [2421, 2481], [4432, 4446], [4455, 4470], [4547, 4562], [4604, 4618], [4666, 4681], [4698, 4716], [4806, 4820], [4869, 4884], [4940, 4954], [5214, 5233], [5242, 5261], [5270, 5289], [5298, 5317], [5326, 5345], [5365, 5385], [5394, 5414], [5423, 5443], [5452, 5472], [5541, 5561], [5597, 5633], [5741, 5759], [5801, 5823], [5868, 5890], [5966, 5997], [6053, 6083], [6100, 6152], [6230, 6260], [6277, 6329], [6445, 6475], [6528, 6558], [6703, 6759], [6809, 6865], [7058, 7089], [7204, 7234], [7317, 7337], [7358, 7378], [7468, 7488], [7509, 7529], [7566, 7599], [7663, 7693], [7710, 7740], [7910, 7931], [7944, 7964], [8013, 8032], [8045, 8065], [8180, 8215], [8228, 8263], [8312, 8345], [8358, 8393], [9559, 9573], [9578, 9592], [9597, 9614], [9679, 9711], [9720, 9731], [9740, 9751], [9760, 9774], [9816, 9871], [9896, 9952], [10827, 10841], [10873, 10895], [10997, 11009], [11159, 11173], [11306, 11323], [11332, 11352], [11361, 11378], [11387, 11401], [11523, 11544], [11561, 11582], [11599, 11620], [11637, 11658], [11675, 11696], [11797, 11814], [11831, 11862], [11879, 11920], [12011, 12048], [12069, 12089], [12206, 12226], [12247, 12280], [12465, 12498], [16320, 16345]], "case_statement": [[4502, 4998], [5688, 7772], [10904, 11205], [11451, 12351]], "conditional_statement": [[2102, 2155], [2197, 2489], [2301, 2489], [2399, 2489], [4410, 5006], [4575, 4732], [4636, 4732], [4777, 4820], [4897, 4970], [5181, 7780], [6365, 6578], [6614, 6885], [6902, 7109], [7270, 7549], [7883, 8405], [8091, 8405], [9626, 9952], [9799, 9952], [10805, 11213], [10957, 11009], [11064, 11173], [11273, 12359], [11956, 12109], [12126, 12300]], "always_construct": [[2070, 2159], [2175, 2493], [4378, 5010], [5149, 7784], [7844, 8541], [8649, 8890], [9520, 9963], [10773, 11217], [11234, 12363], [12429, 12506], [13882, 14241], [16288, 16350]], "parameter_declaration": [[1714, 1733], [1738, 1756], [2537, 2555], [2560, 2576], [2581, 2599], [8921, 8939], [10008, 10026], [10031, 10046], [12547, 12565], [12570, 12585], [15865, 15883], [15888, 15904], [15909, 15927]], "ansi_port_declaration": [[142, 189], [194, 242], [247, 293], [298, 345], [350, 430], [435, 523], [528, 564], [569, 622], [1765, 1780], [1785, 1800], [1823, 1840], [1845, 1880], [1904, 1921], [1936, 1965], [1970, 1999], [2608, 2623], [2628, 2643], [2648, 2669], [2674, 2695], [2700, 2719], [2724, 2740], [2745, 2781], [2786, 2822], [2827, 2846], [8951, 8998], [9003, 9050], [9055, 9115], [9120, 9179], [9184, 9243], [9248, 9314], [9319, 9385], [9390, 9450], [9455, 9513], [10076, 10110], [10115, 10149], [10177, 10218], [10223, 10259], [10281, 10322], [10327, 10365], [12594, 12656], [12661, 12730], [12735, 12798], [13022, 13093], [13098, 13169], [13174, 13247], [15936, 15952], [15957, 15973], [15978, 16000], [16005, 16027], [16032, 16052], [16057, 16074], [16079, 16102], [16107, 16127]]}}
{"sample_i": "Santeep-TT_UM_SERDES", "topmodule": "tt_um_serdes", "code": "/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_serdes (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  // All output pins must be assigned. If not used, assign to 0.\n \n    \n    wire ser_in = uio_in[0];\n    wire ser_out = uio_out[0];\n    wire data_en = uio_in[2];\n    wire par_en = uio_in[3];\n    wire ser_en = uio_in[4];\n\n    serdes_top serdes_inst (\n        .clk(clk),\n        .rst_n(rst_n),\n        .data_en(data_en),\n        .ser_in(ser_in),\n        .par_en(par_en),  \n        .ser_en(ser_en),  \n        .ser_out(ser_out),\n        .data_out(uo_out),\n        .data_8b_in(ui_in)  \n    );\n      assign uio_oe = 8'b0;  \n    assign uio_out[7:1] = 7'b0;\nendmodule\n\n\nmodule serdes_top(\n    input           clk,\n    input           rst_n,\n    input           data_en,\n    input           ser_in,\n    input           par_en,\n    input           ser_en,\n    output wire      ser_out,\n    output wire [7:0]    data_out,\n    input [7:0]     data_8b_in\n);\n\n    // Serializer module\n    wire [7:0]       data_8b_latched;\n    wire [9:0]       data_10b_encoded;\n    wire [9:0]       data_10b_latched;\n\n    latch_8bit latch_8b_inst (\n        .clk(clk),\n        .rst_n(rst_n),\n        .data_8b_in(data_8b_in),\n        .data_en(data_en),\n        .data_8b_out(data_8b_latched)\n    );  \n    \n    encoder_8b_10b encoder_inst (\n        .clk(clk),\n        .rst_n(rst_n),\n        .data_8b_in(data_8b_latched),\n        .ser_en(ser_en),\n        .data_10b_out(data_10b_encoded)\n    );\n    \n    latch_10bit latch_10b_inst (\n        .clk(clk),\n        .rst_n(rst_n),\n        .data_10b_in(data_10b_encoded),\n        .data_en(data_en),\n        .data_10b_out(data_10b_latched)\n    );\n\n    piso_10bit piso_inst (\n        .clk(clk),\n        .rst_n(rst_n),\n        .par_in(data_10b_latched),\n        .load_en(ser_en),\n        .ser_out(ser_out)\n    );\n\n    // Deserializer module\n    wire [9:0]       data_10b;\n    wire[9:0]\t    data_10b_latched_d;\n    wire [7:0]       data_8b_decoded;\n\n    // Instantiate the SIPO module\n    sipo_10bit sipo_inst_d (\n        .clk(clk),\n        .rst_n(rst_n),\n        .ser_in(ser_in),\n        .shift_en(par_en),\n        .par_out(data_10b)\n    );\n\n    // Instantiate the 10-bit latch\n    latch_10bit latch_10b_inst_d (\n        .clk(clk),\n        .rst_n(rst_n),\n        .data_10b_in(data_10b),\n        .data_en(data_en),\n        .data_10b_out(data_10b_latched_d)\n    );\n\n    // Instantiate the 10b/8b decoder\n    decoder_10b_8b decoder_inst_d (\n        .clk(clk),\n        .rst_n(rst_n),\n        .data_10b_in(data_10b_latched_d),\n        .par_en(par_en),\n        .data_8b_out(data_8b_decoded)\n    );\n\n    // Instantiate the 8-bit latch\n    latch_8bit latch_8b_inst_d (\n        .clk(clk),\n        .rst_n(rst_n),\n        .data_8b_in(data_8b_decoded),\n        .data_en(data_en),\n        .data_8b_out(data_out)\n    );\nendmodule\n\nmodule latch_8bit(\n    input           clk,\n    input           rst_n,\n    input [7:0]     data_8b_in,\n    input           data_en,\n    output reg [7:0]    data_8b_out\n);\n\n    always @ ( posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            data_8b_out <= 8'h00;\n        end\n        else begin\n            if (data_en) begin\n                data_8b_out <= data_8b_in;\n            end\n            else data_8b_out <= data_8b_out;\n        end\n    end\n\nendmodule\n\n\nmodule encoder_8b_10b(\n    input           clk,\n    input           rst_n,\n    input [7:0]     data_8b_in,\n    input           ser_en,\n    output reg[9:0]    data_10b_out\n);\n\n    reg [3:0]       temp_4b;\n    reg [5:0]       temp_6b;\n\n    always @ (posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            temp_4b <= 4'b0000;\n            temp_6b <= 6'b000000;\n        end\n        else begin\n            if (!ser_en) begin\n                case (data_8b_in[7:5])\n                3'b000: temp_4b <= 4'b0100;\n                3'b001: temp_4b <= 4'b1001;\n                3'b010: temp_4b <= 4'b0101;\n                3'b011: temp_4b <= 4'b0011;\n                3'b100: temp_4b <= 4'b0010;\n                3'b101: temp_4b <= 4'b1010;\n                3'b110: temp_4b <= 4'b0110;\n                3'b111: temp_4b <= 4'b0001;\n                default: temp_4b <= 4'b0000;    \n                endcase\n                case (data_8b_in[4:0])\n                5'b00000: temp_6b <= 6'b011000;\n                5'b00001: temp_6b <= 6'b011101;\n                5'b00010: temp_6b <= 6'b010010;     \n                5'b00011: temp_6b <= 6'b110001;\n                5'b00100: temp_6b <= 6'b110101;\n                5'b00101: temp_6b <= 6'b101001;\n                5'b00110: temp_6b <= 6'b011001;\n                5'b00111: temp_6b <= 6'b111000;\n                5'b01000: temp_6b <= 6'b111001;\n                5'b01001: temp_6b <= 6'b100101;\n                5'b01010: temp_6b <= 6'b010101;\n                5'b01011: temp_6b <= 6'b110100;\n                5'b01100: temp_6b <= 6'b001101;\n                5'b01101: temp_6b <= 6'b101100;\n                5'b01110: temp_6b <= 6'b011100;\n                5'b01111: temp_6b <= 6'b010111;\n                5'b10000: temp_6b <= 6'b011011;\n                5'b10001: temp_6b <= 6'b100011;\n                5'b10010: temp_6b <= 6'b010011;\n                5'b10011: temp_6b <= 6'b110010;\n                5'b10100: temp_6b <= 6'b001011;\n                5'b10101: temp_6b <= 6'b101010;\n                5'b10110: temp_6b <= 6'b011010;\n                5'b10111: temp_6b <= 6'b111010;\n                5'b11000: temp_6b <= 6'b110011;\n                5'b11001: temp_6b <= 6'b100110;\n                5'b11010: temp_6b <= 6'b010110;\n                5'b11011: temp_6b <= 6'b110110;\n                5'b11100: temp_6b <= 6'b001110;\n                5'b11101: temp_6b <= 6'b101110;\n                5'b11110: temp_6b <= 6'b011110;\n                5'b11111: temp_6b <= 6'b101011;\n                default: temp_6b <= 6'b000000;\n                endcase\n            end\n            else data_10b_out <= {temp_4b, temp_6b};\n        end\n    end \nendmodule\n\nmodule latch_10bit(\n    input           clk,\n    input           rst_n,\n    input [9:0]     data_10b_in,\n    input           data_en,\n    output reg [9:0]    data_10b_out\n);\n    always @ (posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            data_10b_out <= 10'h00;\n        end\n        else begin\n            if (data_en) begin\n                data_10b_out <= data_10b_in;\n            end\n            else data_10b_out <= data_10b_out;\n        end\n    end\nendmodule\n\nmodule piso_10bit(\n    input           clk,\n    input           rst_n,\n    input [9:0]     par_in,\n    input           load_en,\n    output reg      ser_out\n);\n\n    reg [9:0]       shift_reg;\n\n    always @(posedge clk) begin\n        if (!rst_n) begin\n            shift_reg <= 10'b0000000000;\n        end \n        else begin \n            if (load_en) begin\n                shift_reg <= par_in;\n            end\n            else begin\n                ser_out <= shift_reg[0];\n                shift_reg <= {1'b0, shift_reg[9:1]};  \n            end\n        end\n    end\n\nendmodule\n\nmodule sipo_10bit(\n    input           clk,\n    input           rst_n,\n    input           ser_in,\n    input           shift_en,\n    output reg [9:0]    par_out\n);\n\n    reg [9:0]       shift_reg;\n\n    always @ (posedge clk)begin\n        if (!rst_n) begin\n            shift_reg <= 10'b0000000000;\n        end\n        else begin\n            if (shift_en) begin\n                par_out <= shift_reg;\n            end\n            else shift_reg <= {shift_reg[8:0], ser_in};\n        end\n    end\n\nendmodule\n\nmodule decoder_10b_8b(\n    input           clk,\n    input           rst_n,\n    input [9:0]     data_10b_in,\n    input           par_en,\n    output reg [7:0]    data_8b_out\n);\n\n    reg [2:0]       temp_3b;\n    reg [4:0]       temp_5b;\n\n    always @ (posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            temp_3b <= 3'b000;\n            temp_5b <= 5'b00000;\n        end\n        else begin\n            if (!par_en) begin\n                case (data_10b_in[9:6])\n                4'b0100: temp_3b <= 3'b000;\n                4'b1001: temp_3b <= 3'b001;\n                4'b0101: temp_3b <= 3'b010;\n                4'b0011: temp_3b <= 3'b011;\n                4'b0010: temp_3b <= 3'b100;\n                4'b1010: temp_3b <= 3'b101;\n                4'b0110: temp_3b <= 3'b110;\n                4'b0001: temp_3b <= 3'b111;\n                default: temp_3b <= 3'b000;    \n                endcase\n                case (data_10b_in[5:0])\n                6'b011000: temp_5b <= 5'b00000;\n                6'b011101: temp_5b <= 5'b00001;\n                6'b010010: temp_5b <= 5'b00010;     \n                6'b110001: temp_5b <= 5'b00011;\n                6'b110101: temp_5b <= 5'b00100;\n                6'b101001: temp_5b <= 5'b00101;\n                6'b011001: temp_5b <= 5'b00110;\n                6'b111000: temp_5b <= 5'b00111;\n                6'b111001: temp_5b <= 5'b01000;\n                6'b100101: temp_5b <= 5'b01001;\n                6'b010101: temp_5b <= 5'b01010;\n                6'b110100: temp_5b <= 5'b01011;\n                6'b001101: temp_5b <= 5'b01100;\n                6'b101100: temp_5b <= 5'b01101;\n                6'b011100: temp_5b <= 5'b01110;\n                6'b010111: temp_5b <= 5'b01111;\n                6'b011011: temp_5b <= 5'b10000;\n                6'b100011: temp_5b <= 5'b10001;\n                6'b010011: temp_5b <= 5'b10010;\n                6'b110010: temp_5b <= 5'b10011;\n                6'b001011: temp_5b <= 5'b10100;\n                6'b101010: temp_5b <= 5'b10101;\n                6'b011010: temp_5b <= 5'b10110;\n                6'b111010: temp_5b <= 5'b10111;\n                6'b110011: temp_5b <= 5'b11000;\n                6'b100110: temp_5b <= 5'b11001;\n                6'b010110: temp_5b <= 5'b11010;\n                6'b110110: temp_5b <= 5'b11011;\n                6'b001110: temp_5b <= 5'b11100;\n                6'b101110: temp_5b <= 5'b11101;\n                6'b011110: temp_5b <= 5'b11110;\n                6'b101011: temp_5b <= 5'b11111;\n                default: temp_5b <= 5'b00000;\n                endcase\n            end\n            else data_8b_out <= {temp_3b,temp_5b};\n        end\n    end\nendmodule\n", "mask_idx": {"conditional_statement": [[4108, 6449], [7189, 7511], [7293, 7499], [4235, 6437]], "module_program_interface_instantiation": [[1981, 2165], [2923, 3108], [1790, 1971]], "always_construct": [[6648, 6945], [7153, 7519], [8272, 10671], [7733, 8020], [4054, 6458]], "case_statement": [[4270, 4717], [4734, 6368], [8950, 10584], [8486, 8933]], "ansi_port_declaration": [[6494, 6514], [1335, 1358], [1250, 1274], [7005, 7027]], "continuous_assign": [[1107, 1130], [1135, 1162]], "nonblocking_assignment": [[7445, 7483], [5412, 5433], [4980, 5001], [8711, 8729], [6228, 6249]]}, "all_mask_idx": {"module_program_interface_instantiation": [[838, 1100], [1605, 1780], [1790, 1971], [1981, 2165], [2171, 2329], [2505, 2657], [2699, 2879], [2923, 3108], [3149, 3322]], "continuous_assign": [[1107, 1130], [1135, 1162]], "blocking_assignment": [], "nonblocking_assignment": [[3595, 3616], [3695, 3721], [3755, 3782], [4138, 4157], [4170, 4191], [4317, 4336], [4361, 4380], [4405, 4424], [4449, 4468], [4493, 4512], [4537, 4556], [4581, 4600], [4625, 4644], [4670, 4693], [4783, 4804], [4831, 4852], [4879, 4905], [4932, 4953], [4980, 5001], [5028, 5049], [5076, 5097], [5124, 5145], [5172, 5193], [5220, 5241], [5268, 5289], [5316, 5337], [5364, 5385], [5412, 5433], [5460, 5481], [5508, 5529], [5556, 5577], [5604, 5625], [5652, 5673], [5700, 5721], [5748, 5769], [5796, 5817], [5844, 5865], [5892, 5913], [5940, 5961], [5988, 6009], [6036, 6057], [6084, 6105], [6132, 6153], [6180, 6201], [6228, 6249], [6276, 6297], [6323, 6344], [6402, 6437], [6732, 6755], [6834, 6862], [6896, 6925], [7219, 7247], [7328, 7348], [7404, 7428], [7445, 7483], [7799, 7827], [7907, 7928], [7962, 8000], [8356, 8374], [8387, 8407], [8535, 8553], [8579, 8597], [8623, 8641], [8667, 8685], [8711, 8729], [8755, 8773], [8799, 8817], [8843, 8861], [8887, 8909], [9001, 9021], [9049, 9069], [9097, 9122], [9150, 9170], [9198, 9218], [9246, 9266], [9294, 9314], [9342, 9362], [9390, 9410], [9438, 9458], [9486, 9506], [9534, 9554], [9582, 9602], [9630, 9650], [9678, 9698], [9726, 9746], [9774, 9794], [9822, 9842], [9870, 9890], [9918, 9938], [9966, 9986], [10014, 10034], [10062, 10082], [10110, 10130], [10158, 10178], [10206, 10226], [10254, 10274], [10302, 10322], [10350, 10370], [10398, 10418], [10446, 10466], [10494, 10514], [10540, 10560], [10618, 10651]], "case_statement": [[4270, 4717], [4734, 6368], [8486, 8933], [8950, 10584]], "conditional_statement": [[3565, 3794], [3660, 3782], [4108, 6449], [4235, 6437], [6702, 6937], [6799, 6925], [7189, 7511], [7293, 7499], [7769, 8012], [7871, 8000], [8326, 10663], [8451, 10651]], "always_construct": [[3510, 3802], [4054, 6458], [6648, 6945], [7153, 7519], [7733, 8020], [8272, 10671]], "parameter_declaration": [], "ansi_port_declaration": [[128, 175], [180, 228], [233, 279], [284, 331], [336, 416], [421, 509], [514, 550], [555, 608], [1198, 1218], [1223, 1245], [1250, 1274], [1279, 1302], [1307, 1330], [1335, 1358], [1363, 1388], [1393, 1423], [1428, 1454], [3357, 3377], [3382, 3404], [3409, 3436], [3441, 3465], [3470, 3501], [3843, 3863], [3868, 3890], [3895, 3922], [3927, 3950], [3955, 3986], [6494, 6514], [6519, 6541], [6546, 6574], [6579, 6603], [6608, 6640], [6980, 7000], [7005, 7027], [7032, 7055], [7060, 7084], [7089, 7112], [7555, 7575], [7580, 7602], [7607, 7630], [7635, 7660], [7665, 7692], [8060, 8080], [8085, 8107], [8112, 8140], [8145, 8168], [8173, 8204]]}}
{"sample_i": "adonairc-tt07-dda-van-der-pol", "topmodule": "tt_um_adonairc_dda", "code": "/*\n * Copyright (c) 2024 Adonai Cruz\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_adonairc_dda (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\tparameter N = 16; // Posit word size\n\tparameter ES = 1; // Posit ES\n\n\t// All output pins must be assigned. If not used, assign to 0.\n\tassign uo_out  = 0;\n\tassign uio_out[7:3] = 0;\n\tassign uio_out[1:0] = 0;\n\tassign uio_oe[7:4]  = 0;\n\t\n\t// SPI pins\n\twire sclk, cs, mosi, miso;\n\n\t// Output port (MISO)\n\tassign uio_oe[2] = 1; \n\n\t// Input ports\n\tassign cs  = uio_in[0];\n\tassign uio_oe[0] = 0;\n\tassign mosi  = uio_in[1];\n\tassign uio_oe[1] = 0;\n\tassign sclk  = uio_in[3];\n\tassign uio_oe[3] = 0;\n\t\n\t// Dynamical system parameters\n\treg [N-1:0] icx, icy; // Initial conditions for variables x and y\n\n\twire [N-1:0] mu; // Van-der-Pol parameter\n\treg [N-1:0] r_mu;\n\n\t// DDA\n\treg clk_dda; // DDA clock\n\n\tassign mu = r_mu;\n\n\t// SPI\n\treg [2:0] r_SCK;\n\treg [2:0] r_CS;\n\treg [1:0] r_MOSI;\n\treg [4:0] bitcnt; // bit counter\n\treg is_data_received; // high when a byte has been received\n\treg [31:0] data_received;\n\treg [31:0] data_sent;\n\treg [31:0] cnt;\n\n\t// state variables\n\twire [N-1:0] x,y;\n\n\t// Van-Der-Pol DDA instance\n\tdda #(.N(N), .ES(ES)) van_der_pol(\n\t\t.clk(clk_dda),\n\t\t.rst_n(rst_n),\n\t\t.x(x),\n\t\t.y(y),\n\t\t.icx(icx),\n\t\t.icy(icy),\n\t\t.mu(mu)\n\t);\n\n\t// Reset to enable DDA and set initial conditions\n\talways @(posedge clk)  begin\n\t\tif (!rst_n) begin\n\t\t\ticx <= 16'h3000;\n\t\t\ticy <= 16'h3000;\n\t\tend\n\tend\n\n\t// \n\t// SPI interface\n\t//\n\n\t// Sync SCK to FPGA clock using a 3-bits shift register;\n\talways @(posedge clk) r_SCK <= {r_SCK[1:0], sclk};\n\twire SCK_risingedge = (r_SCK[2:1]==2'b01); // detect SCK rising edge\n\twire SCK_fallingedge = (r_SCK[2:1]==2'b10); // SCK falling edge\n\n\t// Sync CS\n\talways @(posedge clk) r_CS <= {r_CS[1:0], cs};\n\twire CS_active = ~r_CS[1]; // CS is active low\n\twire CS_startmessage = (r_CS[2:1]==2'b10); // message starts at falling edge\n\twire CS_endmessage = (r_CS[2:1]==2'b01); // message stops at rising edge\n\n\t// Sync MOSI\n\talways @(posedge clk) r_MOSI <= {r_MOSI[0], mosi};\n\twire MOSI_data = r_MOSI[1];\n\n\t// Handle SPI data in 32-bits word format\n\talways @(posedge clk)\n\tbegin\n\t\tif (~CS_active)\n\t\t\tbitcnt <= 0;\n\t\telse\n\t\tif (SCK_risingedge)\n\t\tbegin\n\t\t\tbitcnt <= bitcnt + 1;\n\t\t\t// implement a shift-left register (since we receive the data MSB first)\n\t\t\tdata_received <= {data_received[30:0], MOSI_data};\n\t\tend\n\tend\n\n\talways @(posedge clk) is_data_received <= CS_active &&  SCK_risingedge && (bitcnt == 5'b11111);\n\n\t// Updates system parameter mu\n\talways @(posedge clk) if(is_data_received) r_mu <= data_received[15:0];\n\n\t// Data write\n\talways @(posedge clk) begin\n\t\tif(!rst_n) begin\n\t\t\tclk_dda <= 0;\n\t\tend\n\t\tif (CS_startmessage) begin\n\t\t\tclk_dda <= !clk_dda; // clock the DDA\n\t\tend\n\tend\n\n\talways @(posedge clk)\n\tif (CS_active)\n\tbegin\n\t\tif (CS_startmessage) data_sent <= {x,y};\n\t\telse\n\t\tif (SCK_fallingedge) data_sent <= (bitcnt == 5'b00000)? x : {data_sent[30:0], 1'b0};\n\tend\n\n\tassign uio_out[2] = data_sent[31]; // send MSB first (MISO)\n\nendmodule\n\n\n/*\n * Copyright (c) 2024 Adonai Cruz\n * SPDX-License-Identifier: Apache-2.0\n */\n\nmodule dda (\n    input clk, // Clock\n    input rst_n, // Reset (active low)\n    output [N-1:0] x,y, // Dynamical system state variables\n    input [N-1:0] icx, icy, // Initial conditions\n    input [N-1:0] mu // Van-der-Pol parameter\n);\n\n// Posit parameters\nparameter N = 16;\nparameter ES = 1;\n\n// Multiplications\nwire [N-1:0] w_mult1, w_mult2, w_mult3;\n\nposit_mult #(.N(N),.ES(ES)) mult1(.in1(x), .in2(x), .out(w_mult1)); // Multiply x*x\nposit_mult #(.N(N),.ES(ES)) mult2(.in1(mu), .in2(w_sub1), .out(w_mult2)); // Multiply mu*(1-x*x)\nposit_mult #(.N(N),.ES(ES)) mult3(.in1(w_mult2), .in2(y), .out(w_mult3)); // Multiply mu*(1-x*x)*y\n\n// Subtraction\nwire [N-1:0] w_sub1, w_sub2;\n\nwire [N-1:0] w_neg_mult1;\nassign w_neg_mult1 = {~w_mult1[N-1], ~w_mult1[N-2:0]+1'b1};\n\nwire [N-1:0] w_neg_x;\nassign w_neg_x = {~x[N-1], ~x[N-2:0]+1'b1};\n\nposit_add #(.N(N),.ES(ES)) sub_1_mult_x_x(.in1(16'b0100000000000000), .in2(w_neg_mult1), .out(w_sub1)); // Subtract 1 - x*x\nposit_add #(.N(N),.ES(ES)) sub_rho_z(.in1(w_mult3), .in2(w_neg_x), .out(w_sub2)); // Subtract mu*(1-x*x)y - x\n\n// Van der Pol oscillator\n// dx/dt = y\n// dy/dt = mu*(1 - x*x) - x\n\neuler_integrator  #(.N(N),.ES(ES)) int1(.out(x), .funct(y), .ic(icx), .clk(clk), .rst_n(rst_n));\neuler_integrator  #(.N(N),.ES(ES)) int2(.out(y), .funct(w_sub2), .ic(icy), .clk(clk), .rst_n(rst_n));\n\nendmodule\n\n\n/// Euler integrator\nmodule euler_integrator(out, funct, clk, rst_n, ic);\n\tparameter N = 16;\n\tparameter ES = 1;\n\n\tinput clk, rst_n;\n\toutput [N-1:0] out; // state variable\n\tinput [N-1:0] funct; // the dV/dt function\n\tinput [N-1:0] ic; // initial condition\n\n\twire [N-1:0] out, v1new;\n\treg [N-1:0] v1;\n\n\twire [N-1:0] out_mult;\n\t\n\t// compute new state variable with dt \n\t// v1(n+1) = v1(n) + dt*funct(n)\n\n    // Multiply funct(n) by constant dt\n\tposit_dt_mult  #(\n\t\t.N(N),\n\t\t.ES(ES)\n\t) mult (\n\t\t.in1(funct),\n\t\t.out(out_mult)\n\t);\n\n\tposit_add #(\n\t\t.N(N),\n\t\t.ES(ES)\n\t)\n\tadd(\n\t\t.in1(out_mult),\n\t\t.in2(v1),\n\t\t.out(v1new)\n\t);\n\n\talways @(posedge clk)\n\tbegin\n\t\tif (!rst_n)\n\t\t\tv1 <= ic;\n\t\telse\n\t\t\tv1 <= v1new;\n\tend\n\tassign out = v1;\n\nendmodule\n\n\n\n/*\n * Copyright (c) 2024 Adonai Cruz\n * SPDX-License-Identifier: Apache-2.0\n */\n\n///////////\n// Adder //\n///////////\nmodule posit_add (in1, in2, out);\n\nfunction [31:0] log2;\ninput reg [31:0] value;\n\tbegin\n\tvalue = value-1;\n\tfor (log2=0; value>0; log2=log2+1)\n        \tvalue = value>>1;\n      \tend\nendfunction\n\nparameter N = 16;\nparameter Bs = log2(N); \nparameter ES = 1;\n\ninput [N-1:0] in1, in2;\noutput [N-1:0] out;\nwire inf, zero;\n\nwire s1 = in1[N-1];\nwire s2 = in2[N-1];\nwire zero_tmp1 = |in1[N-2:0];\nwire zero_tmp2 = |in2[N-2:0];\nwire inf1 = in1[N-1] & (~zero_tmp1),\n\tinf2 = in2[N-1] & (~zero_tmp2);\nwire zero1 = ~(in1[N-1] | zero_tmp1),\n\tzero2 = ~(in2[N-1] | zero_tmp2);\nassign inf = inf1 | inf2,\n\tzero = zero1 & zero2;\n\n//Data Extraction\nwire rc1, rc2;\nwire [Bs-1:0] regime1, regime2;\nwire [ES-1:0] e1, e2;\nwire [N-ES-1:0] mant1, mant2;\nwire [N-1:0] xin1 = s1 ? -in1 : in1;\nwire [N-1:0] xin2 = s2 ? -in2 : in2;\ndata_extract_v1 #(.N(N),.ES(ES)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1));\ndata_extract_v1 #(.N(N),.ES(ES)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2));\n\nwire [N-ES:0] m1 = {zero_tmp1,mant1}, \n\tm2 = {zero_tmp2,mant2};\n\n//Large Checking and Assignment\nwire in1_gt_in2 = (xin1[N-2:0] >= xin2[N-2:0]) ? 1'b1 : 1'b0;\n\nwire ls = in1_gt_in2 ? s1 : s2;\nwire op = s1 ~^ s2;\n\nwire lrc = in1_gt_in2 ? rc1 : rc2;\nwire src = in1_gt_in2 ? rc2 : rc1;\n\nwire [Bs-1:0] lr = in1_gt_in2 ? regime1 : regime2;\nwire [Bs-1:0] sr = in1_gt_in2 ? regime2 : regime1;\n\nwire [ES-1:0] le = in1_gt_in2 ? e1 : e2;\nwire [ES-1:0] se = in1_gt_in2 ? e2 : e1;\n\nwire [N-ES:0] lm = in1_gt_in2 ? m1 : m2;\nwire [N-ES:0] sm = in1_gt_in2 ? m2 : m1;\n\n//Exponent Difference: Lower Mantissa Right Shift Amount\nwire [ES+Bs+1:0] diff;\nwire [Bs:0] lr_N;\nwire [Bs:0] sr_N;\na_abs_regime #(.N(Bs)) uut_abs_regime1 (lrc, lr, lr_N);\na_abs_regime #(.N(Bs)) uut_abs_regime2 (src, sr, sr_N);\na_sub_N #(.N(ES+Bs+1)) uut_ediff ({lr_N,le}, {sr_N, se}, diff);\nwire [Bs-1:0] exp_diff = (|diff[ES+Bs:Bs]) ? {Bs{1'b1}} : diff[Bs-1:0];\n\n//DSR Right Shifting\nwire [N-1:0] DSR_right_in;\ngenerate\n\tif (ES >= 2) \n\tassign DSR_right_in = {sm,{ES-1{1'b0}}};\n\telse \n\tassign DSR_right_in = sm;\nendgenerate\n\nwire [N-1:0] DSR_right_out;\nwire [Bs-1:0] DSR_e_diff  = exp_diff;\nDSR_right_N_S #(.N(N), .S(Bs))  dsr1(.a(DSR_right_in), .b(DSR_e_diff), .c(DSR_right_out));\n\n//Mantissa Addition\nwire [N-1:0] add_m_in1;\ngenerate\n\tif (ES >= 2) \n\tassign add_m_in1 = {lm,{ES-1{1'b0}}};\n\telse \n\tassign add_m_in1 = lm;\nendgenerate\n\nwire [N:0] add_m;\na_add_sub_N #(.N(N)) uut_add_sub_N (op, add_m_in1, DSR_right_out, add_m);\nwire [1:0] mant_ovf = add_m[N:N-1];\n\n//LOD\nwire [N-1:0] LOD_in = {(add_m[N] | add_m[N-1]), add_m[N-2:0]};\nwire [Bs-1:0] left_shift;\nLOD_N #(.N(N)) l2(.in(LOD_in), .out(left_shift));\n\n//DSR Left Shifting\nwire [N-1:0] DSR_left_out_t;\nDSR_left_N_S #(.N(N), .S(Bs)) dsl1(.a(add_m[N:1]), .b(left_shift), .c(DSR_left_out_t));\nwire [N-1:0] DSR_left_out = DSR_left_out_t[N-1] ? DSR_left_out_t[N-1:0] : {DSR_left_out_t[N-2:0],1'b0}; \n\n\n//Exponent and Regime Computation\nwire [ES+Bs+1:0] le_o_tmp, le_o;\na_sub_N #(.N(ES+Bs+1)) sub3 ({lr_N,le}, {{ES+1{1'b0}},left_shift}, le_o_tmp);\nadd_1 #(.N(ES+Bs+1)) uut_add_mantovf (le_o_tmp, mant_ovf[1], le_o);\n\nwire [ES-1:0] e_o;\nwire [Bs-1:0] r_o;\na_reg_exp_op #(.ES(ES), .Bs(Bs)) uut_reg_ro (le_o[ES+Bs:0], e_o, r_o);\n\n//Exponent and Mantissa Packing\nwire [2*N-1+3:0] tmp_o;\ngenerate\n\tif(ES > 2)\n\t\tassign tmp_o = { {N{~le_o[ES+Bs]}}, le_o[ES+Bs], e_o, DSR_left_out[N-2:ES-2], |DSR_left_out[ES-3:0]};\n\telse \n\t\tassign tmp_o = { {N{~le_o[ES+Bs]}}, le_o[ES+Bs], e_o, DSR_left_out[N-2:0], {3-ES{1'b0}} };\n\nendgenerate\n\n//Including/Pushing Regime bits in Exponent-Mantissa Packing\nwire [3*N-1+3:0] tmp1_o;\nDSR_right_N_S #(.N(3*N+3), .S(Bs)) dsr2 (.a({tmp_o,{N{1'b0}}}), .b(r_o), .c(tmp1_o));\n\n//Rounding RNE : ulp_add = G.(R + S) + L.G.(~(R+S))\nwire L = tmp1_o[N+4], G = tmp1_o[N+3], R = tmp1_o[N+2], St = |tmp1_o[N+1:0],\n     ulp = ((G & (R | St)) | (L & G & ~(R | St)));\nwire [N-1:0] rnd_ulp = {{N-1{1'b0}},ulp};\n\nwire [N:0] tmp1_o_rnd_ulp;\na_add_N #(.N(N)) uut_add_ulp (tmp1_o[2*N-1+3:N+3], rnd_ulp, tmp1_o_rnd_ulp);\nwire [N-1:0] tmp1_o_rnd = (r_o < N-ES-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];\n\n//Final Output\nwire [N-1:0] tmp1_oN = ls ? -tmp1_o_rnd : tmp1_o_rnd;\nassign out = inf|zero|(~DSR_left_out[N-1]) ? {inf,{N-1{1'b0}}} : {ls, tmp1_oN[N-1:1]};\n\nendmodule\n\n////////////////\n// Multiplier //\n////////////////\nmodule posit_mult(in1, in2, out);\n\nfunction [31:0] log2;\ninput reg [31:0] value;\n\tbegin\n\tvalue = value-1;\n\tfor (log2=0; value>0; log2=log2+1)\n        \tvalue = value>>1;\n      \tend\nendfunction\n\nparameter N = 16;\nparameter Bs = log2(N); \nparameter ES = 1;\n\ninput [N-1:0] in1, in2;\noutput [N-1:0] out;\nwire inf, zero;\n\nwire s1 = in1[N-1];\nwire s2 = in2[N-1];\nwire zero_tmp1 = |in1[N-2:0];\nwire zero_tmp2 = |in2[N-2:0];\nwire inf1 = in1[N-1] & (~zero_tmp1),\n\tinf2 = in2[N-1] & (~zero_tmp2);\nwire zero1 = ~(in1[N-1] | zero_tmp1),\n\tzero2 = ~(in2[N-1] | zero_tmp2);\nassign inf = inf1 | inf2,\n\tzero = zero1 & zero2;\n\n//Data Extraction\nwire rc1, rc2;\nwire [Bs-1:0] regime1, regime2;\nwire [ES-1:0] e1, e2;\nwire [N-ES-1:0] mant1, mant2;\nwire [N-1:0] xin1 = s1 ? -in1 : in1;\nwire [N-1:0] xin2 = s2 ? -in2 : in2;\ndata_extract_v1 #(.N(N),.ES(ES)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1));\ndata_extract_v1 #(.N(N),.ES(ES)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2));\n\nwire [N-ES:0] m1 = {zero_tmp1,mant1}, \n\tm2 = {zero_tmp2,mant2};\n\n//Sign, Exponent and Mantissa Computation\nwire mult_s = s1 ^ s2;\n\nwire [2*(N-ES)+1:0] mult_m = m1*m2;\nwire mult_m_ovf = mult_m[2*(N-ES)+1];\nwire [2*(N-ES)+1:0] mult_mN = ~mult_m_ovf ? mult_m << 1'b1 : mult_m;\n\nwire [Bs+1:0] r1 = rc1 ? {2'b0,regime1} : -regime1;\nwire [Bs+1:0] r2 = rc2 ? {2'b0,regime2} : -regime2;\nwire [Bs+ES+1:0] mult_e;\nm_add_N_Cin #(.N(Bs+ES+1)) uut_add_exp ({r1,e1}, {r2,e2}, mult_m_ovf, mult_e);\n\n//Exponent and Regime Computation\nwire [ES-1:0] e_o;\nwire [Bs:0] r_o;\nm_reg_exp_op #(.ES(ES), .Bs(Bs)) uut_reg_ro (mult_e[ES+Bs+1:0], e_o, r_o);\n\n//Exponent, Mantissa and GRS Packing\nwire [2*N-1+3:0]tmp_o = {{N{~mult_e[ES+Bs+1]}},mult_e[ES+Bs+1],e_o,mult_mN[2*(N-ES):2*(N-ES)-(N-ES-1)+1], mult_mN[2*(N-ES)-(N-ES-1):2*(N-ES)-(N-ES-1)-1], |mult_mN[2*(N-ES)-(N-ES-1)-2:0] }; \n\n\n//Including Regime bits in Exponent-Mantissa Packing\nwire [3*N-1+3:0] tmp1_o;\nDSR_right_N_S #(.N(3*N+3), .S(Bs+1)) dsr2 (.a({tmp_o,{N{1'b0}}}), .b(r_o[Bs] ? {Bs{1'b1}} : r_o), .c(tmp1_o));\n\n//Rounding RNE : ulp_add = G.(R + S) + L.G.(~(R+S))\nwire L = tmp1_o[N+4], G = tmp1_o[N+3], R = tmp1_o[N+2], St = |tmp1_o[N+1:0],\n     ulp = ((G & (R | St)) | (L & G & ~(R | St)));\nwire [N-1:0] rnd_ulp = {{N-1{1'b0}},ulp};\n\nwire [N:0] tmp1_o_rnd_ulp;\nm_add_N #(.N(N)) uut_add_ulp (tmp1_o[2*N-1+3:N+3], rnd_ulp, tmp1_o_rnd_ulp);\nwire [N-1:0] tmp1_o_rnd = (r_o < N-ES-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];\n\n\n//Final Output\nwire [N-1:0] tmp1_oN = mult_s ? -tmp1_o_rnd : tmp1_o_rnd;\nassign out = inf|zero|(~mult_mN[2*(N-ES)+1]) ? {inf,{N-1{1'b0}}} : {mult_s, tmp1_oN[N-1:1]};\nendmodule\n\n\n///////////////////////////////////////////////\n// Multiply by hard-coded constant in (16,1) //\n/// dt = 0x8000 \t\t\t\t\t         //\n///////////////////////////////////////////////\nmodule posit_dt_mult(in1, out);\n\nfunction [31:0] log2;\ninput reg [31:0] value;\n\tbegin\n\tvalue = value-1;\n\tfor (log2=0; value>0; log2=log2+1)\n        \tvalue = value>>1;\n      \tend\nendfunction\n\nparameter N = 16;\nparameter Bs = log2(N); \nparameter ES = 1;\n\ninput [N-1:0] in1;\noutput [N-1:0] out;\n\nwire s1 = in1[N-1];\nwire s2; //\n\nassign s2 = 0;\n\nwire zero_tmp1 = |in1[N-2:0];\nwire inf = in1[N-1] & (~zero_tmp1);\nwire zero = ~(in1[N-1] | zero_tmp1);\n\n//Data Extraction\nwire rc1, rc2;\nwire [Bs-1:0] regime1, regime2;\nwire [ES-1:0] e1, e2;\nwire [N-ES-1:0] mant1, mant2;\nwire [N-1:0] xin1 = s1 ? -in1 : in1;\nwire [N-1:0] xin2;\n\ndata_extract_v1 #(.N(N),.ES(ES)) uut_de1(.in(xin1), .rc(rc1), .regime(regime1), .exp(e1), .mant(mant1));\n\n// data_extract_v1 #(.N(N),.ES(ES)) uut_de2(.in(xin2), .rc(rc2), .regime(regime2), .exp(e2), .mant(mant2));\nassign regime2 = 4;\nassign xin2 = 16'h0400;\nassign rc2 = 0;\nassign e2 = 0;\nassign mant2 = 0;\n\nwire [N-ES:0] m1 = {zero_tmp1,mant1};\nwire [N-ES:0] m2;\n\nassign m2 = 16'h8000;\n\n//Sign, Exponent and Mantissa Computation\nwire mult_s = s1;\n\nwire [2*(N-ES)+1:0] mult_m = m1*m2;\nwire mult_m_ovf = mult_m[2*(N-ES)+1];\nwire [2*(N-ES)+1:0] mult_mN = ~mult_m_ovf ? mult_m << 1'b1 : mult_m;\n\nwire [Bs+1:0] r1 = rc1 ? {2'b0,regime1} : -regime1;\nwire [Bs+1:0] r2 = rc2 ? {2'b0,regime2} : -regime2;\nwire [Bs+ES+1:0] mult_e;\nm_add_N_Cin #(.N(Bs+ES+1)) uut_add_exp ({r1,e1}, {r2,e2}, mult_m_ovf, mult_e);\n\n//Exponent and Regime Computation\nwire [ES-1:0] e_o;\nwire [Bs:0] r_o;\nm_reg_exp_op #(.ES(ES), .Bs(Bs)) uut_reg_ro (mult_e[ES+Bs+1:0], e_o, r_o);\n\n//Exponent, Mantissa and GRS Packing\nwire [2*N-1+3:0]tmp_o = {{N{~mult_e[ES+Bs+1]}},mult_e[ES+Bs+1],e_o,mult_mN[2*(N-ES):2*(N-ES)-(N-ES-1)+1], mult_mN[2*(N-ES)-(N-ES-1):2*(N-ES)-(N-ES-1)-1], |mult_mN[2*(N-ES)-(N-ES-1)-2:0] }; \n\n\n//Including Regime bits in Exponent-Mantissa Packing\nwire [3*N-1+3:0] tmp1_o;\nDSR_right_N_S #(.N(3*N+3), .S(Bs+1)) dsr2 (.a({tmp_o,{N{1'b0}}}), .b(r_o[Bs] ? {Bs{1'b1}} : r_o), .c(tmp1_o));\n\n//Rounding RNE : ulp_add = G.(R + S) + L.G.(~(R+S))\nwire L = tmp1_o[N+4], G = tmp1_o[N+3], R = tmp1_o[N+2], St = |tmp1_o[N+1:0],\n     ulp = ((G & (R | St)) | (L & G & ~(R | St)));\nwire [N-1:0] rnd_ulp = {{N-1{1'b0}},ulp};\n\nwire [N:0] tmp1_o_rnd_ulp;\nm_add_N #(.N(N)) uut_add_ulp (tmp1_o[2*N-1+3:N+3], rnd_ulp, tmp1_o_rnd_ulp);\nwire [N-1:0] tmp1_o_rnd = (r_o < N-ES-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];\n\n\n//Final Output\nwire [N-1:0] tmp1_oN = mult_s ? -tmp1_o_rnd : tmp1_o_rnd;\nassign out = inf|zero|(~mult_mN[2*(N-ES)+1]) ? {inf,{N-1{1'b0}}} : {mult_s, tmp1_oN[N-1:1]};\nendmodule\n\n\n/////////////////////////////\n// Adder auxiliary modules //\n////////////////////////////\n\n\n/////////////////\nmodule a_sub_N (a,b,c);\nparameter N=10;\ninput [N-1:0] a,b;\noutput [N:0] c;\nwire [N:0] ain = {1'b0,a};\nwire [N:0] bin = {1'b0,b};\na_sub_N_in #(.N(N)) s1 (ain,bin,c);\nendmodule\n\n/////////////////////////\nmodule a_add_N (a,b,c);\nparameter N=10;\ninput [N-1:0] a,b;\noutput [N:0] c;\nwire [N:0] ain = {1'b0,a};\nwire [N:0] bin = {1'b0,b};\na_add_N_in #(.N(N)) a1 (ain,bin,c);\nendmodule\n\n/////////////////////////\nmodule a_sub_N_in (a,b,c);\nparameter N=10;\ninput [N:0] a,b;\noutput [N:0] c;\nassign c = a - b;\nendmodule\n\n/////////////////////////\nmodule a_add_N_in (a,b,c);\nparameter N=10;\ninput [N:0] a,b;\noutput [N:0] c;\nassign c = a + b;\nendmodule\n\n/////////////////////////\nmodule a_add_sub_N (op,a,b,c);\nparameter N=10;\ninput op;\ninput [N-1:0] a,b;\noutput [N:0] c;\nwire [N:0] c_add, c_sub;\n\na_add_N #(.N(N)) a11 (a,b,c_add);\na_sub_N #(.N(N)) s11 (a,b,c_sub);\nassign c = op ? c_add : c_sub;\nendmodule\n\n/////////////////////////\nmodule a_abs_regime (rc, regime, regime_N);\nparameter N = 10;\ninput rc;\ninput [N-1:0] regime;\noutput [N:0] regime_N;\n\nassign regime_N = rc ? {1'b0,regime} : -{1'b0,regime};\nendmodule\n\n/////////////////////////\nmodule a_reg_exp_op (exp_o, e_o, r_o);\nparameter ES=3;\nparameter Bs=5;\ninput [ES+Bs:0] exp_o;\noutput [ES-1:0] e_o;\noutput [Bs-1:0] r_o;\n\nassign e_o = exp_o[ES-1:0];\n\nwire [ES+Bs:0] exp_oN_tmp;\nconv_2c #(.N(ES+Bs)) uut_conv_2c1 (~exp_o[ES+Bs:0],exp_oN_tmp);\nwire [ES+Bs:0] exp_oN = exp_o[ES+Bs] ? exp_oN_tmp[ES+Bs:0] : exp_o[ES+Bs:0];\nassign r_o = (~exp_o[ES+Bs] || |(exp_oN[ES-1:0])) ? exp_oN[ES+Bs-1:ES] + 1 : exp_oN[ES+Bs-1:ES];\nendmodule\n\n\n///////////////////////////////////\n// Multiplier auxiliary modules //\n/////////////////////////////////\nmodule m_add_N (a,b,c);\nparameter N=10;\ninput [N-1:0] a,b;\noutput [N:0] c;\nassign c = {1'b0,a} + {1'b0,b};\nendmodule\n\n/////////////////////////\nmodule m_add_N_Cin (a,b,cin,c);\nparameter N=10;\ninput [N:0] a,b;\ninput cin;\noutput [N:0] c;\nassign c = a + b + cin;\nendmodule\n\n/////////////////////////\nmodule m_reg_exp_op (exp_o, e_o, r_o);\nparameter ES=3;\nparameter Bs=5;\ninput [ES+Bs+1:0] exp_o;\noutput [ES-1:0] e_o;\noutput [Bs:0] r_o;\n\nassign e_o = exp_o[ES-1:0];\n\nwire [ES+Bs:0] exp_oN_tmp;\nconv_2c #(.N(ES+Bs)) uut_conv_2c1 (~exp_o[ES+Bs:0],exp_oN_tmp);\nwire [ES+Bs:0] exp_oN = exp_o[ES+Bs+1] ? exp_oN_tmp[ES+Bs:0] : exp_o[ES+Bs:0];\n\nassign r_o = (~exp_o[ES+Bs+1] || |(exp_oN[ES-1:0])) ? exp_oN[ES+Bs:ES] + 1 : exp_oN[ES+Bs:ES];\nendmodule\n\n//////////////////////\n// General modules //\n////////////////////\nmodule data_extract_v1(in, rc, regime, exp, mant);\nfunction [31:0] log2;\ninput reg [31:0] value;\n\tbegin\n\tvalue = value-1;\n\tfor (log2=0; value>0; log2=log2+1)\n        \tvalue = value>>1;\n      \tend\nendfunction\n\nparameter N=16;\nparameter Bs=log2(N);\nparameter ES = 2;\n\ninput [N-1:0] in;\noutput rc;\noutput [Bs-1:0] regime;\noutput [ES-1:0] exp;\noutput [N-ES-1:0] mant;\n\nwire [N-1:0] xin = in;\nassign rc = xin[N-2];\n\nwire [N-1:0] xin_r = rc ? ~xin : xin;\n\nwire [Bs-1:0] k;\nLOD_N #(.N(N)) xinst_k(.in({xin_r[N-2:0],rc^1'b0}), .out(k));\n\nassign regime = rc ? k-1 : k;\n\nwire [N-1:0] xin_tmp;\nDSR_left_N_S #(.N(N), .S(Bs)) ls (.a({xin[N-3:0],2'b0}),.b(k),.c(xin_tmp));\n\nassign exp= xin_tmp[N-1:N-ES];\nassign mant= xin_tmp[N-ES-1:0];\n\nendmodule\n\n/////////////////////////\nmodule add_1 (a,mant_ovf,c);\nparameter N=10;\ninput [N:0] a;\ninput mant_ovf;\noutput [N:0] c;\nassign c = a + mant_ovf;\nendmodule\n\n/////////////////////////\nmodule conv_2c (a,c);\nparameter N=10;\ninput [N:0] a;\noutput [N:0] c;\nassign c = a + 1'b1;\nendmodule\n\n/////////////////////////\nmodule DSR_left_N_S(a,b,c);\n        parameter N=16;\n        parameter S=4;\n        input [N-1:0] a;\n        input [S-1:0] b;\n        output [N-1:0] c;\n\nwire [N-1:0] tmp [S-1:0];\nassign tmp[0]  = b[0] ? a << 7'd1  : a; \ngenvar i;\ngenerate\n\tfor (i=1; i<S; i=i+1)begin:loop_blk\n\t\tassign tmp[i] = b[i] ? tmp[i-1] << 2**i : tmp[i-1];\n\tend\nendgenerate\nassign c = tmp[S-1];\n\nendmodule\n\n/////////////////////////\nmodule DSR_right_N_S(a,b,c);\n        parameter N=16;\n        parameter S=4;\n        input [N-1:0] a;\n        input [S-1:0] b;\n        output [N-1:0] c;\n\nwire [N-1:0] tmp [S-1:0];\nassign tmp[0]  = b[0] ? a >> 7'd1  : a; \ngenvar i;\ngenerate\n\tfor (i=1; i<S; i=i+1)begin:loop_blk\n\t\tassign tmp[i] = b[i] ? tmp[i-1] >> 2**i : tmp[i-1];\n\tend\nendgenerate\nassign c = tmp[S-1];\n\nendmodule\n\n/////////////////////////\nmodule LOD_N (in, out);\n\n  function [31:0] log2;\n    input reg [31:0] value;\n    begin\n      value = value-1;\n      for (log2=0; value>0; log2=log2+1)\n\tvalue = value>>1;\n    end\n  endfunction\n\nparameter N = 64;\nparameter S = log2(N); \ninput [N-1:0] in;\noutput [S-1:0] out;\n\nwire vld;\nLOD #(.N(N)) l1 (in, out, vld);\nendmodule\n\n/////////////////////////\nmodule LOD (in, out, vld);\n\n  function [31:0] log2;\n    input reg [31:0] value;\n    begin\n      value = value-1;\n      for (log2=0; value>0; log2=log2+1)\n\tvalue = value>>1;\n    end\n  endfunction\n\n\nparameter N = 64;\nparameter S = log2(N);\n\n   input [N-1:0] in;\n   output [S-1:0] out;\n   output vld;\n\n  generate\n    if (N == 2)\n      begin\n\tassign vld = |in;\n\tassign out = ~in[1] & in[0];\n      end\n    else if (N & (N-1))\n      //LOD #(1<<S) LOD ({1<<S {1'b0}} | in,out,vld);\n      LOD #(1<<S) LOD ({in,{((1<<S) - N) {1'b0}}},out,vld);\n    else\n      begin\n\twire [S-2:0] out_l, out_h;\n\twire out_vl, out_vh;\n\tLOD #(N>>1) l(in[(N>>1)-1:0],out_l,out_vl);\n\tLOD #(N>>1) h(in[N-1:N>>1],out_h,out_vh);\n\tassign vld = out_vl | out_vh;\n\tassign out = out_vh ? {1'b0,out_h} : {out_vl,out_l};\n      end\n  endgenerate\nendmodule\n\n", "mask_idx": {"conditional_statement": [[3268, 3402], [5561, 5608], [3318, 3402]], "blocking_assignment": [[20474, 20491], [5914, 5931], [18280, 18297], [20118, 20135], [13087, 13104]], "module_program_interface_instantiation": [[8485, 8572], [5354, 5436], [1625, 1751]], "always_construct": [[5530, 5613], [3221, 3407]], "ansi_port_declaration": [[5781, 5796], [344, 424], [15851, 15854], [5786, 5796], [17632, 17642]], "continuous_assign": [[9083, 9184], [8079, 8116], [7813, 7838]], "parameter_declaration": [[16593, 16610], [19597, 19612], [5999, 6016], [16191, 16206], [5974, 5998], [10300, 10317], [621, 657], [18903, 18918], [13147, 13171], [19621, 19635], [18338, 18359], [18322, 18337], [20177, 20200], [17659, 17674], [3838, 3855], [10318, 10342], [15653, 15668], [16060, 16075], [19215, 19229], [5956, 5973], [20516, 20533]], "nonblocking_assignment": [[2871, 2944], [2015, 2043], [2631, 2643]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1625, 1751], [3917, 4000], [4001, 4097], [4098, 4196], [4397, 4520], [4521, 4630], [4700, 4796], [4797, 4898], [5354, 5436], [5439, 5527], [6562, 6666], [6667, 6771], [7442, 7497], [7498, 7553], [7554, 7617], [7918, 8008], [8179, 8252], [8385, 8434], [8485, 8572], [8747, 8824], [8825, 8892], [8932, 9002], [9385, 9470], [9722, 9798], [10906, 11010], [11011, 11115], [11521, 11599], [11671, 11745], [12054, 12164], [12416, 12492], [13558, 13662], [14280, 14358], [14430, 14504], [14813, 14923], [15175, 15251], [15758, 15793], [15960, 15995], [16413, 16446], [16447, 16480], [16952, 17015], [17797, 17860], [18580, 18641], [18696, 18771], [20250, 20281], [20800, 20853], [20926, 20969], [20971, 21012]], "continuous_assign": [[755, 774], [776, 800], [802, 826], [828, 852], [921, 943], [962, 985], [987, 1008], [1010, 1035], [1037, 1058], [1060, 1085], [1087, 1108], [1311, 1328], [3410, 3469], [4269, 4328], [4352, 4395], [5615, 5631], [6321, 6369], [7764, 7804], [7813, 7838], [8079, 8116], [8125, 8147], [9083, 9184], [9194, 9284], [9957, 10043], [10665, 10713], [12656, 12748], [13264, 13278], [13772, 13791], [13792, 13815], [13816, 13831], [13832, 13846], [13847, 13864], [13923, 13944], [15415, 15507], [16109, 16126], [16240, 16257], [16481, 16511], [16667, 16721], [16896, 16923], [17093, 17189], [17382, 17413], [17543, 17566], [17741, 17768], [17941, 18035], [18501, 18522], [18643, 18672], [18773, 18803], [18804, 18835], [18966, 18990], [19097, 19117], [19333, 19373], [19432, 19483], [19501, 19521], [19739, 19779], [19838, 19889], [19907, 19927], [20658, 20675], [20677, 20705], [21014, 21043], [21045, 21097]], "blocking_assignment": [[5852, 5868], [5914, 5931], [10196, 10212], [10258, 10275], [13025, 13041], [13087, 13104], [18218, 18234], [18280, 18297], [20059, 20075], [20118, 20135], [20415, 20431], [20474, 20491]], "nonblocking_assignment": [[1857, 1873], [1877, 1893], [2015, 2043], [2215, 2239], [2478, 2506], [2631, 2643], [2684, 2705], [2785, 2835], [2871, 2944], [3022, 3050], [3118, 3131], [3170, 3207], [3289, 3308], [3339, 3402], [5576, 5585], [5596, 5608]], "case_statement": [], "conditional_statement": [[1836, 1899], [2612, 2841], [2653, 2841], [3001, 3050], [3098, 3137], [3140, 3213], [3244, 3407], [3268, 3402], [3318, 3402], [5561, 5608]], "always_construct": [[1805, 1904], [1993, 2043], [2193, 2239], [2456, 2506], [2581, 2846], [2849, 2944], [2979, 3050], [3068, 3218], [3221, 3407], [5530, 5613]], "parameter_declaration": [[621, 657], [659, 688], [3820, 3837], [3838, 3855], [4987, 5004], [5006, 5023], [5956, 5973], [5974, 5998], [5999, 6016], [10300, 10317], [10318, 10342], [10343, 10360], [13129, 13146], [13147, 13171], [13172, 13189], [15653, 15668], [15855, 15870], [16060, 16075], [16191, 16206], [16326, 16341], [16593, 16610], [16798, 16813], [16814, 16829], [17331, 17346], [17483, 17498], [17643, 17658], [17659, 17674], [18322, 18337], [18338, 18359], [18360, 18377], [18903, 18918], [19050, 19065], [19191, 19206], [19215, 19229], [19597, 19612], [19621, 19635], [20159, 20176], [20177, 20200], [20516, 20533], [20534, 20556]], "ansi_port_declaration": [[136, 183], [188, 236], [241, 287], [292, 339], [344, 424], [429, 517], [522, 558], [563, 616], [3581, 3600], [3605, 3639], [3644, 3699], [3661, 3699], [3704, 3749], [3723, 3749], [3754, 3795], [4957, 4985], [4962, 4985], [4969, 4985], [4974, 4985], [4981, 4985], [5781, 5796], [5786, 5796], [5791, 5796], [10125, 10140], [10130, 10140], [10135, 10140], [12959, 12969], [12964, 12969], [15645, 15652], [15647, 15652], [15649, 15652], [15847, 15854], [15849, 15854], [15851, 15854], [16052, 16059], [16054, 16059], [16056, 16059], [16183, 16190], [16185, 16190], [16187, 16190], [16315, 16325], [16318, 16325], [16320, 16325], [16322, 16325], [16570, 16592], [16574, 16592], [16582, 16592], [16780, 16797], [16787, 16797], [16792, 16797], [17323, 17330], [17325, 17330], [17327, 17330], [17471, 17482], [17473, 17482], [17475, 17482], [17479, 17482], [17625, 17642], [17632, 17642], [17637, 17642], [18136, 18163], [18140, 18163], [18144, 18163], [18152, 18163], [18157, 18163], [18888, 18902], [18890, 18902], [18899, 18902], [19044, 19049], [19046, 19049], [19175, 19182], [19177, 19182], [19179, 19182], [19581, 19588], [19583, 19588], [19585, 19588], [19980, 19989], [19984, 19989], [20331, 20345], [20335, 20345], [20340, 20345]]}}
{"sample_i": "afasolino-tt06_posit", "topmodule": "tt_um_afasolino", "code": "/*\nBased on paper: \nR. Murillo, A. A. Del Barrio and G. Botella, \"Customized Posit Adders and Multipliers using the FloPoCo Core Generator,\" 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, \ndoi: 10.1109/ISCAS45731.2020.9180771.\n*/\nmodule add #(parameter N=16) (\n   input wire  i_s_1,\n   input wire [N-11:0]  i_sf_1,\n   input wire [N-5:0] i_mant_1,\n   input wire  i_nzn_1,\n   input wire  i_s_2,\n   input wire [N-11:0]  i_sf_2,\n   input wire [N-5:0] i_mant_2,\n   input wire  i_nzn_2,\n   output wire o_s,\n   output wire [N-10:0]o_sf,\n   output wire [N-5:0] o_mant,\n   output wire o_guard,\n   output wire o_sticky,\n   output wire o_nzn\n);\n\n \n  wire X_not_zero ;\n  wire X_nar ;\n  wire Y_not_zero ;\n  wire Y_nar ;\n  wire check_larger ;\n  wire [$clog2(N)+1:0] larger_number ;\n  wire [$clog2(N)+1:0] smallest_number ;\n  wire [N-3:0] larger_mant ;\n  wire [N-3:0] smaller_mant ;\n  wire [$clog2(N)+1:0] offset;\n  wire shift_saturate;\n  wire [$clog2(N):0]mant_offset ;\n  wire [N-1:0]input_shifter ;\n  wire pad_bit;\n  wire [N-1:0] shifted_mant ;\n  wire stk_tmp ;\n  wire [N-3:0] smaller_mant_sh;\n  wire grd_tmp ;\n  wire rnd_tmp ;\n  wire [N-2:0]add_mant;\n  wire grd_bit;\n  wire rnd_bit;\n  wire stk_bit;\n  wire count_type;\n  wire [N:0]add_mant_shift ;\n  wire [$clog2(N):0]count ;\n  wire [(N):0]norm_mant_tmp;\n  wire [N-10:0]add_sf ;\n  wire is_not_zero ;\n  wire is_nar;\n  wire Xi_nzn_2;\n\n  assign X_not_zero = i_s_1 | i_nzn_1;\n  assign X_nar      = i_s_1 & ~(i_nzn_1);\n  assign Y_not_zero = i_s_2 | i_nzn_2;\n  assign Y_nar      = i_s_2 & ~(i_nzn_2);\n\n  assign check_larger    = (($signed(i_sf_1))>($signed(i_sf_2))) ?  1 : 0;\n  assign larger_number    = (check_larger) ? i_sf_1 : i_sf_2;\n  assign smallest_number   = (check_larger) ? i_sf_2 : i_sf_1;\n  assign larger_mant  = (check_larger) ? {i_s_1 , (~i_s_1 & X_not_zero) ,i_mant_1} : {i_s_2,(~i_s_2 & Y_not_zero),i_mant_2};\n  assign smaller_mant = (check_larger) ? {i_s_2,(~i_s_2 & Y_not_zero),i_mant_2} :{i_s_1 , (~i_s_1 & X_not_zero) ,i_mant_1};\n\n  assign offset         = larger_number - smallest_number;\n  assign shift_saturate = (!offset[5]) ? 0 : 1;\n  assign mant_offset    = (shift_saturate) ? 16 : offset[4:0];\n\n  assign input_shifter = {smaller_mant, 2'b00};\n\n  assign pad_bit = smaller_mant[N-3];\n  right_shifter_sticky_16 #(.N(N)) inst_right_shifter_sticky_16_2\n    (  .i_s     (mant_offset),\n      .i_in    (input_shifter),\n      .i_padbit(pad_bit),\n      .o_r     (shifted_mant),\n      .o_sticky(stk_tmp)\n    );\n  assign smaller_mant_sh = shifted_mant[15:2];\n  assign grd_tmp         = shifted_mant[1];\n  assign rnd_tmp         = shifted_mant[0];\n\n\n\n  assign add_mant = {larger_mant[13], larger_mant} + {smaller_mant_sh[13], smaller_mant_sh};\n  assign grd_bit  = grd_tmp;\n  assign rnd_bit  = rnd_tmp;\n  assign stk_bit  = stk_tmp;\n\n  assign count_type     = add_mant[14];\n  assign add_mant_shift = {add_mant[13:0], grd_bit , rnd_bit , stk_bit};\n\n  normalizer_16 #(.N(N)) inst_normalizer_16\n    ( .i_ozb  (count_type),\n      .i_in   (add_mant_shift),\n      .o_count(count),\n      .o_r  (norm_mant_tmp)\n    );\n\n  assign add_sf = {larger_number[5] , larger_number} - ({2'b00 , count}) + 1;\n\n  assign is_not_zero = (count==5'b11111) ? count_type : 1;\n  assign is_nar      = X_nar | Y_nar;\n  assign Xi_nzn_2      = is_not_zero & ~(is_nar);\n  assign o_s        = is_nar | (is_not_zero & add_mant[14]);\n  assign o_mant   = norm_mant_tmp[N-1:4];\n  assign o_guard         = norm_mant_tmp[3];\n  assign o_sticky         = norm_mant_tmp[2] | norm_mant_tmp[1] | norm_mant_tmp[0];\n  assign o_sf =  add_sf;\n  assign o_nzn = Xi_nzn_2;\n\n\nendmodule\n\n\n/*\nBased on paper: \nR. Murillo, A. A. Del Barrio and G. Botella, \"Customized Posit Adders and Multipliers using the FloPoCo Core Generator,\" 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, \ndoi: 10.1109/ISCAS45731.2020.9180771.\n*/\n\n\nmodule data_posit_encoder #( parameter N=16) (\n  input wire i_s ,\n  input wire [N-10:0]i_sf ,\n  input wire [N-5:0]i_mant ,\n  input wire i_guard ,\n  input wire i_sticky ,\n  input wire i_nzn ,\n  output wire [N-1:0] o_r\n);\n\n  wire rc ;\n  wire [$clog2(N):0]rcVect;\n  wire [$clog2(N):0] k ;\n  wire sgnVect ;\n  wire exp ;\n  wire ovf ;\n  wire [$clog2(N)-1:0] regValue;\n  wire regNeg ;\n  wire padBit ;\n  wire [N-2:0]inputShifter ;\n  wire [N-2:0]shiftedPosit ;\n  wire stkBit ;\n  wire [N-2:0] unroundedPosit ;\n  wire lsb ;\n  wire rnd ;\n  wire stk ;\n  wire round;\n  wire [N-2:0]roundedPosit ;\n  wire [N-2:0]unsignedPosit ;\n\n\n  assign rc      = i_sf[N-10];\n  assign rcVect  = {5{rc}};\n  assign k       =  i_sf[5:1] ^ rcVect;\n  assign sgnVect = i_s;\n  assign exp = i_sf[0] ^ sgnVect;\n\n  assign ovf      = (k>13) ? 1 :0;\n  assign regValue = (!ovf) ? k[3:0] : 4'b1110;\n\n  assign regNeg       = i_s ^ rc;\n  assign padBit       = ~(regNeg);\n  assign inputShifter = {regNeg, exp , i_mant, i_guard};\n  right_shifter_sticky_18 #(.N(N))  inst_right_shifter_sticky_18\n    ( .i_s(regValue),\n      .i_in(inputShifter),\n      .i_padbit(padBit),\n      .o_r     (shiftedPosit),\n      .o_sticky(stkBit)\n    );\n  \n  assign unroundedPosit = {padBit, shiftedPosit[N-2:1]};\n\n  assign lsb = shiftedPosit[1];\n  assign rnd = shiftedPosit[0];\n  assign stk = stkBit | i_sticky;\n  assign round = rnd & (lsb | stk | ovf);\n  assign roundedPosit = unroundedPosit + {14'd0,round};\n  \n  assign unsignedPosit = (i_nzn) ? roundedPosit : 0;\n  assign o_r = { i_s  ,unsignedPosit};\n\n\n\nendmodule\n\n\n\nmodule Fixed16toPosit16(\n    input [15:0]    fixed_number_input,\n    output [3:0]    regime_value,\n    output          exponent,\n    output wire [11:0]   mantissa,\n    output          Q,\n    output          sign\n    );\nwire [15:0] fixed_number,fixed_numberaux, fixed_number_neg;\n\n// 2's complement to extract value and sign of the fixed point input\nassign fixed_numberaux = {(16){fixed_number_input[15]}} ;\nassign fixed_number_neg = fixed_number_input ^ fixed_numberaux ;\nassign fixed_number = fixed_number_neg + {15'b000000000000000, fixed_number_input[15]};\nassign sign =  fixed_number_input[15];\nreg [11:0] mantissa_compl;\nwire [3:0] xaux,x;\nwire [2:0] xaux2;\nwire first_regime_bit;\n//\n//  zlc value       regime value\n//      1,2     ->      2\n//      3,4     ->      3\n//      5,6     ->      4\n//      7,8     ->      5\n//      9,10    ->      6\n//      11,12   ->      7\n//      13,14   ->      8\n//      15      ->      9\n//  \n//  regime value -  2   =   {y2,y1,y0}\n//\n//  x3  x2  x1  x0  |   y2  y1  y0\n//  0   0   0   0   |   0   0   0\n//  0   0   0   1   |   0   0   0\n//  0   0   1   0   |   0   0   1\n//  0   0   1   1   |   0   0   1\n//  0   1   0   0   |   0   1   0\n//  0   1   0   1   |   0   1   0\n//  0   1   1   0   |   0   1   1\n//  0   1   1   1   |   0   1   1\n//  1   0   0   0   |   1   0   0\n//  1   0   0   1   |   1   0   0\n//  1   0   1   0   |   1   0   1\n//  1   0   1   1   |   1   0   1\n//  1   1   0   0   |   1   1   0\n//  1   1   0   1   |   1   1   0\n//  1   1   1   0   |   1   1   1\n//  1   1   1   1   |   1   1   1\n//\n\nLeadingZeroCounter_16b LeadingZeroCounter_16b(\n    .x(fixed_number),\n    .count(x),\n    .Q(Q)\n    );\n    \nassign xaux = (sign & first_regime_bit)? x : x-1;\nassign xaux2 = ~(xaux[3:1]);\nassign regime_value = {1'b1,xaux2};\nassign exponent = (first_regime_bit ) ? ~x[0]:x[0];\nassign first_regime_bit = (fixed_number_input[14]==0 && sign==1) ? 1 : 0;\nassign mantissa = (first_regime_bit) ? -mantissa_compl : mantissa_compl;\nalways @(*)\ncase (x)\n      4'b0001: begin\n                  mantissa_compl = fixed_number [13:2];  //\n               end\n      4'b0010: begin\n                  mantissa_compl = fixed_number [12:1];  //\n               end\n      4'b0011: begin\n                  mantissa_compl = fixed_number [11:0];  //\n               end\n      4'b0100: begin\n                  mantissa_compl = {fixed_number [10:0],1'b0};  //\n               end\n      4'b0101: begin\n                  mantissa_compl = {fixed_number [9:0],2'b00};  //\n               end\n      4'b0110: begin\n                  mantissa_compl = {fixed_number [8:0],3'b000};  //\n               end\n      4'b0111: begin\n                  mantissa_compl = {fixed_number [7:0],4'b0000};  //\n               end\n      4'b1000: begin\n                  mantissa_compl = {fixed_number [6:0],5'b00000};  //\n               end\n      4'b1001: begin\n                  mantissa_compl = {fixed_number [5:0],6'b000000};  //\n               end\n      4'b1010: begin\n                  mantissa_compl = {fixed_number [4:0],7'b0000000};  //\n               end\n      4'b1011: begin\n                  mantissa_compl = {fixed_number [3:0],8'b00000000};  //\n               end\n      4'b1100: begin\n                  mantissa_compl = {fixed_number [2:0],9'b000000000};  //\n               end\n      4'b1101: begin\n                  mantissa_compl = {fixed_number [1:0],10'b0000000000};  //\n               end\n      4'b1110: begin\n                  mantissa_compl = {fixed_number [0],11'b00000000000};  //\n                end\n      default: begin\n                  mantissa_compl = {12'b00000000000};  //\n                end\n   endcase\n\t\t\t\t\nendmodule\n\n\n\nmodule LeadingZeroCounter_16b(\n    input  wire [15:0] x,\n    output wire [3:0] count,\n    output wire Q\n    );\n\nwire [3:0] auxa;\nwire [7:0] auxz;\nwire [1:0] auxcount;\n\ngenvar k;\ngenerate\n  for (k=0; k < 4; k=k+1)\n  begin: NLC_generation\n     NLC_16b NLC (.x(x[15-4*k : 12-4*k]),\n              .a(auxa[k]),\n              .z(auxz[2*k+1 : 2*k])\n              );\n  end\nendgenerate\n\nBNE_16b BNEncoder (.a(auxa), \n               .Q(Q),\n               .y(auxcount[1 : 0]));\n\nassign count[3 : 2] = auxcount;\n\nMux_LZC_16b Mux (.i0(auxz[1:0]), \n             .i1(auxz[3:2]), \n             .i2(auxz[5:4]), \n             .i3(auxz[7:6]), \n             .s(auxcount),\n             .o(count[1 : 0])\n             );\n\nendmodule\n\n\nmodule BNE_16b(\n    input  wire [3:0] a,    \n    output  wire  Q,    \n    output  wire [1:0] y    \n    );\n\n\n assign Q = a[0] & a[1] & a[2] & a[3];\n assign y[1] = a[0] & a[1];\n assign y[0] = a[0] & (!a[1] | a[2] );\nendmodule\n\nmodule NLC_16b (\n    input  wire [3:0] x,    // Dedicated inputs \n    output  wire  a,    // Dedicated inputs \n    output  wire [1:0] z    // Dedicated inputs \n    );\n\nwire aprimo,z1,z0,aux1;\nassign aprimo = x[3] | x[2] | x[1] | x[0];\nassign a = ! aprimo;\nassign z1 = x[3] | x[2];\nassign z[1] = ! z1; \nassign z0 = aux1 | x[3];\nassign aux1 = x[1] & ! (x[2]);\nassign z[0] = ! z0;\n\nendmodule \n\nmodule Mux_LZC_16b(\n    input wire [1:0] i0 ,\n    input wire [1:0] i1  ,\n    input wire [1:0] i2  ,\n    input wire [1:0] i3  ,\n    input wire [1:0]  s  ,\n    output reg [1:0] o  \n    );\n\nalways @(*)\n  case (s)\n     2'b00: o = i0;\n     2'b01: o = i1;\n     2'b10: o = i2;\n     2'b11: o = i3;\n\n  endcase\n      \nendmodule\n\n\n/*\nBased on paper: \nR. Murillo, A. A. Del Barrio and G. Botella, \"Customized Posit Adders and Multipliers using the FloPoCo Core Generator,\" 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, \ndoi: 10.1109/ISCAS45731.2020.9180771.\n*/\n\nmodule normalizer_16 #(parameter N=16) (\n\tinput wire [N:0] i_in,\n\tinput wire i_ozb,\n\toutput wire [$clog2(N):0]o_count,\n\toutput wire [N:0] o_r\n);\n\n\twire [N:0] level5 ;\n\twire [N:0] level4 ;\n\twire count4;\n\twire sozb ;\n\twire count3 ;\n\twire [N:0] level3 ;\n\twire count2 ;\n\twire [N:0]level2 ;\n\twire count1;\n\twire [N:0]level1 ;\n\twire count0;\n\twire [N:0]level0;\n\twire [$clog2(N):0]sCount ;\n\n\tassign level5 = i_in;\n\tassign sozb = i_ozb;\n\n\tassign count4 = (level5[N:1] == {16{sozb}}) ? 1: 0;\n\tassign level4 =(!count4) ? level5 : {level5[0],{16{1'b0}}};\n\n\tassign count3 = (level4[N:N-7] == {8{sozb}}) ? 1: 0;\n\tassign level3 = (!count3) ? level4 : {level4[8:0],{8{1'b0}}};\n\n\tassign count2 = (level3[N : N-3] == {4{sozb}})? 1 : 0;\n\n\tassign level2 = (!count2) ? level3  : {level3[12:0],{4{1'b0}}};\n\tassign count1 = level2[N:N-1]=={sozb,sozb} ?  1 : 0;\n\n\tassign level1 = (!count1) ? level2 : {level2[14:0], 2'b00};\n\n\tassign count0 = (level1[N]==sozb) ? 1 : 0;\n\tassign level0 = (!count0) ? level1 : {level1[15:0],1'b0};\n\n\tassign o_r    = level0;\n\tassign sCount = {count4,count3,count2,count1,count0};\n\tassign o_count  = sCount;\n\nendmodule \n\n\nmodule posit_top_open_hw #(parameter  N=16) (\n  input wire [N-1:0] i_in_1,\n  input wire [N-1:0] i_in_2,\n  output wire [5:0] o_sign_regime_exp_1,\n  output wire [5:0] o_sign_regime_exp_2,\n  output wire [N-5:0] o_mantissa_1,\n  output wire [N-5:0] o_mantissa_2,\n  output wire [N-1:0] o_res\n);\n  \n  wire [$clog2(N)+1:0]w_sf_1;\n  wire [N-5:0] w_mant_1;\n\n  wire [$clog2(N)+1:0]w_sf_2;\n  wire [N-5:0] w_mant_2;\n\n  wire [N-10:0]w_sf_res_add;\n  wire [N-5:0]w_mant_res_add;\n  wire w_guard_res_add;\n  wire w_sticky_res_add;\n  wire w_nzn_res_add;\n  wire w_Q_1;\n  wire w_sign_1;\n  wire w_exponent_1;\n  wire [3:0]w_regime_value_1;\n  wire w_Q_2;\n  wire w_s_res_add;\n  wire w_sign_2;\n  wire w_exponent_2;\n  wire [3:0]w_regime_value_2;\n\nFixed16toPosit16 instFixed16toPosit16_1(\n  .fixed_number_input(i_in_1),\n  .Q                 (w_Q_1),\n  .sign              (w_sign_1),\n  .exponent          (w_exponent_1),\n  .mantissa          (w_mant_1),\n  .regime_value      (w_regime_value_1)\n  );\n\nFixed16toPosit16 instFixed16toPosit16_2(\n  .fixed_number_input(i_in_2),\n  .Q                 (w_Q_2),\n  .sign              (w_sign_2),\n  .exponent          (w_exponent_2),\n  .mantissa          (w_mant_2),\n  .regime_value      (w_regime_value_2)\n  );\n\nassign w_sf_1 =(!w_sign_1) ? {1'b1, w_regime_value_1,w_exponent_1}: {1'b1, w_regime_value_1,~w_exponent_1} ;\nassign w_sf_2 =(!w_sign_2) ? {1'b1, w_regime_value_2,w_exponent_2}:  {1'b1, w_regime_value_2,~w_exponent_2};\nassign o_sign_regime_exp_1 = (!w_sign_1) ?  {w_sign_1,w_regime_value_1,w_exponent_1} : {w_sign_1,w_regime_value_1,~w_exponent_1};\nassign o_sign_regime_exp_2 = (!w_sign_2) ?  {w_sign_2,w_regime_value_2,w_exponent_2} : {w_sign_2,w_regime_value_2,~w_exponent_2};\nassign o_mantissa_1 = w_mant_1;\nassign o_mantissa_2 = w_mant_2;\n\n  add #(.N(N)) inst_add(\n    .i_s_1   (w_sign_1),\n    .i_sf_1  (w_sf_1),\n    .i_mant_1(w_mant_1),\n    .i_nzn_1 (~w_Q_1),\n    .i_sf_2  (w_sf_2),\n    .i_mant_2(w_mant_2),\n    .i_nzn_2 (~w_Q_2),\n    .i_s_2   (w_sign_2),\n    .o_nzn   (w_nzn_res_add),\n    .o_s     (w_s_res_add),\n    .o_sticky(w_sticky_res_add),\n    .o_guard (w_guard_res_add),\n    .o_sf    (w_sf_res_add),\n    .o_mant  (w_mant_res_add)\n  );\n\n  data_posit_encoder #(.N(N)) inst_data_posit_encoder\n    (  .i_mant  (w_mant_res_add),\n      .i_guard (w_guard_res_add),\n\n      .i_nzn   (w_nzn_res_add),\n      .i_sf(w_sf_res_add),\n      .i_s     (w_s_res_add),\n      .i_sticky(w_sticky_res_add),\n      .o_r     (o_res)\n    );\n\nendmodule\n\n\n/*\nBased on paper: \nR. Murillo, A. A. Del Barrio and G. Botella, \"Customized Posit Adders and Multipliers using the FloPoCo Core Generator,\" 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, \ndoi: 10.1109/ISCAS45731.2020.9180771.\n*/\n\nmodule right_shifter_sticky_16 #(parameter N=16) (\n  input wire [N-1:0] i_in,\n  input wire [$clog2(N):0] i_s,\n  input wire i_padbit,\n  output wire [N-1:0] o_r,\n  output wire o_sticky\n);\n\n\n  wire [$clog2(N):0] ps;\n  wire [N-1:0] Xpadded;\n  wire [N-1:0] level5;\n  wire stk4 ;\n  wire [N-1:0] level4 ;\n  wire stk3 ;\n  wire [N-1:0] level3 ;\n  wire stk2 ;\n  wire [N-1:0] level2 ;\n  wire stk1 ;\n  wire [N-1:0] level1 ;\n  wire stk0 ;\n  wire [N-1:0] level0 ;\n\n  assign ps      = i_s;\n  assign Xpadded = i_in;\n  assign level5  = Xpadded;\n  assign stk4    = (level5!=0 && ps[4]==1) ?  1 : 0;\n  assign level4  = (ps[4]==0) ?  level5 : {16{i_padbit}} ;\n  assign stk3    = ((level4[7:0]!=0 && ps[3]==1)|| stk4==1) ? 1 : 0;\n  assign level3 =  ps[3]==0 ?  level4 : {{8{i_padbit}},level4[15 : 8]};\n  assign stk2 = ((level3[3:0]!=0 && ps[2]==1)|| stk3==1) ? 1 : 0;\n  assign level2 =  ps[2]==0 ?  level3 : {{4{i_padbit}},level3[15 : 4]};\n  assign stk1 = ((level2[1:0]!=0 && ps[1]==1)|| stk2==1) ? 1 : 0;\n  assign level1 =  ps[1]==0 ?  level2 : {{2{i_padbit}},level2[15 : 2]};\n  assign stk0 = ((level1[0]!=0 && ps[0]==1)|| stk1==1) ? 1 : 0;\n  assign level0 =   ps[0]==0 ?  level1 : {i_padbit,level1[15 : 1]};\n  assign o_r = level0;\n  assign o_sticky = stk0;\n\n\n\n\nendmodule\n\n\n/*\nBased on paper: \nR. Murillo, A. A. Del Barrio and G. Botella, \"Customized Posit Adders and Multipliers using the FloPoCo Core Generator,\" 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, \ndoi: 10.1109/ISCAS45731.2020.9180771.\n*/\n\nmodule right_shifter_sticky_18 #(parameter N=16) (\n  input wire [N-2:0] i_in,\n  input wire [$clog2(N)-1:0] i_s,\n  input wire i_padbit,\n  output wire [N-2:0] o_r,\n  output wire o_sticky\n);\n\n\n  wire [$clog2(N)-1:0] ps;\n  wire [N-2:0] Xpadded;\n  wire [N-2:0] level4 ;\n  wire stk3 ;\n  wire [N-2:0] level3 ;\n  wire stk2 ;\n  wire [N-2:0] level2 ;\n  wire stk1 ;\n  wire [N-2:0] level1 ;\n  wire stk0 ;\n  wire [N-2:0] level0 ;\n\n  assign ps      = i_s;\n  assign Xpadded = i_in;\n  assign level4  = Xpadded ;\n  assign stk3    = ((level4[7:0]!=0 && ps[3]==1)) ? 1 : 0;\n  assign level3 =  ps[3]==0 ?  level4 : {{8{i_padbit}},level4[14 : 8]};\n  assign stk2 = ((level3[3:0]!=0 && ps[2]==1)|| stk3==1) ? 1 : 0;\n  assign level2 =  ps[2]==0 ?  level3 : {{4{i_padbit}},level3[14 : 4]};\n  assign stk1 = ((level2[1:0]!=0 && ps[1]==1)|| stk2==1) ? 1 : 0;\n  assign level1 =  ps[1]==0 ?  level2 : {{2{i_padbit}},level2[14 : 2]};\n  assign stk0 = ((level1[0]!=0 && ps[0]==1)|| stk1==1) ? 1 : 0;\n  assign level0 =   ps[0]==0 ?  level1 : {i_padbit,level1[14 : 1]};\n  assign o_r = level0;\n  assign o_sticky = stk0;\n\n\n\n\nendmodule\n\n\n/*\n* Copyright (c) 2024 Your Name\n* SPDX-License-Identifier: Apache-2.0\n*/\n//////////////////////////////////////////////////////////////////////////////////\n// Companies: (a) University of Salerno, Fisciano (SA), Italy; \n//            (b) STMicroelectronics, Napoli, Italy.\n// Engineer: Andrea Fasolino (a), Gian Domenico Licciardo (a), Aldo Torino (b), Francesco Del Prete (b), Claudio Parrella (b).\n// \n// Module Name: tt_um_afasolino\n// \n// \n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n`default_nettype none\n\nmodule tt_um_afasolino (\n  input  wire [7:0] ui_in,    // Dedicated inputs\n  output wire [7:0] uo_out,   // Dedicated outputs\n  input  wire [7:0] uio_in,   // IOs: Input path\n  output wire [7:0] uio_out,  // IOs: Output path\n  output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n  input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n  input  wire       clk,      // clock\n  input  wire       rst_n     // reset_n - low to reset\n);\n\n// All output pins must be assigned. If not used, assign to 0.\n//  assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in\n//  assign uio_out = 0;\n//  assign uio_oe  = 0;\n  localparam  data_buffer_size_bit=8;\n  localparam  data_posit_size_bit=16;\n  localparam  buffer_size = 4;\n  localparam  buffer_size_read = 12;\n  reg alu_ready;\n  reg [clog2(buffer_size+1)-1:0] wr_data_pointer;\n  reg [clog2(buffer_size_read+1)-1:0] rd_data_pointer;\n  wire data_input_valid;\n  wire [data_posit_size_bit-1:0]data_input_1;\n  wire [data_posit_size_bit-1:0]data_input_2;\n  wire [data_posit_size_bit-1:0]o_result;\n  reg [data_buffer_size_bit-1:0] input_buffer_data_1;\n  reg [data_buffer_size_bit-1:0] input_buffer_data_2;\n  reg [data_buffer_size_bit-1:0] input_buffer_data_3;\n  reg [data_buffer_size_bit-1:0] input_buffer_data_4;\n  reg data_valid_sync1;\n  reg data_valid_sync2;\n  reg read_data_valid_sync1;\n  reg read_data_valid_sync2;\n  reg read_data;\n  wire read_data_valid;\n  wire [5:0]w_sign_regime_exp_1;\n  wire [5:0]w_sign_regime_exp_2;\n  wire [11:0]w_mantissa_1;\n  wire [11:0]w_mantissa_2;\n\n  reg read_data_ready;\n  reg [7:0]out_reg;\n  assign data_input_valid = uio_in[0]; //Data valid on IO in 0\n  assign uio_oe[0]        = 0;\n  assign uio_oe[1]        = 1;\n  assign data_input_1     = {input_buffer_data_2,input_buffer_data_1};\n  assign data_input_2     = {input_buffer_data_4,input_buffer_data_3};\n  assign uio_out[1]       = alu_ready;//alu ready on Output 1\n\n  assign read_data_valid = uio_in[2];// Read Data valid on IO in 0\n  assign uio_oe[2]       = 0;\n  assign uio_out[3]      = read_data_ready;\n  assign uio_oe[3]       = 1;\n  assign uo_out     = out_reg;\n  assign uio_oe[7:4] = 0; \n  assign uio_out[7:4]=0;\n  assign uio_out[0]=0;\n  assign uio_out[2]=0;\n  always@(posedge clk, negedge rst_n)begin\n    if(rst_n==0)begin\n      data_valid_sync1<=0;\n      data_valid_sync2<=0;\n      read_data_valid_sync1<=0;\n      read_data_valid_sync2<=0;\n    end\n    else begin\n      data_valid_sync1<=data_input_valid;\n      data_valid_sync2<=data_valid_sync1;\n      read_data_valid_sync1<=read_data_valid;\n      read_data_valid_sync2<=read_data_valid_sync1;\n    end\n  end\n\n  always@(posedge clk, negedge rst_n)begin\n    if(rst_n==0)begin\n      input_buffer_data_1<=0;\n      input_buffer_data_2<=0;\n      input_buffer_data_3<=0;\n      input_buffer_data_4<=0;\n      wr_data_pointer<=0;\n      rd_data_pointer<=0;\n      alu_ready<=1;\n      read_data<=0;\n      out_reg<=0;\n      read_data_ready<=0;\n    end\n    else begin\n      if(data_valid_sync2==1 && alu_ready==1) begin\n        case(wr_data_pointer)\n          'd0: begin\n            input_buffer_data_1<=ui_in;\n            wr_data_pointer<=wr_data_pointer+1;\n            alu_ready<=0;\n          end\n          'd1: begin\n            input_buffer_data_2<=ui_in;\n            wr_data_pointer<=wr_data_pointer+1;\n            alu_ready<=0;\n          end\n          'd2: begin\n            input_buffer_data_3<=ui_in;\n            wr_data_pointer<=wr_data_pointer+1;\n            alu_ready<=0;\n          end\n          'd3: begin\n            input_buffer_data_4<=ui_in;\n            alu_ready<=0;\n            read_data<=1;\n            read_data_ready<=1;\n            rd_data_pointer<=0;\n          end\n\n          default:begin\n            input_buffer_data_1<=0;\n            input_buffer_data_2<=0;\n            input_buffer_data_3<=0;\n            input_buffer_data_4<=0;\n            wr_data_pointer<=0;\n            alu_ready<=1;\n            read_data_ready<=0;\n          end\n        endcase\n      end\n      if(read_data==0)begin\n        if(data_valid_sync2==0)begin\n          alu_ready<=1;\n        end\n      end\n      else begin\n        if(read_data_ready)begin\n          case(rd_data_pointer)\n            'd0: begin\n              out_reg<=data_input_1[7:0];\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd1: begin\n              out_reg<=data_input_1[15:8];\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd2: begin\n              out_reg<=data_input_2[7:0];\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd3: begin\n              out_reg<=data_input_2[15:8];\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd4: begin\n              out_reg<={2'b00,w_sign_regime_exp_1};\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd5: begin\n              out_reg<={2'b00,w_sign_regime_exp_2};\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end \n            'd6: begin\n              out_reg<=w_mantissa_1[7:0];\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd7: begin\n              out_reg<={4'd0,w_mantissa_1[11:8]};\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end \n            'd8: begin\n              out_reg<=w_mantissa_2[7:0];\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd9: begin\n              out_reg<={4'd0,w_mantissa_2[11:8]};\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end                                      \n\n            'd10: begin\n              out_reg<=o_result[7:0];\n              if(read_data_valid_sync2==1) begin\n                rd_data_pointer<=rd_data_pointer+1;\n                read_data_ready<=0;\n              end\n            end\n            'd11: begin\n             out_reg<=o_result[15:8];\n              if(read_data_valid_sync2==1) begin\n                read_data_ready<=0;\n                read_data<=0;\n                alu_ready<=1;\n                wr_data_pointer<=0;\n              end\n            end\n            default:begin\n              out_reg<=0;\n              alu_ready<=1;\n              rd_data_pointer<=0;\n              read_data_ready<=0;\n            end\n          endcase\n        end\n        else if(read_data_valid_sync2==0)begin\n          read_data_ready<=1;\n        end\n      end\n    end\n  end\n\n  posit_top_open_hw inst_posit_top(\n    .i_in_1(data_input_1),\n    .i_in_2(data_input_2),\n    .o_res(o_result),\n    .o_sign_regime_exp_1(w_sign_regime_exp_1),\n    .o_sign_regime_exp_2(w_sign_regime_exp_2),\n    .o_mantissa_1       (w_mantissa_1),\n    .o_mantissa_2       (w_mantissa_2)\n  );\n\n  function integer clog2;\n    input integer value;\n    begin\n      value = value-1;\n      for (clog2=0; value>0; clog2=clog2+1)\n        value = value>>1;\n    end\n  endfunction\n\nendmodule\n", "mask_idx": {"conditional_statement": [[23352, 23492], [20808, 25566], [23598, 23738], [22260, 25548]], "blocking_assignment": [[10652, 10659], [8994, 9033], [7771, 7819], [7985, 8034], [7571, 7612]], "module_program_interface_instantiation": [[13091, 13340], [4864, 5062], [6991, 7091], [9461, 9549]], "always_construct": [[10597, 10710], [7411, 9064], [20360, 20759], [20763, 25572]], "case_statement": [[7423, 9064], [10611, 10710], [21165, 22113], [22295, 25447]], "ansi_port_declaration": [[16503, 16527], [18306, 18386], [14899, 14923]], "continuous_assign": [[2127, 2187], [9903, 9940], [20060, 20124], [4620, 4651], [11478, 11537]], "parameter_declaration": [[16399, 16416], [14879, 14896], [278, 295], [3910, 3927], [11019, 11036]], "nonblocking_assignment": [[21970, 21993], [25152, 25165], [24794, 24817]]}, "all_mask_idx": {"module_program_interface_instantiation": [[2278, 2493], [2929, 3088], [4864, 5062], [6991, 7091], [9325, 9441], [9461, 9549], [9584, 9780], [12840, 13089], [13091, 13340], [13887, 14288], [14292, 14566], [25576, 25863]], "continuous_assign": [[1407, 1443], [1446, 1485], [1488, 1524], [1527, 1566], [1570, 1642], [1645, 1704], [1707, 1767], [1770, 1892], [1895, 2016], [2020, 2076], [2079, 2124], [2127, 2187], [2191, 2236], [2240, 2275], [2496, 2540], [2543, 2584], [2587, 2628], [2634, 2724], [2727, 2753], [2756, 2782], [2785, 2811], [2815, 2852], [2855, 2925], [3092, 3167], [3171, 3227], [3230, 3265], [3268, 3315], [3318, 3376], [3379, 3418], [3421, 3463], [3466, 3547], [3550, 3572], [3575, 3599], [4497, 4525], [4528, 4553], [4556, 4593], [4596, 4617], [4620, 4651], [4655, 4687], [4690, 4734], [4738, 4769], [4772, 4804], [4807, 4861], [5068, 5122], [5126, 5155], [5158, 5187], [5190, 5221], [5224, 5263], [5266, 5319], [5325, 5375], [5378, 5414], [5780, 5837], [5838, 5902], [5903, 5990], [5991, 6029], [7097, 7146], [7147, 7175], [7176, 7211], [7212, 7263], [7264, 7337], [7338, 7410], [9551, 9582], [9903, 9940], [9942, 9968], [9970, 10007], [10211, 10253], [10254, 10274], [10275, 10299], [10300, 10320], [10321, 10345], [10346, 10376], [10377, 10396], [11379, 11400], [11402, 11422], [11425, 11476], [11478, 11537], [11540, 11592], [11594, 11655], [11658, 11712], [11715, 11778], [11780, 11832], [11835, 11894], [11897, 11939], [11941, 11998], [12001, 12024], [12026, 12079], [12081, 12106], [13342, 13450], [13451, 13559], [13560, 13689], [13690, 13819], [13820, 13851], [13852, 13883], [15299, 15320], [15323, 15345], [15348, 15373], [15376, 15426], [15429, 15485], [15488, 15554], [15557, 15626], [15629, 15692], [15695, 15764], [15767, 15830], [15833, 15902], [15905, 15966], [15969, 16034], [16037, 16057], [16060, 16083], [16786, 16807], [16810, 16832], [16835, 16861], [16864, 16920], [16923, 16992], [16995, 17058], [17061, 17130], [17133, 17196], [17199, 17268], [17271, 17332], [17335, 17400], [17403, 17423], [17426, 17449], [19730, 19790], [19793, 19821], [19824, 19852], [19855, 19923], [19926, 19994], [19997, 20056], [20060, 20124], [20127, 20154], [20157, 20198], [20201, 20228], [20231, 20259], [20262, 20286], [20289, 20311], [20314, 20334], [20337, 20357]], "blocking_assignment": [[7471, 7512], [7571, 7612], [7671, 7712], [7771, 7819], [7878, 7926], [7985, 8034], [8093, 8143], [8202, 8253], [8312, 8364], [8423, 8476], [8535, 8589], [8648, 8703], [8762, 8819], [8878, 8934], [8994, 9033], [10632, 10639], [10652, 10659], [10672, 10679], [10692, 10699], [25932, 25948], [26001, 26018]], "nonblocking_assignment": [[20429, 20449], [20456, 20476], [20483, 20508], [20515, 20540], [20570, 20605], [20612, 20647], [20654, 20693], [20700, 20745], [20832, 20855], [20862, 20885], [20892, 20915], [20922, 20945], [20952, 20971], [20978, 20997], [21004, 21017], [21024, 21037], [21044, 21055], [21062, 21081], [21220, 21247], [21260, 21295], [21308, 21321], [21369, 21396], [21409, 21444], [21457, 21470], [21518, 21545], [21558, 21593], [21606, 21619], [21667, 21694], [21707, 21720], [21733, 21746], [21759, 21778], [21791, 21810], [21862, 21885], [21898, 21921], [21934, 21957], [21970, 21993], [22006, 22025], [22038, 22051], [22064, 22083], [22199, 22212], [22354, 22381], [22447, 22482], [22499, 22518], [22590, 22618], [22684, 22719], [22736, 22755], [22827, 22854], [22920, 22955], [22972, 22991], [23063, 23091], [23157, 23192], [23209, 23228], [23300, 23337], [23403, 23438], [23455, 23474], [23546, 23583], [23649, 23684], [23701, 23720], [23793, 23820], [23886, 23921], [23938, 23957], [24029, 24064], [24130, 24165], [24182, 24201], [24274, 24301], [24367, 24402], [24419, 24438], [24510, 24545], [24611, 24646], [24663, 24682], [24794, 24817], [24883, 24918], [24935, 24954], [25026, 25050], [25116, 25135], [25152, 25165], [25182, 25195], [25212, 25231], [25306, 25317], [25332, 25345], [25360, 25379], [25394, 25413], [25517, 25536]], "case_statement": [[7423, 9064], [10611, 10710], [21165, 22113], [22295, 25447]], "conditional_statement": [[20405, 20753], [20808, 25566], [21111, 22123], [22130, 25558], [22160, 22224], [22260, 25548], [22396, 22536], [22633, 22773], [22869, 23009], [23106, 23246], [23352, 23492], [23598, 23738], [23835, 23975], [24079, 24219], [24316, 24456], [24560, 24700], [24832, 24972], [25065, 25249], [25473, 25548]], "always_construct": [[7411, 9064], [10597, 10710], [20360, 20759], [20763, 25572]], "parameter_declaration": [[278, 295], [3910, 3927], [11019, 11036], [12148, 12166], [14879, 14896], [16399, 16416]], "ansi_port_declaration": [[299, 317], [321, 349], [353, 381], [385, 405], [409, 427], [431, 459], [463, 491], [495, 515], [519, 535], [539, 564], [568, 595], [599, 619], [623, 644], [648, 665], [3930, 3946], [3949, 3974], [3977, 4003], [4006, 4026], [4029, 4050], [4053, 4071], [4074, 4097], [5460, 5495], [5500, 5529], [5534, 5559], [5564, 5594], [5599, 5617], [5622, 5642], [9118, 9139], [9144, 9168], [9173, 9186], [9814, 9838], [9843, 9863], [9868, 9892], [10040, 10084], [10089, 10129], [10134, 10178], [10434, 10455], [10460, 10482], [10487, 10509], [10514, 10536], [10541, 10563], [10568, 10588], [11038, 11060], [11062, 11079], [11081, 11114], [11116, 11137], [12169, 12195], [12198, 12224], [12227, 12265], [12268, 12306], [12309, 12342], [12345, 12378], [12381, 12406], [14899, 14923], [14926, 14955], [14958, 14978], [14981, 15005], [15008, 15028], [16419, 16443], [16446, 16477], [16480, 16500], [16503, 16527], [16530, 16550], [18106, 18153], [18156, 18204], [18207, 18253], [18256, 18303], [18306, 18386], [18389, 18477], [18480, 18516], [18519, 18572]]}}
{"sample_i": "aj-stein-nist-tt_stopwatch_project", "topmodule": "tt_um_ajstein_stopwatch", "code": "//_\\TLV_version 1d: tl-x.org, generated by SandPiper(TM) 1.14-2022/10/10-beta-Pro\n//_\\source top.tlv 36\n\n//_\\SV\n   // Include Tiny Tapeout Lab.\n   // Included URL: \"https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/35e36bd144fddd75495d4cbc01c4fc50ac5bde6f/tlv_lib/tiny_tapeout_lib.tlv\"// Included URL: \"https://raw.githubusercontent.com/os-fpga/Virtual-FPGA-Lab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlv_lib/fpga_includes.tlv\"\n//_\\source top.tlv 79\n//_\\SV\n\n// ================================================\n// A simple Makerchip Verilog test bench driving random stimulus.\n// Modify the module contents to your needs.\n// ================================================\n\n\n// Provide a wrapper module to debounce input signals if requested.\n\n//_\\SV\n\n\n\n// =======================\n// The Tiny Tapeout module\n// =======================\n\nmodule tt_um_ajstein_stopwatch (\n    input  wire [7:0] ui_in,    // Dedicated inputs - connected to the input switches\n    output wire [7:0] uo_out,   // Dedicated outputs - connected to the 7 segment display\n       // The FPGA is based on TinyTapeout 3 which has no bidirectional I/Os (vs. TT6 for the ASIC).\n    input  wire [7:0] uio_in,   // IOs: Bidirectional Input path\n    output wire [7:0] uio_out,  // IOs: Bidirectional Output path\n    output wire [7:0] uio_oe,   // IOs: Bidirectional Enable path (active high: 0=input, 1=output)\n    \n    input  wire       ena,      // will go high when the design is enabled\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n   wire reset = ! rst_n;\n\n// ---------- Generated Code Inlined Here (before 1st \\TLV) ----------\n// Generated by SandPiper(TM) 1.14-2022/10/10-beta-Pro from Redwood EDA, LLC.\n// (Installed here: /usr/local/mono/sandpiper/distro.)\n// Redwood EDA, LLC does not claim intellectual property rights to this file and provides no warranty regarding its correctness or quality.\n\n\n// For silencing unused signal messages.\n`define BOGUS_USE(ignore)\n\n\ngenvar digit, input_label, leds, switch;\n\n\n//\n// Signals declared top-level.\n//\n\n// For $slideswitch.\nwire [7:0] L0_slideswitch_a0;\n\n// For $sseg_decimal_point_n.\nwire L0_sseg_decimal_point_n_a0;\n\n// For $sseg_digit_n.\nwire [7:0] L0_sseg_digit_n_a0;\n\n// For $sseg_segment_n.\nwire [6:0] L0_sseg_segment_n_a0;\n\n// For /fpga_pins/fpga$cycle_counter.\nwire [31:0] FpgaPins_Fpga_cycle_counter_a0;\nreg  [31:0] FpgaPins_Fpga_cycle_counter_a1;\n\n// For /fpga_pins/fpga$display_counter.\nwire [3:0] FpgaPins_Fpga_display_counter_a0;\nreg  [3:0] FpgaPins_Fpga_display_counter_a1;\n\n// For /fpga_pins/fpga$reset.\nwire FpgaPins_Fpga_reset_a0;\n\n// For /fpga_pins/fpga$segments.\nwire [6:0] FpgaPins_Fpga_segments_a0;\n\n\n\n\n   //\n   // Scope: /fpga_pins\n   //\n\n\n      //\n      // Scope: /fpga\n      //\n\n         // Staging of $cycle_counter.\n         always @(posedge clk) FpgaPins_Fpga_cycle_counter_a1[31:0] <= FpgaPins_Fpga_cycle_counter_a0[31:0];\n\n         // Staging of $display_counter.\n         always @(posedge clk) FpgaPins_Fpga_display_counter_a1[3:0] <= FpgaPins_Fpga_display_counter_a0[3:0];\n\n\n\n\n\n\n\n//\n// Debug Signals\n//\n\ngenerate\n\n   if (1) begin : DEBUG_SIGS_GTKWAVE\n\n      (* keep *) wire [7:0] \\@0$slideswitch ;\n      assign \\@0$slideswitch = L0_slideswitch_a0;\n      (* keep *) wire  \\@0$sseg_decimal_point_n ;\n      assign \\@0$sseg_decimal_point_n = L0_sseg_decimal_point_n_a0;\n      (* keep *) wire [7:0] \\@0$sseg_digit_n ;\n      assign \\@0$sseg_digit_n = L0_sseg_digit_n_a0;\n      (* keep *) wire [6:0] \\@0$sseg_segment_n ;\n      assign \\@0$sseg_segment_n = L0_sseg_segment_n_a0;\n\n      //\n      // Scope: /digit[0:0]\n      //\n      for (digit = 0; digit <= 0; digit=digit+1) begin : \\/digit \n\n         //\n         // Scope: /leds[7:0]\n         //\n         for (leds = 0; leds <= 7; leds=leds+1) begin : \\/leds \n            (* keep *) wire  \\//@0$viz_lit ;\n            assign \\//@0$viz_lit = L1_Digit[digit].L2_Leds[leds].L2_viz_lit_a0;\n         end\n      end\n\n      //\n      // Scope: /fpga_pins\n      //\n      if (1) begin : \\/fpga_pins \n\n         //\n         // Scope: /fpga\n         //\n         if (1) begin : \\/fpga \n            (* keep *) wire [31:0] \\//@0$cycle_counter ;\n            assign \\//@0$cycle_counter = FpgaPins_Fpga_cycle_counter_a0;\n            (* keep *) wire [3:0] \\//@0$display_counter ;\n            assign \\//@0$display_counter = FpgaPins_Fpga_display_counter_a0;\n            (* keep *) wire  \\//@0$reset ;\n            assign \\//@0$reset = FpgaPins_Fpga_reset_a0;\n            (* keep *) wire [6:0] \\//@0$segments ;\n            assign \\//@0$segments = FpgaPins_Fpga_segments_a0;\n         end\n      end\n\n      //\n      // Scope: /switch[7:0]\n      //\n      for (switch = 0; switch <= 7; switch=switch+1) begin : \\/switch \n         (* keep *) wire  \\/@0$viz_switch ;\n         assign \\/@0$viz_switch = L1_Switch[switch].L1_viz_switch_a0;\n      end\n\n\n   end\n\nendgenerate\n\n// ---------- Generated Code Ends ----------\n//_\\TLV\n   /* verilator lint_off UNOPTFLAT */\n   //_\\source top.tlv 72   // Instantiated from top.tlv, 146 as: m5+tt_lab.\n      // Connect Tiny Tapeout I/Os to Virtual FPGA Lab.\n      //_\\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/35e36bd144fddd75495d4cbc01c4fc50ac5bde6f/tlvlib/tinytapeoutlib.tlv 76   // Instantiated from top.tlv, 74 as: m5+tt_connections()\n         assign L0_slideswitch_a0[7:0] = ui_in;\n         assign L0_sseg_segment_n_a0[6:0] = ~ uo_out[6:0];\n         assign L0_sseg_decimal_point_n_a0 = ~ uo_out[7];\n         assign L0_sseg_digit_n_a0[7:0] = 8'b11111110;\n      //_\\end_source\n      // Instantiate the Virtual FPGA Lab.\n      //_\\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 307   // Instantiated from top.tlv, 76 as: m5+board(/top, /fpga, 7, $, , stopwatch)\n         \n         //_\\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 355   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 309 as: m4+thanks(m5__l(309)m5_eval(m5_get(BOARD_THANKS_ARGS)))\n            //_/thanks\n               \n         //_\\end_source\n         \n      \n         // Board VIZ.\n      \n         // Board Image.\n         \n         //_/fpga_pins\n            \n            //_/fpga\n               //_\\source top.tlv 43   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 340 as: m4+stopwatch.\n               \n                  assign FpgaPins_Fpga_reset_a0 = reset;\n                  assign FpgaPins_Fpga_cycle_counter_a0[31:0] = FpgaPins_Fpga_reset_a0 ? 1 :\n                      FpgaPins_Fpga_cycle_counter_a1 == 20000000 ? 1 :\n                      FpgaPins_Fpga_cycle_counter_a1 + 1;\n                  assign FpgaPins_Fpga_display_counter_a0[3:0] =\n                     FpgaPins_Fpga_reset_a0 ? 4'd0 :\n                     FpgaPins_Fpga_cycle_counter_a0 == 20000000\n                         ? FpgaPins_Fpga_display_counter_a1 == 9 ? 0 :\n                           FpgaPins_Fpga_display_counter_a1 + 1 :\n                     //default\n                           FpgaPins_Fpga_display_counter_a1;\n                  assign FpgaPins_Fpga_segments_a0[6:0] =\n                     (FpgaPins_Fpga_display_counter_a0 == 0) ? 7'b1000000 :\n                     (FpgaPins_Fpga_display_counter_a0 == 1) ? 7'b1111001 :\n                     (FpgaPins_Fpga_display_counter_a0 == 2) ? 7'b0100100 :\n                     (FpgaPins_Fpga_display_counter_a0 == 3) ? 7'b0110000 :\n                     (FpgaPins_Fpga_display_counter_a0 == 4) ? 7'b0011001 :\n                     (FpgaPins_Fpga_display_counter_a0 == 5) ? 7'b0010010 :\n                     (FpgaPins_Fpga_display_counter_a0 == 6) ? 7'b0000010 :\n                     (FpgaPins_Fpga_display_counter_a0 == 7) ? 7'b1111000 :\n                     (FpgaPins_Fpga_display_counter_a0 == 8) ? 7'b0000000 :\n                     7'b0010000 ; // '9'\n                  assign uo_out = {1'b0, ~FpgaPins_Fpga_segments_a0};\n                  assign uio_out = 8'b0;\n                  assign uio_oe = 8'b0;\n               //_\\end_source\n      \n         // LEDs.\n         \n      \n         // 7-Segment\n         //_\\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 395   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 346 as: m4+fpga_sseg.\n            generate for (digit = 0; digit <= 0; digit=digit+1) begin : L1_Digit //_/digit\n               \n               for (leds = 0; leds <= 7; leds=leds+1) begin : L2_Leds //_/leds\n\n                  // For $viz_lit.\n                  wire L2_viz_lit_a0;\n\n                  assign L2_viz_lit_a0 = (! L0_sseg_digit_n_a0[digit]) && ! ((leds == 7) ? L0_sseg_decimal_point_n_a0 : L0_sseg_segment_n_a0[leds % 7]);\n                  \n               end\n            end endgenerate\n         //_\\end_source\n      \n         // slideswitches\n         //_\\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv 454   // Instantiated from /raw.githubusercontent.com/osfpga/VirtualFPGALab/a069f1e4e19adc829b53237b3e0b5d6763dc3194/tlvlib/fpgaincludes.tlv, 349 as: m4+fpga_switch.\n            generate for (switch = 0; switch <= 7; switch=switch+1) begin : L1_Switch //_/switch\n\n               // For $viz_switch.\n               wire L1_viz_switch_a0;\n\n               assign L1_viz_switch_a0 = L0_slideswitch_a0[switch];\n               \n            end endgenerate\n         //_\\end_source\n      \n         // pushbuttons\n         \n      //_\\end_source\n      // Label the switch inputs [0..7] (1..8 on the physical switch panel) (top-to-bottom).\n      //_\\source /raw.githubusercontent.com/osfpga/VirtualFPGALab/35e36bd144fddd75495d4cbc01c4fc50ac5bde6f/tlvlib/tinytapeoutlib.tlv 82   // Instantiated from top.tlv, 78 as: m5+tt_input_labels_viz(⌈\"UNUSED\", \"UNUSED\", \"UNUSED\", \"UNUSED\", \"UNUSED\", \"UNUSED\", \"UNUSED\", \"UNUSED\"⌉)\n         generate for (input_label = 0; input_label <= 7; input_label=input_label+1) begin : L1_InputLabel //_/input_label\n            \n         end endgenerate\n      //_\\end_source\n   \n   //_\\end_source\n\n/*SV_plus*/\n\n   // ==========================================\n   // If you are using Verilog for your design,\n   // your Verilog logic goes here.\n   // Note, output assignments are in my_design.\n   // ==========================================\n\n//_\\SV\nendmodule\n\n\n// Undefine macros defined by SandPiper.\n`undef BOGUS_USE\n", "mask_idx": {"always_construct": [[2990, 3091], [2839, 2938]], "ansi_port_declaration": [[1396, 1466], [1512, 1565], [970, 1055]], "continuous_assign": [[8142, 8164], [4559, 4609], [6656, 6859]], "nonblocking_assignment": [[2861, 2938], [3012, 3091]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[3223, 3266], [3323, 3384], [3438, 3483], [3539, 3588], [3878, 3945], [4200, 4260], [4331, 4395], [4451, 4495], [4559, 4609], [4805, 4865], [5326, 5364], [5374, 5423], [5433, 5481], [5491, 5536], [6599, 6637], [6656, 6859], [6878, 7270], [7289, 8053], [8072, 8123], [8142, 8164], [8183, 8204], [8876, 9010], [9621, 9673]], "blocking_assignment": [], "nonblocking_assignment": [[2861, 2938], [3012, 3091]], "case_statement": [], "conditional_statement": [], "always_construct": [[2839, 2938], [2990, 3091]], "parameter_declaration": [], "ansi_port_declaration": [[884, 965], [970, 1055], [1161, 1221], [1226, 1287], [1292, 1386], [1396, 1466], [1471, 1507], [1512, 1565]]}}
{"sample_i": "asinghani-tinywspr-tt07", "topmodule": "tt_um_asinghani_tinywspr", "code": "/*\n * Copyright (c) 2024 Anish Singhani\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_asinghani_tinywspr (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n    assign uio_out = 0;\n    assign uio_oe  = 0;\n\n    reg config_start0, config_start1, config_start2;\n    always @(posedge clk) begin\n        config_start0 <= ui_in[1];\n        config_start1 <= config_start0;\n        config_start2 <= config_start1;\n    end\n\n    reg rf_start0, rf_start1, rf_start2;\n    always @(posedge clk) begin\n        rf_start0 <= ui_in[2];\n        rf_start1 <= rf_start0;\n        rf_start2 <= rf_start1;\n    end\n\n    reg config_valid0, config_valid1, config_valid2, config_validlast;\n    always @(posedge clk) begin\n        config_valid0 <= ui_in[0];\n        config_valid1 <= config_valid0;\n        config_valid2 <= config_valid1;\n        config_validlast <= config_valid2;\n    end\n\n    TopLevel tl (\n        .clock(clk),\n        .reset(!rst_n),\n        .io_config_bits_in(uio_in),\n        .io_config_valid_in(config_valid2 && ~config_validlast),\n        .io_config_start(config_start2),\n        .io_rf_start(rf_start2),\n        .io_rf_out(uo_out[0]),\n        .io_bit_out(uo_out[7:6])\n    );\n\n    assign uo_out[1] = uo_out[0];\n    assign uo_out[5:2] = 0;\n\nendmodule\n\n\nmodule StringEncoder (\n\tclock,\n\treset,\n\tio_config_in_valid,\n\tio_config_in_bits,\n\tio_start,\n\tio_done,\n\tio_bit_out_valid,\n\tio_bit_out_bits\n);\n\tinput clock;\n\tinput reset;\n\tinput io_config_in_valid;\n\tinput [7:0] io_config_in_bits;\n\tinput io_start;\n\toutput wire io_done;\n\toutput wire io_bit_out_valid;\n\toutput wire io_bit_out_bits;\n\treg [3:0] state;\n\treg [4:0] pc;\n\treg [3:0] instr_op;\n\treg [7:0] instr_value;\n\treg [27:0] accum;\n\treg [27:0] mul_reg;\n\treg [27:0] reg_n;\n\treg [5:0] power_dbm;\n\treg [31:0] conv_reg;\n\twire _GEN = state == 4'h0;\n\twire _GEN_0 = state == 4'h1;\n\twire _GEN_1 = state == 4'h2;\n\twire _GEN_2 = instr_op == 4'h0;\n\twire _GEN_3 = instr_op == 4'h1;\n\twire _GEN_4 = instr_op == 4'h2;\n\twire _GEN_5 = instr_op == 4'h3;\n\twire _GEN_6 = instr_op == 4'h4;\n\twire _GEN_7 = instr_op == 4'h5;\n\twire _GEN_8 = instr_op == 4'h6;\n\twire _GEN_9 = _GEN_5 | _GEN_6;\n\twire _GEN_10 = _GEN | _GEN_0;\n\treg io_bit_out_REG_valid;\n\treg io_bit_out_REG_bits;\n\treg bit_out_tmp_valid_REG;\n\treg bit_out_tmp_valid_REG_1;\n\treg bit_out_tmp_valid_REG_2;\n\treg REG;\n\treg REG_1;\n\talways @(posedge clock) begin : sv2v_autoblock_1\n\t\treg [255:0] _GEN_11;\n\t\treg _GEN_12;\n\t\treg _GEN_13;\n\t\treg _GEN_14;\n\t\treg _GEN_15;\n\t\treg _GEN_16;\n\t\treg _GEN_17;\n\t\treg _GEN_18;\n\t\treg _GEN_19;\n\t\treg _GEN_20;\n\t\treg _GEN_21;\n\t\treg bit_tmp_valid;\n\t\treg [127:0] _GEN_22;\n\t\t_GEN_11 = 256'h00000000000000030a0112b3020a0000000a051b0a041b0a031b020a01240000;\n\t\t_GEN_12 = _GEN_2 | _GEN_3;\n\t\t_GEN_13 = instr_op == 4'h7;\n\t\t_GEN_14 = state == 4'h3;\n\t\t_GEN_15 = state == 4'h4;\n\t\t_GEN_16 = state == 4'h5;\n\t\t_GEN_17 = _GEN_14 | _GEN_15;\n\t\t_GEN_18 = state == 4'h6;\n\t\t_GEN_19 = state == 4'h7;\n\t\t_GEN_20 = state == 4'h8;\n\t\t_GEN_21 = ((_GEN | _GEN_0) | _GEN_1) | _GEN_17;\n\t\tbit_tmp_valid = ~_GEN_21 & (_GEN_16 | _GEN_18 ? ~instr_value[0] : (_GEN_19 ? ~(|instr_value) : (_GEN_20 ? ~instr_value[0] : (state == 4'h9) & (~(|instr_value) | ~instr_value[0]))));\n\t\tif (reset)\n\t\t\tstate <= 4'h0;\n\t\telse begin : sv2v_autoblock_2\n\t\t\treg [63:0] _GEN_23;\n\t\t\t_GEN_23 = {state, state, state, state, 4'h0, (|instr_value ? state : 4'hb), (|instr_value ? state : 4'ha), (|instr_value ? state : 4'h9), (|instr_value ? state : 4'h8), (|instr_value ? state : 4'h7), (|instr_value ? state : 4'h6), 5'h0a, (io_config_in_valid ? 3'h4 : 3'h3), (_GEN_2 ? 4'h1 : (_GEN_3 ? {2'h0, (io_config_in_valid ? 2'h1 : 2'h2)} : (_GEN_4 ? {2'h0, (|instr_value ? 2'h2 : 2'h1)} : (_GEN_9 ? 4'h1 : (_GEN_7 ? {2'h0, (io_config_in_valid ? 2'h1 : 2'h2)} : (_GEN_8 ? {2'h0, (io_config_in_valid ? 2'h1 : 2'h2)} : (_GEN_13 ? 4'h1 : {2'h0, instr_op == 4'h8, 1'h1}))))))), 4'h2, (io_start ? 4'h1 : state)};\n\t\t\tstate <= _GEN_23[state * 4+:4];\n\t\tend\n\t\tif (_GEN) begin\n\t\t\tif (io_start)\n\t\t\t\tpc <= 5'h00;\n\t\tend\n\t\telse if (_GEN_0) begin\n\t\t\tpc <= pc + 5'h01;\n\t\t\tmul_reg <= 28'h0000000;\n\t\tend\n\t\telse if ((~_GEN_1 | _GEN_12) | ~_GEN_4)\n\t\t\t;\n\t\telse\n\t\t\tmul_reg <= mul_reg + accum;\n\t\tif (_GEN | ~_GEN_0)\n\t\t\t;\n\t\telse begin : sv2v_autoblock_3\n\t\t\treg [127:0] _GEN_24;\n\t\t\t_GEN_24 = 128'h00000086252462507312312312121210;\n\t\t\tinstr_op <= _GEN_24[pc * 4+:4];\n\t\tend\n\t\t_GEN_22 = {instr_value, instr_value, instr_value, instr_value, instr_value, instr_value - 8'h01, (|instr_value ? instr_value - 8'h01 : 8'h80), (|instr_value ? instr_value - 8'h01 : 8'h3d), (|instr_value ? instr_value - 8'h01 : 8'h0b), (|instr_value ? instr_value - 8'h01 : 8'h01), (|instr_value ? instr_value - 8'h01 : 8'h1d), 8'h37, instr_value, (_GEN_12 | ~_GEN_4 ? instr_value : instr_value - 8'h01), _GEN_11[pc * 8+:8], instr_value};\n\t\tinstr_value <= _GEN_22[state * 8+:8];\n\t\tif (~_GEN_10) begin\n\t\t\tif (_GEN_1) begin\n\t\t\t\tif (_GEN_2)\n\t\t\t\t\taccum <= 28'h0000000;\n\t\t\t\telse begin : sv2v_autoblock_4\n\t\t\t\t\treg [27:0] _dec_res_T;\n\t\t\t\t\t_dec_res_T = accum + {21'h000000, ((_GEN_10 | ~_GEN_1) | _GEN_2 ? 7'h00 : (_GEN_3 ? (io_config_in_valid ? (io_config_in_bits == 8'h20 ? 7'h24 : (io_config_in_bits < 8'h3a ? io_config_in_bits[6:0] - 7'h30 : io_config_in_bits[6:0] - 7'h37)) : 7'h00) : (_GEN_4 | _GEN_9 ? 7'h00 : (_GEN_7 ? (io_config_in_valid ? io_config_in_bits[6:0] + 7'h3f : 7'h00) : (_GEN_8 & io_config_in_valid ? io_config_in_bits[6:0] - 7'h30 : 7'h00)))))};\n\t\t\t\t\tif (_GEN_3) begin\n\t\t\t\t\t\tif (io_config_in_valid)\n\t\t\t\t\t\t\taccum <= _dec_res_T;\n\t\t\t\t\tend\n\t\t\t\t\telse if (_GEN_4) begin\n\t\t\t\t\t\tif (~(|instr_value))\n\t\t\t\t\t\t\taccum <= mul_reg;\n\t\t\t\t\tend\n\t\t\t\t\telse if (_GEN_9) begin : sv2v_autoblock_5\n\t\t\t\t\t\treg _sub_res_T_2;\n\t\t\t\t\t\treg [27:0] _GEN_25;\n\t\t\t\t\t\t_sub_res_T_2 = instr_op == 4'h4;\n\t\t\t\t\t\t_GEN_25 = {20'h00000, instr_value};\n\t\t\t\t\t\taccum <= (_sub_res_T_2 ? _GEN_25 : accum) - (_sub_res_T_2 ? accum : _GEN_25);\n\t\t\t\t\tend\n\t\t\t\t\telse if ((_GEN_7 | _GEN_8) & io_config_in_valid)\n\t\t\t\t\t\taccum <= _dec_res_T;\n\t\t\t\tend\n\t\t\t\tif (((((((_GEN_2 | _GEN_3) | _GEN_4) | _GEN_5) | _GEN_6) | _GEN_7) | _GEN_8) | ~_GEN_13)\n\t\t\t\t\t;\n\t\t\t\telse\n\t\t\t\t\treg_n <= accum;\n\t\t\tend\n\t\t\telse begin\n\t\t\t\tif (((_GEN_14 | _GEN_15) | _GEN_16) | ~(_GEN_18 & ~instr_value[0]))\n\t\t\t\t\t;\n\t\t\t\telse\n\t\t\t\t\taccum <= {accum[26:0], 1'h0};\n\t\t\t\tif (_GEN_17 | ~(_GEN_16 & ~instr_value[0]))\n\t\t\t\t\t;\n\t\t\t\telse\n\t\t\t\t\treg_n <= {reg_n[26:0], 1'h0};\n\t\t\tend\n\t\tend\n\t\tif (~((_GEN | _GEN_0) | _GEN_1)) begin\n\t\t\tif (_GEN_14) begin\n\t\t\t\tif (io_config_in_valid)\n\t\t\t\t\tpower_dbm <= io_config_in_bits[5:0];\n\t\t\tend\n\t\t\telse if ((((_GEN_15 | _GEN_16) | _GEN_18) | _GEN_19) | ~(_GEN_20 & ~instr_value[0]))\n\t\t\t\t;\n\t\t\telse\n\t\t\t\tpower_dbm <= {power_dbm[4:0], 1'h0};\n\t\tend\n\t\tif (bit_tmp_valid)\n\t\t\tconv_reg <= {conv_reg[30:0], ~_GEN_21 & (_GEN_16 ? reg_n[27] : (_GEN_18 ? accum[14] : _GEN_19 | (_GEN_20 & power_dbm[5])))};\n\t\telse if (_GEN & io_start)\n\t\t\tconv_reg <= 32'h00000000;\n\t\tio_bit_out_REG_valid <= bit_out_tmp_valid_REG | bit_out_tmp_valid_REG_2;\n\t\tio_bit_out_REG_bits <= (REG_1 ? ^(conv_reg & 32'he4613c47) : ^(conv_reg & 32'hf2d05351));\n\t\tbit_out_tmp_valid_REG <= bit_tmp_valid;\n\t\tbit_out_tmp_valid_REG_1 <= bit_tmp_valid;\n\t\tbit_out_tmp_valid_REG_2 <= bit_out_tmp_valid_REG_1;\n\t\tREG <= bit_tmp_valid;\n\t\tREG_1 <= REG;\n\tend\n\tassign io_done = state == 4'hb;\n\tassign io_bit_out_valid = io_bit_out_REG_valid;\n\tassign io_bit_out_bits = io_bit_out_REG_bits;\nendmodule\nmodule BitGenerator (\n\tclock,\n\treset,\n\tio_config_in_valid,\n\tio_config_in_bits,\n\tio_start,\n\tio_bit_out_ready,\n\tio_bit_out_bits\n);\n\tinput clock;\n\tinput reset;\n\tinput io_config_in_valid;\n\tinput [7:0] io_config_in_bits;\n\tinput io_start;\n\tinput io_bit_out_ready;\n\toutput wire [1:0] io_bit_out_bits;\n\twire _se_io_done;\n\twire _se_io_bit_out_valid;\n\twire _se_io_bit_out_bits;\n\twire [255:0] _GEN = 256'hfffffffffffffffffffffffc63580ca0e2cdc9045634955858b340a407a47103;\n\treg regs_0;\n\treg regs_1;\n\treg regs_2;\n\treg regs_3;\n\treg regs_4;\n\treg regs_5;\n\treg regs_6;\n\treg regs_7;\n\treg regs_8;\n\treg regs_9;\n\treg regs_10;\n\treg regs_11;\n\treg regs_12;\n\treg regs_13;\n\treg regs_14;\n\treg regs_15;\n\treg regs_16;\n\treg regs_17;\n\treg regs_18;\n\treg regs_19;\n\treg regs_20;\n\treg regs_21;\n\treg regs_22;\n\treg regs_23;\n\treg regs_24;\n\treg regs_25;\n\treg regs_26;\n\treg regs_27;\n\treg regs_28;\n\treg regs_29;\n\treg regs_30;\n\treg regs_31;\n\treg regs_32;\n\treg regs_33;\n\treg regs_34;\n\treg regs_35;\n\treg regs_36;\n\treg regs_37;\n\treg regs_38;\n\treg regs_39;\n\treg regs_40;\n\treg regs_41;\n\treg regs_42;\n\treg regs_43;\n\treg regs_44;\n\treg regs_45;\n\treg regs_46;\n\treg regs_47;\n\treg regs_48;\n\treg regs_49;\n\treg regs_50;\n\treg regs_51;\n\treg regs_52;\n\treg regs_53;\n\treg regs_54;\n\treg regs_55;\n\treg regs_56;\n\treg regs_57;\n\treg regs_58;\n\treg regs_59;\n\treg regs_60;\n\treg regs_61;\n\treg regs_62;\n\treg regs_63;\n\treg regs_64;\n\treg regs_65;\n\treg regs_66;\n\treg regs_67;\n\treg regs_68;\n\treg regs_69;\n\treg regs_70;\n\treg regs_71;\n\treg regs_72;\n\treg regs_73;\n\treg regs_74;\n\treg regs_75;\n\treg regs_76;\n\treg regs_77;\n\treg regs_78;\n\treg regs_79;\n\treg regs_80;\n\treg regs_81;\n\treg regs_82;\n\treg regs_83;\n\treg regs_84;\n\treg regs_85;\n\treg regs_86;\n\treg regs_87;\n\treg regs_88;\n\treg regs_89;\n\treg regs_90;\n\treg regs_91;\n\treg regs_92;\n\treg regs_93;\n\treg regs_94;\n\treg regs_95;\n\treg regs_96;\n\treg regs_97;\n\treg regs_98;\n\treg regs_99;\n\treg regs_100;\n\treg regs_101;\n\treg regs_102;\n\treg regs_103;\n\treg regs_104;\n\treg regs_105;\n\treg regs_106;\n\treg regs_107;\n\treg regs_108;\n\treg regs_109;\n\treg regs_110;\n\treg regs_111;\n\treg regs_112;\n\treg regs_113;\n\treg regs_114;\n\treg regs_115;\n\treg regs_116;\n\treg regs_117;\n\treg regs_118;\n\treg regs_119;\n\treg regs_120;\n\treg regs_121;\n\treg regs_122;\n\treg regs_123;\n\treg regs_124;\n\treg regs_125;\n\treg regs_126;\n\treg regs_127;\n\treg regs_128;\n\treg regs_129;\n\treg regs_130;\n\treg regs_131;\n\treg regs_132;\n\treg regs_133;\n\treg regs_134;\n\treg regs_135;\n\treg regs_136;\n\treg regs_137;\n\treg regs_138;\n\treg regs_139;\n\treg regs_140;\n\treg regs_141;\n\treg regs_142;\n\treg regs_143;\n\treg regs_144;\n\treg regs_145;\n\treg regs_146;\n\treg regs_147;\n\treg regs_148;\n\treg regs_149;\n\treg regs_150;\n\treg regs_151;\n\treg regs_152;\n\treg regs_153;\n\treg regs_154;\n\treg regs_155;\n\treg regs_156;\n\treg regs_157;\n\treg regs_158;\n\treg regs_159;\n\treg regs_160;\n\treg regs_161;\n\treg [7:0] ctr;\n\talways @(posedge clock)\n\t\tif (io_bit_out_ready) begin\n\t\t\tregs_0 <= regs_81;\n\t\t\tregs_1 <= regs_82;\n\t\t\tregs_2 <= regs_83;\n\t\t\tregs_3 <= regs_84;\n\t\t\tregs_4 <= regs_85;\n\t\t\tregs_5 <= regs_86;\n\t\t\tregs_6 <= regs_87;\n\t\t\tregs_7 <= regs_88;\n\t\t\tregs_8 <= regs_89;\n\t\t\tregs_9 <= regs_90;\n\t\t\tregs_10 <= regs_91;\n\t\t\tregs_11 <= regs_92;\n\t\t\tregs_12 <= regs_93;\n\t\t\tregs_13 <= regs_94;\n\t\t\tregs_14 <= regs_95;\n\t\t\tregs_15 <= regs_96;\n\t\t\tregs_16 <= regs_97;\n\t\t\tregs_17 <= regs_98;\n\t\t\tregs_18 <= regs_99;\n\t\t\tregs_19 <= regs_100;\n\t\t\tregs_20 <= regs_101;\n\t\t\tregs_21 <= regs_102;\n\t\t\tregs_22 <= regs_103;\n\t\t\tregs_23 <= regs_104;\n\t\t\tregs_24 <= regs_105;\n\t\t\tregs_25 <= regs_106;\n\t\t\tregs_26 <= regs_107;\n\t\t\tregs_27 <= regs_108;\n\t\t\tregs_28 <= regs_109;\n\t\t\tregs_29 <= regs_110;\n\t\t\tregs_30 <= regs_111;\n\t\t\tregs_31 <= regs_112;\n\t\t\tregs_32 <= regs_113;\n\t\t\tregs_33 <= regs_114;\n\t\t\tregs_34 <= regs_115;\n\t\t\tregs_35 <= regs_116;\n\t\t\tregs_36 <= regs_117;\n\t\t\tregs_37 <= regs_118;\n\t\t\tregs_38 <= regs_119;\n\t\t\tregs_39 <= regs_120;\n\t\t\tregs_40 <= regs_121;\n\t\t\tregs_41 <= regs_122;\n\t\t\tregs_42 <= regs_123;\n\t\t\tregs_43 <= regs_124;\n\t\t\tregs_44 <= regs_125;\n\t\t\tregs_45 <= regs_126;\n\t\t\tregs_46 <= regs_127;\n\t\t\tregs_47 <= regs_128;\n\t\t\tregs_48 <= regs_129;\n\t\t\tregs_49 <= regs_130;\n\t\t\tregs_50 <= regs_131;\n\t\t\tregs_51 <= regs_132;\n\t\t\tregs_52 <= regs_133;\n\t\t\tregs_53 <= regs_134;\n\t\t\tregs_54 <= regs_135;\n\t\t\tregs_55 <= regs_136;\n\t\t\tregs_56 <= regs_137;\n\t\t\tregs_57 <= regs_138;\n\t\t\tregs_58 <= regs_139;\n\t\t\tregs_59 <= regs_140;\n\t\t\tregs_60 <= regs_141;\n\t\t\tregs_61 <= regs_142;\n\t\t\tregs_62 <= regs_143;\n\t\t\tregs_63 <= regs_144;\n\t\t\tregs_64 <= regs_145;\n\t\t\tregs_65 <= regs_146;\n\t\t\tregs_66 <= regs_147;\n\t\t\tregs_67 <= regs_148;\n\t\t\tregs_68 <= regs_149;\n\t\t\tregs_69 <= regs_150;\n\t\t\tregs_70 <= regs_151;\n\t\t\tregs_71 <= regs_152;\n\t\t\tregs_72 <= regs_153;\n\t\t\tregs_73 <= regs_154;\n\t\t\tregs_74 <= regs_155;\n\t\t\tregs_75 <= regs_156;\n\t\t\tregs_76 <= regs_157;\n\t\t\tregs_77 <= regs_158;\n\t\t\tregs_78 <= regs_159;\n\t\t\tregs_79 <= regs_160;\n\t\t\tregs_80 <= regs_161;\n\t\t\tregs_81 <= regs_41;\n\t\t\tregs_82 <= regs_42;\n\t\t\tregs_83 <= regs_43;\n\t\t\tregs_84 <= regs_44;\n\t\t\tregs_85 <= regs_0;\n\t\t\tregs_86 <= regs_45;\n\t\t\tregs_87 <= regs_46;\n\t\t\tregs_88 <= regs_47;\n\t\t\tregs_89 <= regs_48;\n\t\t\tregs_90 <= regs_49;\n\t\t\tregs_91 <= regs_50;\n\t\t\tregs_92 <= regs_51;\n\t\t\tregs_93 <= regs_52;\n\t\t\tregs_94 <= regs_53;\n\t\t\tregs_95 <= regs_54;\n\t\t\tregs_96 <= regs_55;\n\t\t\tregs_97 <= regs_56;\n\t\t\tregs_98 <= regs_57;\n\t\t\tregs_99 <= regs_58;\n\t\t\tregs_100 <= regs_59;\n\t\t\tregs_101 <= regs_60;\n\t\t\tregs_102 <= regs_61;\n\t\t\tregs_103 <= regs_62;\n\t\t\tregs_104 <= regs_63;\n\t\t\tregs_105 <= regs_64;\n\t\t\tregs_106 <= regs_65;\n\t\t\tregs_107 <= regs_66;\n\t\t\tregs_108 <= regs_67;\n\t\t\tregs_109 <= regs_68;\n\t\t\tregs_110 <= regs_69;\n\t\t\tregs_111 <= regs_70;\n\t\t\tregs_112 <= regs_71;\n\t\t\tregs_113 <= regs_72;\n\t\t\tregs_114 <= regs_73;\n\t\t\tregs_115 <= regs_74;\n\t\t\tregs_116 <= regs_75;\n\t\t\tregs_117 <= regs_76;\n\t\t\tregs_118 <= regs_77;\n\t\t\tregs_119 <= regs_78;\n\t\t\tregs_120 <= regs_79;\n\t\t\tregs_121 <= regs_80;\n\t\t\tregs_122 <= regs_21;\n\t\t\tregs_123 <= regs_22;\n\t\t\tregs_124 <= regs_23;\n\t\t\tregs_125 <= regs_24;\n\t\t\tregs_126 <= regs_25;\n\t\t\tregs_127 <= regs_26;\n\t\t\tregs_128 <= regs_27;\n\t\t\tregs_129 <= regs_28;\n\t\t\tregs_130 <= regs_29;\n\t\t\tregs_131 <= regs_30;\n\t\t\tregs_132 <= regs_31;\n\t\t\tregs_133 <= regs_32;\n\t\t\tregs_134 <= regs_33;\n\t\t\tregs_135 <= regs_34;\n\t\t\tregs_136 <= regs_35;\n\t\t\tregs_137 <= regs_36;\n\t\t\tregs_138 <= regs_37;\n\t\t\tregs_139 <= regs_38;\n\t\t\tregs_140 <= regs_39;\n\t\t\tregs_141 <= regs_40;\n\t\t\tregs_142 <= regs_11;\n\t\t\tregs_143 <= regs_12;\n\t\t\tregs_144 <= regs_13;\n\t\t\tregs_145 <= regs_14;\n\t\t\tregs_146 <= regs_15;\n\t\t\tregs_147 <= regs_16;\n\t\t\tregs_148 <= regs_17;\n\t\t\tregs_149 <= regs_18;\n\t\t\tregs_150 <= regs_19;\n\t\t\tregs_151 <= regs_20;\n\t\t\tregs_152 <= regs_6;\n\t\t\tregs_153 <= regs_7;\n\t\t\tregs_154 <= regs_8;\n\t\t\tregs_155 <= regs_9;\n\t\t\tregs_156 <= regs_10;\n\t\t\tregs_157 <= regs_3;\n\t\t\tregs_158 <= regs_4;\n\t\t\tregs_159 <= regs_5;\n\t\t\tregs_160 <= regs_2;\n\t\t\tregs_161 <= regs_1;\n\t\t\tctr <= ctr + 8'h01;\n\t\tend\n\t\telse begin\n\t\t\tif (_se_io_bit_out_valid) begin\n\t\t\t\tregs_0 <= regs_1;\n\t\t\t\tregs_1 <= regs_2;\n\t\t\t\tregs_2 <= regs_3;\n\t\t\t\tregs_3 <= regs_4;\n\t\t\t\tregs_4 <= regs_5;\n\t\t\t\tregs_5 <= regs_6;\n\t\t\t\tregs_6 <= regs_7;\n\t\t\t\tregs_7 <= regs_8;\n\t\t\t\tregs_8 <= regs_9;\n\t\t\t\tregs_9 <= regs_10;\n\t\t\t\tregs_10 <= regs_11;\n\t\t\t\tregs_11 <= regs_12;\n\t\t\t\tregs_12 <= regs_13;\n\t\t\t\tregs_13 <= regs_14;\n\t\t\t\tregs_14 <= regs_15;\n\t\t\t\tregs_15 <= regs_16;\n\t\t\t\tregs_16 <= regs_17;\n\t\t\t\tregs_17 <= regs_18;\n\t\t\t\tregs_18 <= regs_19;\n\t\t\t\tregs_19 <= regs_20;\n\t\t\t\tregs_20 <= regs_21;\n\t\t\t\tregs_21 <= regs_22;\n\t\t\t\tregs_22 <= regs_23;\n\t\t\t\tregs_23 <= regs_24;\n\t\t\t\tregs_24 <= regs_25;\n\t\t\t\tregs_25 <= regs_26;\n\t\t\t\tregs_26 <= regs_27;\n\t\t\t\tregs_27 <= regs_28;\n\t\t\t\tregs_28 <= regs_29;\n\t\t\t\tregs_29 <= regs_30;\n\t\t\t\tregs_30 <= regs_31;\n\t\t\t\tregs_31 <= regs_32;\n\t\t\t\tregs_32 <= regs_33;\n\t\t\t\tregs_33 <= regs_34;\n\t\t\t\tregs_34 <= regs_35;\n\t\t\t\tregs_35 <= regs_36;\n\t\t\t\tregs_36 <= regs_37;\n\t\t\t\tregs_37 <= regs_38;\n\t\t\t\tregs_38 <= regs_39;\n\t\t\t\tregs_39 <= regs_40;\n\t\t\t\tregs_40 <= regs_41;\n\t\t\t\tregs_41 <= regs_42;\n\t\t\t\tregs_42 <= regs_43;\n\t\t\t\tregs_43 <= regs_44;\n\t\t\t\tregs_44 <= regs_45;\n\t\t\t\tregs_45 <= regs_46;\n\t\t\t\tregs_46 <= regs_47;\n\t\t\t\tregs_47 <= regs_48;\n\t\t\t\tregs_48 <= regs_49;\n\t\t\t\tregs_49 <= regs_50;\n\t\t\t\tregs_50 <= regs_51;\n\t\t\t\tregs_51 <= regs_52;\n\t\t\t\tregs_52 <= regs_53;\n\t\t\t\tregs_53 <= regs_54;\n\t\t\t\tregs_54 <= regs_55;\n\t\t\t\tregs_55 <= regs_56;\n\t\t\t\tregs_56 <= regs_57;\n\t\t\t\tregs_57 <= regs_58;\n\t\t\t\tregs_58 <= regs_59;\n\t\t\t\tregs_59 <= regs_60;\n\t\t\t\tregs_60 <= regs_61;\n\t\t\t\tregs_61 <= regs_62;\n\t\t\t\tregs_62 <= regs_63;\n\t\t\t\tregs_63 <= regs_64;\n\t\t\t\tregs_64 <= regs_65;\n\t\t\t\tregs_65 <= regs_66;\n\t\t\t\tregs_66 <= regs_67;\n\t\t\t\tregs_67 <= regs_68;\n\t\t\t\tregs_68 <= regs_69;\n\t\t\t\tregs_69 <= regs_70;\n\t\t\t\tregs_70 <= regs_71;\n\t\t\t\tregs_71 <= regs_72;\n\t\t\t\tregs_72 <= regs_73;\n\t\t\t\tregs_73 <= regs_74;\n\t\t\t\tregs_74 <= regs_75;\n\t\t\t\tregs_75 <= regs_76;\n\t\t\t\tregs_76 <= regs_77;\n\t\t\t\tregs_77 <= regs_78;\n\t\t\t\tregs_78 <= regs_79;\n\t\t\t\tregs_79 <= regs_80;\n\t\t\t\tregs_80 <= regs_81;\n\t\t\t\tregs_81 <= regs_82;\n\t\t\t\tregs_82 <= regs_83;\n\t\t\t\tregs_83 <= regs_84;\n\t\t\t\tregs_84 <= regs_85;\n\t\t\t\tregs_85 <= regs_86;\n\t\t\t\tregs_86 <= regs_87;\n\t\t\t\tregs_87 <= regs_88;\n\t\t\t\tregs_88 <= regs_89;\n\t\t\t\tregs_89 <= regs_90;\n\t\t\t\tregs_90 <= regs_91;\n\t\t\t\tregs_91 <= regs_92;\n\t\t\t\tregs_92 <= regs_93;\n\t\t\t\tregs_93 <= regs_94;\n\t\t\t\tregs_94 <= regs_95;\n\t\t\t\tregs_95 <= regs_96;\n\t\t\t\tregs_96 <= regs_97;\n\t\t\t\tregs_97 <= regs_98;\n\t\t\t\tregs_98 <= regs_99;\n\t\t\t\tregs_99 <= regs_100;\n\t\t\t\tregs_100 <= regs_101;\n\t\t\t\tregs_101 <= regs_102;\n\t\t\t\tregs_102 <= regs_103;\n\t\t\t\tregs_103 <= regs_104;\n\t\t\t\tregs_104 <= regs_105;\n\t\t\t\tregs_105 <= regs_106;\n\t\t\t\tregs_106 <= regs_107;\n\t\t\t\tregs_107 <= regs_108;\n\t\t\t\tregs_108 <= regs_109;\n\t\t\t\tregs_109 <= regs_110;\n\t\t\t\tregs_110 <= regs_111;\n\t\t\t\tregs_111 <= regs_112;\n\t\t\t\tregs_112 <= regs_113;\n\t\t\t\tregs_113 <= regs_114;\n\t\t\t\tregs_114 <= regs_115;\n\t\t\t\tregs_115 <= regs_116;\n\t\t\t\tregs_116 <= regs_117;\n\t\t\t\tregs_117 <= regs_118;\n\t\t\t\tregs_118 <= regs_119;\n\t\t\t\tregs_119 <= regs_120;\n\t\t\t\tregs_120 <= regs_121;\n\t\t\t\tregs_121 <= regs_122;\n\t\t\t\tregs_122 <= regs_123;\n\t\t\t\tregs_123 <= regs_124;\n\t\t\t\tregs_124 <= regs_125;\n\t\t\t\tregs_125 <= regs_126;\n\t\t\t\tregs_126 <= regs_127;\n\t\t\t\tregs_127 <= regs_128;\n\t\t\t\tregs_128 <= regs_129;\n\t\t\t\tregs_129 <= regs_130;\n\t\t\t\tregs_130 <= regs_131;\n\t\t\t\tregs_131 <= regs_132;\n\t\t\t\tregs_132 <= regs_133;\n\t\t\t\tregs_133 <= regs_134;\n\t\t\t\tregs_134 <= regs_135;\n\t\t\t\tregs_135 <= regs_136;\n\t\t\t\tregs_136 <= regs_137;\n\t\t\t\tregs_137 <= regs_138;\n\t\t\t\tregs_138 <= regs_139;\n\t\t\t\tregs_139 <= regs_140;\n\t\t\t\tregs_140 <= regs_141;\n\t\t\t\tregs_141 <= regs_142;\n\t\t\t\tregs_142 <= regs_143;\n\t\t\t\tregs_143 <= regs_144;\n\t\t\t\tregs_144 <= regs_145;\n\t\t\t\tregs_145 <= regs_146;\n\t\t\t\tregs_146 <= regs_147;\n\t\t\t\tregs_147 <= regs_148;\n\t\t\t\tregs_148 <= regs_149;\n\t\t\t\tregs_149 <= regs_150;\n\t\t\t\tregs_150 <= regs_151;\n\t\t\t\tregs_151 <= regs_152;\n\t\t\t\tregs_152 <= regs_153;\n\t\t\t\tregs_153 <= regs_154;\n\t\t\t\tregs_154 <= regs_155;\n\t\t\t\tregs_155 <= regs_156;\n\t\t\t\tregs_156 <= regs_157;\n\t\t\t\tregs_157 <= regs_158;\n\t\t\t\tregs_158 <= regs_159;\n\t\t\t\tregs_159 <= regs_160;\n\t\t\t\tregs_160 <= regs_161;\n\t\t\t\tregs_161 <= _se_io_bit_out_bits;\n\t\t\tend\n\t\t\tif (_se_io_done)\n\t\t\t\tctr <= 8'h00;\n\t\tend\n\tStringEncoder se(\n\t\t.clock(clock),\n\t\t.reset(reset),\n\t\t.io_config_in_valid(io_config_in_valid),\n\t\t.io_config_in_bits(io_config_in_bits),\n\t\t.io_start(io_start),\n\t\t.io_done(_se_io_done),\n\t\t.io_bit_out_valid(_se_io_bit_out_valid),\n\t\t.io_bit_out_bits(_se_io_bit_out_bits)\n\t);\n\tassign io_bit_out_bits = {regs_0, _GEN[ctr]};\nendmodule\nmodule TopLevel (\n\tclock,\n\treset,\n\tio_config_bits_in,\n\tio_config_valid_in,\n\tio_config_start,\n\tio_rf_start,\n\tio_rf_out,\n\tio_bit_out\n);\n\tinput clock;\n\tinput reset;\n\tinput [7:0] io_config_bits_in;\n\tinput io_config_valid_in;\n\tinput io_config_start;\n\tinput io_rf_start;\n\toutput wire io_rf_out;\n\toutput wire [1:0] io_bit_out;\n\twire [1:0] _se_io_bit_out_bits;\n\treg [7:0] config_regs_0;\n\treg [7:0] config_regs_1;\n\treg [7:0] config_regs_2;\n\treg [7:0] config_regs_3;\n\treg [7:0] config_regs_4;\n\treg [7:0] config_regs_5;\n\treg [7:0] config_regs_6;\n\treg [7:0] config_regs_7;\n\treg [7:0] config_regs_8;\n\treg [7:0] config_regs_9;\n\treg [31:0] symbol_time_ctr;\n\treg [31:0] osc_time_ctr;\n\treg [7:0] symbol_ctr;\n\twire _GEN = symbol_time_ctr == 32'h00000000;\n\talways @(posedge clock) begin : sv2v_autoblock_1\n\t\treg [31:0] symbol_time;\n\t\tsymbol_time = {config_regs_0, config_regs_1, config_regs_2, config_regs_3};\n\t\tif (io_config_valid_in) begin\n\t\t\tconfig_regs_0 <= config_regs_1;\n\t\t\tconfig_regs_1 <= config_regs_2;\n\t\t\tconfig_regs_2 <= config_regs_3;\n\t\t\tconfig_regs_3 <= config_regs_4;\n\t\t\tconfig_regs_4 <= config_regs_5;\n\t\t\tconfig_regs_5 <= config_regs_6;\n\t\t\tconfig_regs_6 <= config_regs_7;\n\t\t\tconfig_regs_7 <= config_regs_8;\n\t\t\tconfig_regs_8 <= config_regs_9;\n\t\t\tconfig_regs_9 <= io_config_bits_in;\n\t\tend\n\t\tif (_GEN) begin\n\t\t\tsymbol_time_ctr <= symbol_time;\n\t\t\tsymbol_ctr <= symbol_ctr - 8'h01;\n\t\tend\n\t\telse begin\n\t\t\tif (|symbol_ctr)\n\t\t\t\tsymbol_time_ctr <= symbol_time_ctr - 32'h00000001;\n\t\t\telse if (io_rf_start)\n\t\t\t\tsymbol_time_ctr <= symbol_time;\n\t\t\tif (io_rf_start)\n\t\t\t\tsymbol_ctr <= 8'ha2;\n\t\tend\n\t\tif (|symbol_ctr)\n\t\t\tosc_time_ctr <= (osc_time_ctr + {config_regs_4, config_regs_5, config_regs_6, config_regs_7}) + {14'h0000, {16'h0000, _se_io_bit_out_bits} * {2'h0, config_regs_8, config_regs_9}};\n\t\telse if (io_rf_start)\n\t\t\tosc_time_ctr <= 32'h00000000;\n\tend\n\tBitGenerator se(\n\t\t.clock(clock),\n\t\t.reset(reset),\n\t\t.io_config_in_valid(io_config_valid_in),\n\t\t.io_config_in_bits(io_config_bits_in),\n\t\t.io_start(io_config_start),\n\t\t.io_bit_out_ready(_GEN),\n\t\t.io_bit_out_bits(_se_io_bit_out_bits)\n\t);\n\tassign io_rf_out = osc_time_ctr[31];\n\tassign io_bit_out = _se_io_bit_out_bits;\nendmodule\n", "mask_idx": {"conditional_statement": [[6884, 7018], [6780, 7018], [20396, 20437], [20260, 20392]], "blocking_assignment": [[3427, 3608], [19680, 19755], [3265, 3293], [3323, 3347], [3184, 3208]], "module_program_interface_instantiation": [[18537, 18807], [20709, 20944], [1339, 1643]], "always_construct": [[933, 1063], [1140, 1333], [736, 886], [19603, 20707], [2774, 7582], [10519, 18535]], "ansi_port_declaration": [[7761, 7780], [301, 348], [18920, 18939]], "continuous_assign": [[18809, 18854], [1683, 1706], [7584, 7615]], "nonblocking_assignment": [[19966, 19997], [12155, 12175], [17698, 17719], [15833, 15852], [13167, 13187], [15881, 15900], [14594, 14611], [12927, 12947], [10796, 10815]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1339, 1643], [18537, 18807], [20709, 20944]], "continuous_assign": [[634, 653], [658, 677], [1649, 1678], [1683, 1706], [7584, 7615], [7617, 7664], [7666, 7711], [18809, 18854], [20946, 20982], [20984, 21024]], "blocking_assignment": [[3042, 3122], [3125, 3151], [3154, 3181], [3184, 3208], [3211, 3235], [3238, 3262], [3265, 3293], [3296, 3320], [3323, 3347], [3350, 3374], [3377, 3424], [3427, 3608], [3698, 4310], [4660, 4708], [4752, 5189], [5383, 5810], [6093, 6125], [6132, 6167], [19680, 19755]], "nonblocking_assignment": [[772, 798], [807, 838], [847, 878], [969, 991], [1000, 1023], [1032, 1055], [1176, 1202], [1211, 1242], [1251, 1282], [1291, 1325], [3625, 3639], [4314, 4345], [4391, 4403], [4438, 4455], [4459, 4482], [4546, 4573], [4712, 4743], [5192, 5229], [5294, 5315], [5871, 5891], [5963, 5980], [6174, 6251], [6321, 6341], [6464, 6479], [6594, 6623], [6693, 6722], [6832, 6868], [6982, 7018], [7049, 7173], [7205, 7230], [7233, 7305], [7308, 7397], [7400, 7439], [7442, 7483], [7486, 7537], [7540, 7561], [7564, 7577], [10576, 10594], [10598, 10616], [10620, 10638], [10642, 10660], [10664, 10682], [10686, 10704], [10708, 10726], [10730, 10748], [10752, 10770], [10774, 10792], [10796, 10815], [10819, 10838], [10842, 10861], [10865, 10884], [10888, 10907], [10911, 10930], [10934, 10953], [10957, 10976], [10980, 10999], [11003, 11023], [11027, 11047], [11051, 11071], [11075, 11095], [11099, 11119], [11123, 11143], [11147, 11167], [11171, 11191], [11195, 11215], [11219, 11239], [11243, 11263], [11267, 11287], [11291, 11311], [11315, 11335], [11339, 11359], [11363, 11383], [11387, 11407], [11411, 11431], [11435, 11455], [11459, 11479], [11483, 11503], [11507, 11527], [11531, 11551], [11555, 11575], [11579, 11599], [11603, 11623], [11627, 11647], [11651, 11671], [11675, 11695], [11699, 11719], [11723, 11743], [11747, 11767], [11771, 11791], [11795, 11815], [11819, 11839], [11843, 11863], [11867, 11887], [11891, 11911], [11915, 11935], [11939, 11959], [11963, 11983], [11987, 12007], [12011, 12031], [12035, 12055], [12059, 12079], [12083, 12103], [12107, 12127], [12131, 12151], [12155, 12175], [12179, 12199], [12203, 12223], [12227, 12247], [12251, 12271], [12275, 12295], [12299, 12319], [12323, 12343], [12347, 12367], [12371, 12391], [12395, 12415], [12419, 12439], [12443, 12463], [12467, 12487], [12491, 12510], [12514, 12533], [12537, 12556], [12560, 12579], [12583, 12601], [12605, 12624], [12628, 12647], [12651, 12670], [12674, 12693], [12697, 12716], [12720, 12739], [12743, 12762], [12766, 12785], [12789, 12808], [12812, 12831], [12835, 12854], [12858, 12877], [12881, 12900], [12904, 12923], [12927, 12947], [12951, 12971], [12975, 12995], [12999, 13019], [13023, 13043], [13047, 13067], [13071, 13091], [13095, 13115], [13119, 13139], [13143, 13163], [13167, 13187], [13191, 13211], [13215, 13235], [13239, 13259], [13263, 13283], [13287, 13307], [13311, 13331], [13335, 13355], [13359, 13379], [13383, 13403], [13407, 13427], [13431, 13451], [13455, 13475], [13479, 13499], [13503, 13523], [13527, 13547], [13551, 13571], [13575, 13595], [13599, 13619], [13623, 13643], [13647, 13667], [13671, 13691], [13695, 13715], [13719, 13739], [13743, 13763], [13767, 13787], [13791, 13811], [13815, 13835], [13839, 13859], [13863, 13883], [13887, 13907], [13911, 13931], [13935, 13955], [13959, 13979], [13983, 14003], [14007, 14027], [14031, 14051], [14055, 14075], [14079, 14099], [14103, 14123], [14127, 14147], [14151, 14171], [14175, 14194], [14198, 14217], [14221, 14240], [14244, 14263], [14267, 14287], [14291, 14310], [14314, 14333], [14337, 14356], [14360, 14379], [14383, 14402], [14406, 14425], [14484, 14501], [14506, 14523], [14528, 14545], [14550, 14567], [14572, 14589], [14594, 14611], [14616, 14633], [14638, 14655], [14660, 14677], [14682, 14700], [14705, 14724], [14729, 14748], [14753, 14772], [14777, 14796], [14801, 14820], [14825, 14844], [14849, 14868], [14873, 14892], [14897, 14916], [14921, 14940], [14945, 14964], [14969, 14988], [14993, 15012], [15017, 15036], [15041, 15060], [15065, 15084], [15089, 15108], [15113, 15132], [15137, 15156], [15161, 15180], [15185, 15204], [15209, 15228], [15233, 15252], [15257, 15276], [15281, 15300], [15305, 15324], [15329, 15348], [15353, 15372], [15377, 15396], [15401, 15420], [15425, 15444], [15449, 15468], [15473, 15492], [15497, 15516], [15521, 15540], [15545, 15564], [15569, 15588], [15593, 15612], [15617, 15636], [15641, 15660], [15665, 15684], [15689, 15708], [15713, 15732], [15737, 15756], [15761, 15780], [15785, 15804], [15809, 15828], [15833, 15852], [15857, 15876], [15881, 15900], [15905, 15924], [15929, 15948], [15953, 15972], [15977, 15996], [16001, 16020], [16025, 16044], [16049, 16068], [16073, 16092], [16097, 16116], [16121, 16140], [16145, 16164], [16169, 16188], [16193, 16212], [16217, 16236], [16241, 16260], [16265, 16284], [16289, 16308], [16313, 16332], [16337, 16356], [16361, 16380], [16385, 16404], [16409, 16428], [16433, 16452], [16457, 16476], [16481, 16500], [16505, 16524], [16529, 16548], [16553, 16572], [16577, 16596], [16601, 16620], [16625, 16644], [16649, 16668], [16673, 16692], [16697, 16716], [16721, 16740], [16745, 16764], [16769, 16788], [16793, 16812], [16817, 16836], [16841, 16861], [16866, 16887], [16892, 16913], [16918, 16939], [16944, 16965], [16970, 16991], [16996, 17017], [17022, 17043], [17048, 17069], [17074, 17095], [17100, 17121], [17126, 17147], [17152, 17173], [17178, 17199], [17204, 17225], [17230, 17251], [17256, 17277], [17282, 17303], [17308, 17329], [17334, 17355], [17360, 17381], [17386, 17407], [17412, 17433], [17438, 17459], [17464, 17485], [17490, 17511], [17516, 17537], [17542, 17563], [17568, 17589], [17594, 17615], [17620, 17641], [17646, 17667], [17672, 17693], [17698, 17719], [17724, 17745], [17750, 17771], [17776, 17797], [17802, 17823], [17828, 17849], [17854, 17875], [17880, 17901], [17906, 17927], [17932, 17953], [17958, 17979], [17984, 18005], [18010, 18031], [18036, 18057], [18062, 18083], [18088, 18109], [18114, 18135], [18140, 18161], [18166, 18187], [18192, 18213], [18218, 18239], [18244, 18265], [18270, 18291], [18296, 18317], [18322, 18343], [18348, 18369], [18374, 18395], [18400, 18421], [18426, 18447], [18452, 18484], [18516, 18529], [19791, 19822], [19826, 19857], [19861, 19892], [19896, 19927], [19931, 19962], [19966, 19997], [20001, 20032], [20036, 20067], [20071, 20102], [20106, 20141], [20169, 20200], [20204, 20237], [20281, 20331], [20361, 20392], [20417, 20437], [20466, 20645], [20673, 20702]], "case_statement": [], "conditional_statement": [[3611, 4351], [4354, 4573], [4373, 4403], [4417, 4573], [4496, 4573], [4576, 4749], [5232, 6735], [5255, 6729], [5277, 6349], [5816, 6341], [5840, 5891], [5911, 6341], [5935, 5980], [6000, 6341], [6271, 6341], [6354, 6479], [6505, 6623], [6628, 6722], [6738, 7024], [6780, 7018], [6803, 6868], [6884, 7018], [7027, 7230], [7181, 7230], [10545, 18535], [14448, 18491], [18495, 18529], [19758, 20147], [20150, 20443], [20260, 20392], [20340, 20392], [20396, 20437], [20446, 20702], [20653, 20702]], "always_construct": [[736, 886], [933, 1063], [1140, 1333], [2774, 7582], [10519, 18535], [19603, 20707]], "parameter_declaration": [], "ansi_port_declaration": [[145, 192], [197, 245], [250, 296], [301, 348], [353, 433], [438, 526], [531, 567], [572, 625], [1744, 1750], [1752, 1758], [1760, 1779], [1781, 1799], [1801, 1810], [1812, 1820], [1822, 1839], [1841, 1856], [7745, 7751], [7753, 7759], [7761, 7780], [7782, 7800], [7802, 7811], [7813, 7830], [7832, 7847], [18884, 18890], [18892, 18898], [18900, 18918], [18920, 18939], [18941, 18957], [18959, 18971], [18973, 18983], [18985, 18995]]}}
{"sample_i": "barakhoffer-tt07-vga-snake", "topmodule": "tt_um_vga_snake", "code": "/*\n * Copyright (c) 2024 Barak Hoffer\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_vga_snake (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  // All output pins must be assigned. If not used, assign to 0.\n  assign uio_out = 0;\n  assign uio_oe  = 0;\n\n  assign uio_out = 8'b0;\n  assign uio_oe  = 8'b0;\n\n  // List all unused inputs to prevent warnings\n  wire _unused = &{ena, uio_in, ui_in[7:4], 1'b0};\n\n  wire [5:0] rrggbb, rrggbb_snake;\n  wire [9:0] x_px;  // X position for actual pixel.\n  wire [9:0] y_px;  // Y position for actual pixel.\n  wire hsync, vsync, activevideo;\n\n  assign uo_out[0] = rrggbb[5]; // R[1]\n  assign uo_out[1] = rrggbb[3]; // G[1]\n  assign uo_out[2] = rrggbb[1]; // B[1]\n  assign uo_out[3] = vsync;\n  assign uo_out[4] = rrggbb[4]; // R[0]\n  assign uo_out[5] = rrggbb[2]; // G[1]\n  assign uo_out[6] = rrggbb[0]; // B[0]\n  assign uo_out[7] = hsync;\n\n  assign rrggbb = activevideo ? rrggbb_snake : 6'b0;\n\n  VgaSyncGen vga_0 (\n      .px_clk(clk),\n      .hsync(hsync),\n      .vsync(vsync),\n      .x_px(x_px),\n      .y_px(y_px),\n      .activevideo(activevideo),\n      .reset(~rst_n)\n  );\n\n  snake u_snake (\n        .clk(clk),\n        .rst_n(rst_n),\n        .x_px(x_px),\n        .y_px(y_px),\n        .left(ui_in[0]),\n        .right(ui_in[1]),\n        .up(ui_in[2]),\n        .down(ui_in[3]),\n        .rrggbb(rrggbb_snake)\n  );\n\nendmodule\n\n\n`default_nettype none\n//////////////////////////////////////////////////////////////////////////////////\n// Company: Ridotech\n// Engineer: Juan Manuel Rico\n// \n// Create Date:    09:34:23 30/09/2017 \n// Module Name:    vga_controller\n// Description:    Basic control for 640x480@72Hz VGA signal.\n//\n// Dependencies: \n//\n// Revision: \n// Revision 0.01 - File Created for Roland Coeurjoly (RCoeurjoly) in 640x480@85Hz.\n// Revision 0.02 - Change for 640x480@60Hz.\n// Revision 0.03 - Solved some mistakes.\n// Revision 0.04 - Change for 640x480@72Hz and output signals 'activevideo'\n//                 and 'px_clk'.\n//\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule VgaSyncGen (\n            input wire       px_clk,        // Input clock: 31.5MHz\n            input wire       reset,         // reset\n            output wire      hsync,         // Horizontal sync out\n            output wire      vsync,         // Vertical sync out\n            output reg [9:0] x_px,          // X position for actual pixel.\n            output reg [9:0] y_px,          // Y position for actual pixel.\n            output wire      activevideo\n         );\n\n    /*\n    http://www.epanorama.net/faq/vga2rgb/calc.html\n    [*User-Defined_mode,(640X480)]\n    PIXEL_CLK   =   31500\n    H_DISP      =   640\n    V_DISP      =   480\n    H_FPORCH    =   24\n    H_SYNC      =   40\n    H_BPORCH    =   128\n    V_FPORCH    =   9\n    V_SYNC      =   3\n    V_BPORCH    =   28\n    */\n\n    // Video structure constants.\n    parameter activeHvideo = 640;               // Width of visible pixels.\n    parameter activeVvideo =  480;              // Height of visible lines.\n    parameter hfp = 24;                         // Horizontal front porch length.\n    parameter hpulse = 40;                      // Hsync pulse length.\n    parameter hbp = 128;                        // Horizontal back porch length.\n    parameter vfp = 9;                          // Vertical front porch length.\n    parameter vpulse = 3;                       // Vsync pulse length.\n    parameter vbp = 28;                         // Vertical back porch length.\n    parameter blackH = hfp + hpulse + hbp;      // Hide pixels in one line.\n    parameter blackV = vfp + vpulse + vbp;      // Hide lines in one frame.\n    parameter hpixels = blackH + activeHvideo;  // Total horizontal pixels.\n    parameter vlines = blackV + activeVvideo;   // Total lines.\n\n    // Registers for storing the horizontal & vertical counters.\n    reg [9:0] hc;\n    reg [9:0] vc;\n\n    // Counting pixels.\n    always @(posedge px_clk)\n    begin\n        if(reset) begin\n            hc <= 0;\n            vc <= 0;\n        end else begin\n            // Keep counting until the end of the line.\n            if (hc < hpixels - 1)\n                hc <= hc + 1;\n            else\n            // When we hit the end of the line, reset the horizontal\n            // counter and increment the vertical counter.\n            // If vertical counter is at the end of the frame, then\n            // reset that one too.\n            begin\n                hc <= 0;\n                if (vc < vlines - 1)\n                vc <= vc + 1;\n            else\n               vc <= 0;\n            end\n        end\n     end\n\n    // Generate sync pulses (active low) and active video.\n    assign hsync = (hc >= hfp && hc < hfp + hpulse) ? 0:1;\n    assign vsync = (vc >= vfp && vc < vfp + vpulse) ? 0:1;\n    assign activevideo = (hc >= blackH && vc >= blackV) ? 1:0;\n\n    // Generate color.\n    always @(posedge px_clk)\n    begin\n        if(reset) begin\n            x_px <= 0;\n            y_px <= 0;\n        end else begin\n            x_px <= hc - blackH;\n            y_px <= vc - blackV;\n        end\n     end\n endmodule\n`default_nettype wire\n\n\nmodule snake(clk, rst_n, x_px, y_px, rrggbb, left, right, up, down);\n    input clk;\n    input rst_n;\n    input [9:0] x_px;\n    input [9:0] y_px;\n    input left;\n    input right;\n    input up;\n    input down;\n    output wire [5:0] rrggbb;\n\n    localparam MAX_SIZE = 6;\n\n    reg [MAX_SIZE*10-1:0] snakeX = {(MAX_SIZE){10'd100}}, snakeY={(MAX_SIZE){10'd100}};\n    reg [9:0] appleX = 10'd150, appleY = 10'd150;\n    reg [9:0] prev_y;\n    reg [2:0] size = 3'd0;\n    reg [9:0] appleX_n, appleY_n;\n    reg [1:0] direction = 2'b01;\n    reg eat_apple;\n    reg game_over;\n    \n    wire [MAX_SIZE-1:0] body;\n    wire [MAX_SIZE-1:0] bodySize;\n    wire clk;\n    wire border, apple;\n    wire R, G, B;\n    \n    assign R = game_over | apple;\n    assign bodySize = body[MAX_SIZE-1:0] & ({(MAX_SIZE){1'b1}} >> (MAX_SIZE-size-1));\n    assign G = (|bodySize) && !game_over;\n    assign B = border && !game_over;\n\n    assign rrggbb = {R, R, G, G, B, B};\n    \n    always @(posedge clk) begin\n        if (!rst_n) \n            direction <= 2'b01;\n        else if (left)\n            direction <= 2'b00;\n        else if (right)\n            direction <= 2'b01;\n        else if (up)\n            direction <= 2'b10;\n        else if (down)\n            direction <= 2'b11;\n    end\n\n    always @(posedge clk)\n    begin\n        if(!rst_n)\n            game_over <= 1'b0;\n        else if((border && bodySize[0]) || (|(bodySize[MAX_SIZE-1:1]) && bodySize[0])) \n            game_over <= 1'b1;\n    end\n\n    generate\n        genvar i;\n        for (i = 0; i < MAX_SIZE; i = i+1) begin\n            assign body[i] = ((x_px > snakeX[i*10+9:i*10] && x_px < snakeX[i*10+9:i*10]+10) && \n                                (y_px > snakeY[i*10+9:i*10] && y_px < snakeY[i*10+9:i*10]+10));\n        end\n    endgenerate\n\n    assign border = (x_px < 11) || (x_px > 629) || (y_px < 11) || (y_px > 469);\n    assign apple = ((x_px > appleX && x_px < appleX+10) && \n                 (y_px > appleY && y_px < appleY+10));    \n        \n    always @*\n    begin\n        case(direction)\n            2'b00: begin\n                appleX_n = appleX + 30;\n                appleY_n = appleY + 120;\n            end\n            2'b01: begin\n                appleX_n = appleX + 70;\n                appleY_n = appleY + 140;\n            end\n            2'b10: begin\n                appleX_n = appleX + 60;\n                appleY_n = appleY + 40;\n            end\n            2'b11: begin\n                appleX_n = appleX + 80;\n                appleY_n = appleY + 20;\n            end                    \n        endcase\n        if (appleX_n < 11)\n            appleX_n = 11;\n        if (appleX_n > 619)\n            appleX_n = 310;\n        if (appleY_n < 11)\n            appleY_n = 11;\n        if (appleY_n > 459)\n            appleY_n = 250;            \n    end\n\n    always @(posedge clk)\n    begin\n        if(!rst_n) begin\n            snakeX <= {{(MAX_SIZE-1){10'd700}},10'd100};\n            snakeY <= {{(MAX_SIZE-1){10'd700}},10'd100};\n            appleX <= 10'd150;\n            appleY <= 10'd150;\n            size <= 0;\n            prev_y  <= 10'b0;\n            eat_apple <= 1'b0;\n        end\n        else\n        begin\n            prev_y <= y_px;\n            if (prev_y != y_px && (y_px == 0)) begin\n                case(direction)\n                    2'b00: snakeX[9:0] <= snakeX[9:0] - 10;\n                    2'b01: snakeX[9:0] <= snakeX[9:0] + 10;\n                    2'b10: snakeY[9:0] <= snakeY[9:0] - 10;\n                    2'b11: snakeY[9:0] <= snakeY[9:0] + 10;\n                endcase\n                snakeX[MAX_SIZE*10-1:10] <= snakeX[(MAX_SIZE-1)*10-1:0];\n                snakeY[MAX_SIZE*10-1:10] <= snakeY[(MAX_SIZE-1)*10-1:0];\n\n                if(eat_apple) begin\n                    if (size < MAX_SIZE-1)\n                        size <= size + 1;\n                    eat_apple <= 0;\n                    appleX <= appleX_n;\n                    appleY <= appleY_n;\n                end\n\n            end\n            else if((apple && bodySize[0]))\n                eat_apple <= 1'b1;\n\n        end\n    end\n    \nendmodule\n\n", "mask_idx": {"conditional_statement": [[9306, 9546], [4467, 5094], [4616, 5082]], "blocking_assignment": [[7846, 7870], [8049, 8072], [7724, 7748], [7968, 7991], [8259, 8274]], "module_program_interface_instantiation": [[1588, 1821], [1407, 1584]], "always_construct": [[4424, 5103], [6876, 7084], [5373, 5587]], "case_statement": [[8863, 9142], [7627, 8164]], "ansi_port_declaration": [[2592, 2647], [520, 556], [5654, 5691], [186, 234]], "continuous_assign": [[1324, 1349], [6352, 6433], [6480, 6512], [1056, 1093]], "parameter_declaration": [[4233, 4292], [3855, 3921], [3465, 3536], [3623, 3689], [3775, 3850], [4157, 4228], [4081, 4152], [3694, 3770], [4005, 4076]], "nonblocking_assignment": [[9624, 9642], [9159, 9215], [6624, 6643]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1407, 1584], [1588, 1821]], "continuous_assign": [[686, 705], [708, 727], [731, 753], [756, 778], [1056, 1093], [1096, 1133], [1136, 1173], [1176, 1201], [1204, 1241], [1244, 1281], [1284, 1321], [1324, 1349], [1353, 1403], [5168, 5222], [5227, 5281], [5286, 5344], [6318, 6347], [6352, 6433], [6438, 6475], [6480, 6512], [6518, 6553], [7178, 7357], [7391, 7466], [7471, 7585]], "blocking_assignment": [[7684, 7707], [7724, 7748], [7806, 7829], [7846, 7870], [7928, 7951], [7968, 7991], [8049, 8072], [8089, 8112], [8204, 8218], [8259, 8274], [8314, 8328], [8369, 8396]], "nonblocking_assignment": [[4495, 4503], [4516, 4524], [4654, 4667], [4950, 4958], [5012, 5025], [5058, 5066], [5444, 5454], [5467, 5477], [5513, 5533], [5546, 5566], [6624, 6643], [6679, 6698], [6735, 6754], [6788, 6807], [6843, 6862], [6939, 6957], [7058, 7076], [8479, 8523], [8536, 8580], [8593, 8611], [8624, 8642], [8655, 8665], [8678, 8695], [8708, 8726], [8778, 8793], [8906, 8938], [8966, 8998], [9026, 9058], [9086, 9118], [9159, 9215], [9232, 9288], [9393, 9410], [9431, 9446], [9467, 9486], [9507, 9526], [9624, 9642]], "case_statement": [[7627, 8164], [8863, 9142]], "conditional_statement": [[4467, 5094], [4616, 5082], [4975, 5066], [5416, 5578], [6599, 6862], [6657, 6862], [6712, 6862], [6768, 6862], [6821, 6862], [6916, 7076], [6971, 7076], [8173, 8218], [8227, 8274], [8283, 8328], [8337, 8396], [8450, 9655], [8806, 9642], [9306, 9546], [9346, 9410], [9581, 9642]], "always_construct": [[4424, 5103], [5373, 5587], [6563, 6870], [6876, 7084], [7599, 8404], [8410, 9663]], "parameter_declaration": [[3389, 3460], [3465, 3536], [3541, 3618], [3623, 3689], [3694, 3770], [3775, 3850], [3855, 3921], [3926, 4000], [4005, 4076], [4081, 4152], [4157, 4228], [4233, 4292]], "ansi_port_declaration": [[134, 181], [186, 234], [239, 285], [290, 337], [342, 422], [427, 515], [520, 556], [561, 614], [2592, 2647], [2660, 2700], [2713, 2767], [2780, 2832], [2845, 2908], [2921, 2984], [2997, 3025], [5636, 5691], [5641, 5691], [5648, 5691], [5654, 5691], [5660, 5691], [5668, 5691], [5674, 5691], [5681, 5691], [5685, 5691]]}}
{"sample_i": "cpacejo-adia_psu_seq_test", "topmodule": "tt_um_adia_psu_seq_test", "code": "/*\n * Copyright (c) 2024 Applied Invention, LLC\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_adia_psu_seq_test (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  wire [8:0] ctl0;\n  wire [8:0] ctl1;\n  wire r0_w2_en, r1_w3_en, r2_w0_en, r3_w1_en;\n\n  psu_sequencer #(8) seq (clk, rst_n, ctl0, ctl1, r0_w2_en, r1_w3_en, r2_w0_en, r3_w1_en);\n\n  assign uo_out[0] = ui_in[0];\n  assign uo_out[7:1] = ui_in[0] ? ctl1[7:1] : ctl0[7:1];\n  assign uio_out[0] = ctl0[0];\n  assign uio_out[1] = ctl0[8];\n  assign uio_out[2] = ctl1[0];\n  assign uio_out[3] = ctl1[8];\n  assign uio_out[4] = r0_w2_en;\n  assign uio_out[5] = r1_w3_en;\n  assign uio_out[6] = r2_w0_en;\n  assign uio_out[7] = r3_w1_en;\n\n  assign uio_oe = 'hff;\n\n  // List all unused inputs to prevent warnings\n  wire _unused = &{ena, 1'b0};\n\nendmodule\n\n\n/*\n * Copyright (c) 2024 Applied Invention, LLC\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule psu_sequencer #(parameter integer steps = 8) (\n  input wire clk, input wire rst_n,\n  output wire [steps:0] ctl0, output wire [steps:0] ctl1,\n  output wire r0_w2_en, output wire r1_w3_en,\n  output wire r2_w0_en, output wire r3_w1_en\n);\n  reg [3:0] phase;\n  reg [steps-1:0] step;\n\n  always @(posedge clk or negedge rst_n)\n    if (!rst_n) begin\n      phase <= 4'b1000;\n      step <= 1 << (steps-1);\n    end else begin\n      step <= {step[steps-2:0], step[steps-1]};\n      phase <= step[steps-1] ? {phase[2:0], phase[3]} : phase;\n    end\n\n  assign ctl0[0] = (phase[2] & step[steps-1]) | phase[3];\n  assign ctl1[0] = (phase[3] & step[steps-1]) | phase[0];\n\n  generate\n    genvar i;\n    for (i = 1; i < steps; i = i + 1) begin\n      assign ctl0[i] = (phase[0] & step[i-1]) | (phase[2] & step[steps-i-1]);\n      assign ctl1[i] = (phase[1] & step[i-1]) | (phase[3] & step[steps-i-1]);\n    end\n  endgenerate\n\n  assign ctl0[steps] = (phase[0] & step[steps-1]) | phase[1];\n  assign ctl1[steps] = (phase[1] & step[steps-1]) | phase[2];\n\n  assign r0_w2_en = phase[1] & step[steps-1];\n  assign r1_w3_en = phase[2] & step[steps-1];\n  assign r2_w0_en = phase[3] & step[steps-1];\n  assign r3_w1_en = phase[0] & step[steps-1];\n\nendmodule\n", "mask_idx": {"conditional_statement": [[1719, 1928]], "module_program_interface_instantiation": [[725, 813]], "always_construct": [[1676, 1928]], "ansi_port_declaration": [[1480, 1535], [1606, 1626], [152, 199]], "continuous_assign": [[2468, 2511], [905, 933], [848, 902]], "parameter_declaration": [[1411, 1441]], "nonblocking_assignment": [[1816, 1857], [1767, 1790], [1743, 1760]]}, "all_mask_idx": {"module_program_interface_instantiation": [[725, 813]], "continuous_assign": [[817, 845], [848, 902], [905, 933], [936, 964], [967, 995], [998, 1026], [1029, 1058], [1061, 1090], [1093, 1122], [1125, 1154], [1158, 1179], [1932, 1987], [1990, 2045], [2122, 2193], [2200, 2271], [2297, 2356], [2359, 2418], [2422, 2465], [2468, 2511], [2514, 2557], [2560, 2603]], "blocking_assignment": [], "nonblocking_assignment": [[1743, 1760], [1767, 1790], [1816, 1857], [1864, 1920]], "case_statement": [], "conditional_statement": [[1719, 1928]], "always_construct": [[1676, 1928]], "parameter_declaration": [[1411, 1441]], "ansi_port_declaration": [[152, 199], [204, 252], [257, 303], [308, 355], [360, 440], [445, 533], [538, 574], [579, 632], [1444, 1477], [1460, 1477], [1480, 1535], [1508, 1535], [1538, 1581], [1560, 1581], [1584, 1626], [1606, 1626]]}}
{"sample_i": "drburke3-FastMagnitudeComparator", "topmodule": "tt_um_drburke3_top", "code": "/*\n * Copyright (c) 2024 Daniel Burke\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`timescale 1ns / 1ps\n`define default_netname none\n\n// Begin Tiny Tapeout wrapper interface\nmodule tt_um_drburke3_top (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // will go high when the design is enabled\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  // All output pins must be assigned. If not used, assign to 0.\n  /// assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in\n  assign uio_out = 0;\n  assign uio_oe  = 0;\n  assign uo_out [7:3] = 0;\n\n// Instantiate project\n    \nmagnitude_comparator my_mag_comp_8b(\n.A      (ui_in[7:0]),   // input A\n.LT_out    (uo_out[0]),  // A less than B\n.EQ_out    (uo_out[1]),  // A equal to B\n.GT_out    (uo_out[2]),  // A greater than B\n.B      (uio_in[7:0])  // input B\n);\n\nendmodule\n// End Tiny Tapeout wrapper interface\n\n///////////////////////////////////////////////////////////////////////\n// Magnitude Comparator                                              //\n//                                                                   //\n// Designer: Clint Cole (Digilent)                                   //\n// https://www.realdigital.org/doc/a39d855f71772426c968c0151112b476  //\n//                                                                   //\n// This component is bit-sliced expandable, structural code          //\n// re-expressed in the AND-INV format to target optimized ABC9       //\n// AIG graph synthesis in OpenLane.                                  //\n//                                                                   //\n// The element is scaled by repeating the comparator_bitslice module // \n// as needed taking the outputs from the proceeding bit as inputs    // \n// as below.                                                         //\n//                                                                   //\n///////////////////////////////////////////////////////////////////////\nmodule magnitude_comparator(\n    input [7:0] A,\n    input [7:0] B,\n    output LT_out,\n    output EQ_out,\n    output GT_out\n    );\n\nwire [7:0] GT_internal;\nwire [7:0] EQ_internal;\nwire [7:0] LT_internal;\n\ncomparator_bitslice slice_0 (\n    .A(A[0]),\n    .B(B[0]),\n    .LT_in(1'b0),\n    .EQ_in(1'b1),\n    .GT_in(1'b0),\n    .LT_out(LT_internal[0]),\n    .EQ_out(EQ_internal[0]),\n    .GT_out(GT_internal[0])\n    );\n\ncomparator_bitslice slice_1 (\n    .A(A[1]),\n    .B(B[1]),\n    .LT_in(LT_internal[0]),\n    .EQ_in(EQ_internal[0]),\n    .GT_in(GT_internal[0]),\n    .LT_out(LT_internal[1]),\n    .EQ_out(EQ_internal[1]),\n    .GT_out(GT_internal[1])\n    );\n\ncomparator_bitslice slice_2 (\n    .A(A[2]),\n    .B(B[2]),\n    .LT_in(LT_internal[1]),\n    .EQ_in(EQ_internal[1]),\n    .GT_in(GT_internal[1]),\n    .LT_out(LT_internal[2]),\n    .EQ_out(EQ_internal[2]),\n    .GT_out(GT_internal[2])\n    );\n\ncomparator_bitslice slice_3 (\n    .A(A[3]),\n    .B(B[3]),\n    .LT_in(LT_internal[2]),\n    .EQ_in(EQ_internal[2]),\n    .GT_in(GT_internal[2]),\n    .LT_out(LT_internal[3]),\n    .EQ_out(EQ_internal[3]),\n    .GT_out(GT_internal[3])\n    );\n    \n  comparator_bitslice slice_4 (\n    .A(A[4]),\n    .B(B[4]),\n    .LT_in(LT_internal[3]),\n    .EQ_in(EQ_internal[3]),\n    .GT_in(GT_internal[3]),\n    .LT_out(LT_internal[4]),\n    .EQ_out(EQ_internal[4]),\n    .GT_out(GT_internal[4])\n    );\n\ncomparator_bitslice slice_5 (\n    .A(A[5]),\n    .B(B[5]),\n    .LT_in(LT_internal[4]),\n    .EQ_in(EQ_internal[4]),\n    .GT_in(GT_internal[4]),\n    .LT_out(LT_internal[5]),\n    .EQ_out(EQ_internal[5]),\n    .GT_out(GT_internal[5])\n    );\n    \ncomparator_bitslice slice_6 (\n    .A(A[6]),\n    .B(B[6]),\n    .LT_in(LT_internal[5]),\n    .EQ_in(EQ_internal[5]),\n    .GT_in(GT_internal[5]),\n    .LT_out(LT_internal[6]),\n    .EQ_out(EQ_internal[6]),\n    .GT_out(GT_internal[6])\n    );\n\ncomparator_bitslice slice_7 (\n    .A(A[7]),\n    .B(B[7]),\n    .LT_in(LT_internal[6]),\n    .EQ_in(EQ_internal[6]),\n    .GT_in(GT_internal[6]),\n    .LT_out(LT_internal[7]),\n    .EQ_out(EQ_internal[7]),\n    .GT_out(GT_internal[7])\n    );\n    \nassign LT_out = LT_internal[3];\nassign EQ_out = EQ_internal[3];\nassign GT_out = GT_internal[3];\n\nendmodule\n\n\n`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 05/13/2024 11:36:50 AM\n// Design Name: \n// Module Name: comparator_bitslice\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\nmodule comparator_bitslice(\n    input A,\n    input B,\n    input LT_in,\n    input EQ_in,\n    input GT_in,\n    output LT_out,\n    output EQ_out,\n    output GT_out\n    );\n\n// original naive structural Verilog code as per RealDigital\n// assign GT_out =  ( A & ~B ) | (~(A ^ B) & GT_in);\n// re-expressed in AND-INV form for optimal processing in ABC9 AIG graph format\nassign GT_out = ~(~( A & ~B ) & ~(~(~(~A & ~B) & ~(A & B)) & GT_in));\n\n// original naive structural Verilog code as per RealDigital\n// assign EQ_out =  EQ_in & (( A & B ) | (~A & ~B));\n// re-expressed in AND-INV form for optimal processing in ABC9 AIG graph format\nassign EQ_out = EQ_in & ~(~( A & B ) & ~(~A & ~B));\n\n// original naive structural Verilog code as per RealDigital\n// assign LT_out = ( B & ~A ) | ( ~(A ^ B) & LT_in);\n// re-expressed in AND-INV form for optimal processing in ABC9 AIG graph format\nassign LT_out = ~(~( B & ~A ) & ~( ~(( ~(~A & ~B)) & ~(A & B)) & LT_in));\n\nendmodule\n", "mask_idx": {"module_program_interface_instantiation": [[3178, 3412], [2706, 2940], [2500, 2704], [2942, 3176]], "ansi_port_declaration": [[2348, 2362], [361, 408], [5112, 5125], [5023, 5035]], "continuous_assign": [[829, 848], [873, 897], [4404, 4435]]}, "all_mask_idx": {"module_program_interface_instantiation": [[927, 1163], [2500, 2704], [2706, 2940], [2942, 3176], [3178, 3412], [3420, 3654], [3656, 3890], [3896, 4130], [4132, 4366]], "continuous_assign": [[829, 848], [851, 870], [873, 897], [4372, 4403], [4404, 4435], [4436, 4467], [5328, 5397], [5593, 5644], [5840, 5913]], "blocking_assignment": [], "nonblocking_assignment": [], "case_statement": [], "conditional_statement": [], "always_construct": [], "parameter_declaration": [], "ansi_port_declaration": [[205, 252], [257, 305], [310, 356], [361, 408], [413, 493], [498, 568], [573, 609], [614, 667], [2329, 2343], [2348, 2362], [2367, 2381], [2386, 2400], [2405, 2418], [4997, 5005], [5010, 5018], [5023, 5035], [5040, 5052], [5057, 5069], [5074, 5088], [5093, 5107], [5112, 5125]]}}
{"sample_i": "ejfogleman-tt07-ef-smsdac8", "topmodule": "tt_um_ejfogleman_smsdac8", "code": "/*\n * Copyright (c) 2024 Eric Fogleman\n * SPDX-License-Identifier: GPL-2.0-or-later\n *\n * Blocks for fully-segmented mismatch shaping encoder \n * from SEGMENTED MISMATCH-SHAPING D/A CONVERSION, \n * Fishov, Fogleman, Siragusa, Galton \n * 2002 IEEE International Symposium on Circuits and Systems (ISCAS)\n */\n/* verilator lint_off DECLFILENAME */\n\n// retiming reg\nmodule ef_smsdac_reg #(parameter BITS = 8) (\n    input i_clk,\n    input i_rst_b,\n    input [BITS-1:0] i_d,\n    output reg [BITS-1:0] o_q );\n\n\talways @( posedge i_clk, negedge i_rst_b ) \n\t\tif ( i_rst_b == 1'b0 ) \n\t\t\to_q <= 0;\n\t\telse\n\t\t\to_q <= i_d;\n\nendmodule\n\n// the segmenting switching block\nmodule ef_smsdac_mse_seg_sb ( \n\tinput i_clk, \n\tinput i_rst_b, \n\tinput i_r, \n\tinput i_en, \n\tinput i_x, \n\tinput i_xc, \n\toutput wire [1:0] o_y, \n\toutput wire o_yc );\n\n\twire odd = i_x ^ i_xc;\t// input parity\n\twire q;\t\t\t\t// switching sequence\n\n\t// \"carry\" output (lsb weight); round up/down on odd input\n\tassign o_yc = odd ? q : i_x;\n\n\t// 3-level DAC outputs\n\tassign o_y[1] = odd & ~q;\n\tassign o_y[0] = ~odd | ~q;\n\n\t// switching sequence state machine\n\tef_smsdac_mse_sb_sm sb_sm(\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.i_odd(odd),\n\t\t.i_r(i_r),\n\t\t.i_en(i_en),\n\t\t.o_q(q));\n\t\t\t \nendmodule\n\n// the binary switching block\nmodule ef_smsdac_mse_bin_sb ( \n\tinput i_clk,\n\tinput i_rst_b,\n\tinput i_r,\n\tinput i_en,\n\tinput i_x,\n\tinput i_xc,\n\toutput wire [1:0] o_y) ;\n\n\twire q;\t\t\t\t// switching sequence\n\twire odd = i_x ^ i_xc;\t\t// input parity\n\n\t// 3-level DAC output\n\t// if odd, split based on switching sequence\n\tassign o_y[1] = odd ? q : i_xc;\n\tassign o_y[0] = odd ? ~q : i_xc;\n\n\t// switching sequence state machine\n\tef_smsdac_mse_sb_sm sb_sm(\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.i_odd(odd),\n\t\t.i_r(i_r),\n\t\t.i_en(i_en),\n\t\t.o_q(q));\n\nendmodule\n\n// the switching sequence state machine\n// updates only when sb input is odd\n// i_r is a random dither bit\n// i_en == 1'b0 halts state machine and routes i_r to q\nmodule ef_smsdac_mse_sb_sm( \n\tinput i_clk, \n\tinput i_rst_b, \n\tinput i_odd, \n\tinput i_r, \n\tinput i_en, \n\toutput wire o_q );\n\n\t// switching sequence; update only on odd inputs\n\t// en == 1'b0 stops mismatch shaping (static encoder)\n\treg [1:0] q;\n\twire [1:0] q_d;   // next state info\n\tassign q_d[1] = (i_en & i_odd) ? ~q[1]: q[1]; \n\tassign q_d[0] = (i_en & i_odd) ? ( q[1] ? i_r : ~q[0] ) : q[0];\n\n\t// enabled:  highpass shaping\n\t// disabled:  random shaping (whitening)\n\tassign o_q = i_en ? q[0] : i_r;\n\n\talways @( posedge i_clk, negedge i_rst_b ) begin \n\t\tif ( i_rst_b == 1'b0 ) \n\t\t\tq <= 2'b00;\n\t\telse  \n\t\t\tq <= q_d;\n\tend\n\nendmodule\n/* verilator lint_on DECLFILENAME */\n\n\n/*\n * Copyright (c) 2024 Eric Fogleman\n * SPDX-License-Identifier: Apache-2.0\n  *\n * LFSR w/ multiple tapped outputs\n * updates K states at a time to avoid correlation in tapped bits\n * From: A 3.3-V SINGLE-POLY CMOS AUDIO ADC DELTA–SIGMA MODULATOR WITH 98-DB \n * PEAK SINAD AND 105-DB PEAK SFDR, Fogleman et al\n */\n\n/* verilator lint_off DECLFILENAME */\n// n = 20, 1 + x^3 + x^n, K = 8\nmodule ef_lfsr20_8 ( \n\tinput i_clk, \n\tinput i_rst_b, \n\tinput i_en, \n\toutput wire [7:0] o_r );\n\n\treg [19:0] q;\n\tassign o_r[7:0] = q[8:1];  \n\n\talways @( posedge i_clk, negedge i_rst_b ) begin\n\t\tif( ~i_rst_b ) begin\n\t\t\tq[19:1] <= 19'b0;\n\t\t\tq[0] <= 1'b1;\n\t\tend\n\t\telse begin\n\t\t\tif ( i_en ) begin\n\t\t\t\t// jumps 8 states per clock\n\t\t\t\tq[19:12] <= q[7:0] ^ q[10:3];\n\t\t\t\tq[11:0] <= q[19:8];\n\t\t\tend\n\t\tend\n\tend\n\t\nendmodule\n/* verilator lint_on DECLFILENAME */\n\n\n/*\n * Copyright (c) 2024 Eric Fogleman\n * SPDX-License-Identifier: GPL-2.0-or-later\n *\n * 8-b fully-segmented mismatch shaping encoder \n * from SEGMENTED MISMATCH-SHAPING D/A CONVERSION, \n * Fishov, Fogleman, Siragusa, Galton \n * 2002 IEEE International Symposium on Circuits and Systems (ISCAS)\n * y0 drives 1x 3-level DAC\n * y1: 2x, y2: 4x, ..., y6: 64x\n * 128x DAC driven by x7, yc\n * i_en == 1'b0 stops mismatch shaping (static encoder)\n */\n/* verilator lint_off DECLFILENAME */\n\n// 8-b hierarchical encoder\n// seg switching blocks to requantize the input\n// binary switching blocks for each scaled 3-level DAC\nmodule ef_smsdac8_mse ( \n\tinput i_clk,\n\tinput i_rst_b,\n\tinput i_en,\n\tinput [7:0] i_x,\n\tinput i_xc,\n\tinput [7:0] i_r,\n\toutput [13:0] o_y );\t// y64[1:0], y32[1:0], ..., y1[1;0] \n \n\t// 8 layers:  input 7, output 0\n\t// elements numbered top to bottom.  \n\t// signals and instances use layer, element notation:\n\t// u_s70 is 0th switching block in layer 7\n\t// y70 is output of layer 7, element 0\n\n\t// carry outs from segmenting switching blocks\n\twire yc70, yc60, yc50, yc40, yc30, yc20, yc10;\n\n\twire [1:0] y10, y20, y30, y40, y50, y60;  // to binary encoders\n    // verilator lint_off UNUSEDSIGNAL\n\twire [1:0] y70;\t // unused\n    // verilator lint_on UNUSEDSIGNAL\n\n\t// layer 7\n\tef_smsdac_mse_seg_sb u_s70( \n\t\t.i_x(i_x[0]), \n\t\t.i_xc(i_xc), \n\t\t.i_r(i_r[7]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_yc(yc70), \n\t\t.o_y(y70[1:0]) );  // unused\n\n\t// layer 6\n\tef_smsdac_mse_seg_sb u_s60( \n\t\t.i_x(i_x[1]), \n\t\t.i_xc(yc70), \n\t\t.i_r(i_r[6]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_yc(yc60), \n\t\t.o_y(y60[1:0]) );\n\n\tef_smsdac_mse_bin_sb u_s06(\n\t\t.i_x(y60[1]), \n\t\t.i_xc(y60[0]),\n\t\t.i_r(i_r[6]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.o_y(o_y[1:0]) );\t// 1*delta DAC\n\n\t// layer 5\n\tef_smsdac_mse_seg_sb u_s50( \n\t\t.i_x(i_x[2]), \n\t\t.i_xc(yc60), \n\t\t.i_r(i_r[5]),\n\t\t.i_en(i_en), \n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_yc(yc50), \n\t\t.o_y(y50[1:0]) );\n\n\tef_smsdac_mse_bin_sb u_s05(\n\t\t.i_x(y50[1]), \n\t\t.i_xc(y50[0]),\n\t\t.i_r(i_r[5]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.o_y(o_y[3:2]) );\t// 2*delta DAC\n\n\t// layer 4\n\tef_smsdac_mse_seg_sb u_s40( \n\t\t.i_x(i_x[3]), \n\t\t.i_xc(yc50), \n\t\t.i_r(i_r[4]),\n\t\t.i_en(i_en), \n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_yc(yc40), \n\t\t.o_y(y40[1:0]) );\n\n\tef_smsdac_mse_bin_sb u_s04(\n\t\t.i_x(y40[1]), \n\t\t.i_xc(y40[0]),\n\t\t.i_r(i_r[4]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.o_y(o_y[5:4]) );\t// 4*delta DAC\n\n\t// layer 3\n\tef_smsdac_mse_seg_sb u_s30( \n\t\t.i_x(i_x[4]), \n\t\t.i_xc(yc40), \n\t\t.i_r(i_r[3]),\n\t\t.i_en(i_en), \n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_yc(yc30), \n\t\t.o_y(y30[1:0]) );\n\t\t\n\tef_smsdac_mse_bin_sb u_s03(\n\t\t.i_x(y30[1]), \n\t\t.i_xc(y30[0]),\n\t\t.i_r(i_r[3]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.o_y(o_y[7:6]) );\t// 8*delta DAC\n\t\t\n\t// layer 2\n\tef_smsdac_mse_seg_sb u_s20( \n\t\t.i_x(i_x[5]), \n\t\t.i_xc(yc30), \n\t\t.i_r(i_r[2]),\n\t\t.i_en(i_en), \n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_yc(yc20), \n\t\t.o_y(y20[1:0]) );\n\t\t\n\tef_smsdac_mse_bin_sb u_s02(\n\t\t.i_x(y20[1]), \n\t\t.i_xc(y20[0]),\n\t\t.i_r(i_r[2]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.o_y(o_y[9:8]) );\t// 16*delta DAC\n\n\t// layer 1\n\tef_smsdac_mse_seg_sb u_s10( \n\t\t.i_x(i_x[6]), \n\t\t.i_xc(yc20), \n\t\t.i_r(i_r[1]),\n\t\t.i_en(i_en), \n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_yc(yc10), \n\t\t.o_y(y10[1:0]) );\n\t\t\n\tef_smsdac_mse_bin_sb u_s01(\n\t\t.i_x(y10[1]), \n\t\t.i_xc(y10[0]),\n\t\t.i_r(i_r[1]), \n\t\t.i_en(i_en),\n\t\t.i_clk(i_clk),\n\t\t.i_rst_b(i_rst_b),\n\t\t.o_y(o_y[11:10]) );\t// 32*delta DAC\n\t\t\n\t// layer 0\n\t// {i_x[7], yc10};\t\t\n\t// ms-segment from {input msb, final carry out}\n\tef_smsdac_mse_bin_sb u_s00( \n\t\t.i_x(i_x[7]), \n\t\t.i_xc(yc10), \n\t\t.i_r(i_r[0]),\n\t\t.i_en(i_en), \n\t\t.i_clk(i_clk), \n\t\t.i_rst_b(i_rst_b), \n\t\t.o_y(o_y[13:12]) );\t// 64*delta DAC\n\nendmodule\n\n\n// DAC top level \n//\nmodule ef_smsdac8_top( \n    input i_clk, \n    input i_rst_b, \n    input i_en_enc, \n    input i_en_dith, \n    input [7:0] i_x, \n    output wire [13:0] o_y );\t// y64[1:0], y32[1:0], ..., y1[1;0] \n\n    wire [7:0] x_sync1, x_sync2; // input data synchronizer\n    wire [7:0] r;  // random dither bits\n    wire [13:0] y;  // encoder outputs to final reclock\n\n    // input data sync reg\n    ef_smsdac_reg #(.BITS(8)) u_sync1(\n        .i_clk(i_clk), \n        .i_rst_b(i_rst_b), \n        .i_d(i_x), \n        .o_q(x_sync1) );  \n\n    // input data sync reg\n    ef_smsdac_reg #(.BITS(8)) u_sync2(\n        .i_clk(i_clk), \n        .i_rst_b(i_rst_b), \n        .i_d(x_sync1), \n        .o_q(x_sync2) );  \n\n    // mismatch-shaping encoder\n    ef_smsdac8_mse u_dac(\n        .i_clk(i_clk), \n        .i_rst_b(i_rst_b), \n        .i_en(i_en_enc),\n        .i_x(x_sync2), \n        .i_xc(1'b0),  // no carry in\n        .i_r(r), \n        .o_y(y) );\n\n    // LFSR\n    ef_lfsr20_8 u_lfsr(\n        .i_clk(i_clk),\n        .i_rst_b(i_rst_b),\n        .i_en(i_en_dith),\n        .o_r(r) );\n\n    // output retiming reg\n    ef_smsdac_reg #(.BITS(14)) u_reg(\n        .i_clk(i_clk), \n        .i_rst_b(i_rst_b), \n        .i_d(y), \n        .o_q(o_y) );\n\nendmodule\n/* verilator lint_on DECLFILENAME */\n\n\n/*\n * Copyright (c) 2024 Eric Fogleman\n * SPDX-License-Identifier: Apache-2.0\n *\n * TT project wrapper for ef_smsdac\n * 1-10 MHz Segmented mismatch-shaping DAC \n * Input clock at 1-50 MHz \n * 8-b unsigned input data on ui_in[7:0]; sync'd to clk (oversampled)\n * uo_out[7:0] connect to {64x, 32x, 16x, 8x} weight 3-level DACs\n * uio_out[7:3] optionally connect to {4x, 2x, 1x} 3-level DACs \n */\n\n`default_nettype none\n\nmodule tt_um_ejfogleman_smsdac8 (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    // verilator lint_off UNUSEDSIGNAL\n    input  wire [7:0] uio_in,   // IOs: Input path\n    // verilator lint_off UNUSEDSIGNAL\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // will go high when the design is enabled\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n    );\n  \n  // release reset when project enabled\n  wire ena_and_rst_n = ena & rst_n;\n\n  assign uio_oe[7:0] = 8'b11111100;    // uio[7:2] used to bring out extra DAC lsbs\n  assign uio_out[1:0] = 2'h0;    // uio[1:0] used as control inputs\n\n  ef_smsdac8_top u_top( \n    .i_clk(clk), \n    .i_rst_b(ena_and_rst_n), \n    .i_en_enc(uio_in[0]),\n    .i_en_dith(uio_in[1]),\n    .i_x(ui_in[7:0]), \n    .o_y({uo_out[7:0],uio_out[7:2]}) );\n\nendmodule\n", "mask_idx": {"conditional_statement": [[2508, 2568], [550, 608], [3203, 3404]], "module_program_interface_instantiation": [[6175, 6341], [7145, 7316], [8290, 8404], [5467, 5633], [6714, 6883], [6358, 6527]], "always_construct": [[2456, 2573], [3152, 3409], [504, 608]], "ansi_port_declaration": [[4163, 4174], [7460, 7477], [7379, 7392]], "continuous_assign": [[2235, 2281], [9782, 9847], [2422, 2453]], "parameter_declaration": [[385, 406]], "nonblocking_assignment": [[2559, 2568], [3372, 3391], [577, 586]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1103, 1222], [1658, 1777], [4747, 4927], [4942, 5111], [5114, 5280], [5295, 5464], [5467, 5633], [5648, 5817], [5820, 5986], [6001, 6170], [6175, 6341], [6358, 6527], [6532, 6699], [6714, 6883], [6888, 7057], [7145, 7316], [7735, 7868], [7901, 8038], [8076, 8272], [8290, 8404], [8437, 8561], [9851, 10037]], "continuous_assign": [[955, 983], [1010, 1035], [1037, 1063], [1553, 1584], [1586, 1618], [2235, 2281], [2283, 2346], [2422, 2453], [3122, 3149], [9698, 9779], [9782, 9847]], "blocking_assignment": [], "nonblocking_assignment": [[577, 586], [597, 608], [2535, 2546], [2559, 2568], [3227, 3244], [3248, 3261], [3338, 3367], [3372, 3391]], "case_statement": [], "conditional_statement": [[550, 608], [2508, 2568], [3203, 3404], [3284, 3398]], "always_construct": [[504, 608], [2456, 2573], [3152, 3409]], "parameter_declaration": [[385, 406]], "ansi_port_declaration": [[411, 423], [428, 442], [447, 468], [473, 501], [687, 700], [702, 717], [719, 730], [732, 744], [746, 757], [759, 771], [773, 796], [798, 817], [1301, 1313], [1315, 1329], [1331, 1341], [1343, 1354], [1356, 1366], [1368, 1379], [1381, 1405], [1983, 1996], [1998, 2013], [2015, 2028], [2030, 2041], [2043, 2055], [2057, 2075], [3034, 3047], [3049, 3064], [3066, 3078], [3080, 3104], [4102, 4114], [4116, 4130], [4132, 4143], [4145, 4161], [4163, 4174], [4176, 4192], [4194, 4251], [7379, 7392], [7397, 7412], [7417, 7433], [7438, 7455], [7460, 7477], [7482, 7544], [9068, 9115], [9120, 9168], [9212, 9258], [9302, 9349], [9354, 9434], [9439, 9509], [9514, 9550], [9555, 9608]]}}
{"sample_i": "ender110-tt07-clock", "topmodule": "tt_um_ender_clock", "code": " \n\n/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n/* verilator lint_off UNUSEDSIGNAL */\n`default_nettype none\n\t/* verilator lint_off WIDTHTRUNC */\nmodule tt_um_ender_clock (\n\tinput  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n//修改名称\nwire reset;\nwire clock ;\nassign clock=clk;\nassign reset=rst_n;\n//control signel\nwire [2:0]status;\nparameter status_show_time=3'd0;\nparameter status_show_hour=3'd1;\nparameter status_show_minute=3'd2;\nparameter status_show_month=3'd3;\nparameter status_show_day=3'd4;\nreg clock_run_flag;\nreg[15:0]clock_counter;\nalways @(posedge clock or negedge reset)\nbegin\n\tif(!reset)\n\tbegin\n\t\tclock_counter<=16'd0;\n\tend\n\telse\n\tbegin\n\t       clock_counter<=clock_counter+16'd1;\n\tend\nend\n//second clock\nwire second_flag;\nwire [15:0]clock_count;\ntime_control #(16,0) time_control_second_flags(  .clock(clock),  .reset((reset&clock_run_flag)), .add_req(1'd1),.carry_flag(second_flag),.data_out(clock_count),.max(16'd32767) );\n//second\nwire second_carry;\nwire [5:0]seond;\ntime_control #(6,0) time_control_second(  .clock(clock),  .reset((reset&clock_run_flag)), .add_req(second_flag),.carry_flag(second_carry),.data_out(seond),.max(6'd59) );\n//minutes\nwire [5:0]minute;\nwire minute_carry;\n\ttime_control #(6,0) time_control_minute(  .clock(clock),  .reset(reset), .add_req(second_carry||((status==status_show_minute)&&key_add_negedge)),.data_out(minute),.carry_flag(minute_carry),.max(6'd59) );\n//hour\nwire [4:0]hour;\nwire hour_carry;\n\ttime_control #(5,0) time_control_hour(  .clock(clock),  .reset(reset), .add_req(minute_carry||((status==status_show_hour)&&key_add_negedge)),.data_out(hour),.carry_flag(hour_carry),.max(5'd23) );\n//day\nwire [4:0]day;\nwire[4:0]day_this_month;\nwire day_carry;\n\ttime_control #(5,1) time_control_day(  .clock(clock),  .reset(reset), .add_req(hour_carry||((status==status_show_day)&&key_add_negedge)),.data_out(day),.carry_flag(day_carry),.max(day_this_month[4:0]) );\n//month\nwire [3:0]month;\nwire month_carry;\n\ttime_control #(4,1) time_control_month(  .clock(clock),  .reset(reset), .add_req(day_carry||((status==status_show_month)&&key_add_negedge)),.data_out(month),.carry_flag(month_carry),.max(4'd12) );\n//key\nwire key_10ms_flag;\nwire key_add_negedge;\nwire [8:0]counter_10ms;\ntime_control #(9,0) time_control_10ms(  .clock(clock),  .reset(reset), .add_req(1'b1),.data_out(counter_10ms),.carry_flag(key_10ms_flag),.max(9'd327) );\n\nkey key_add(  .clock(clock),  .reset(reset), .time_flag(key_10ms_flag), .key_in(ui_in[1]), .key_out(key_add_negedge) );\nwire key_mode_negedge;\nkey key_mode(  .clock(clock),  .reset(reset), .time_flag(key_10ms_flag), .key_in(ui_in[0]), .key_out(key_mode_negedge) );\n    \n\t//clock_run_flag\n\talways @(posedge clock or negedge reset)\n\tbegin\n\t   if(!reset)\n\t   begin\n\t       clock_run_flag<=1'd1;\n\t   end\n\t   else\n\t   begin\n\t       if((status!=status_show_time)&&(key_add_negedge))\n\t       begin\n\t           clock_run_flag<=1'd0;\n\t       end\n\t       if(status==status_show_time)\n\t       begin\n\t           clock_run_flag<=1'd1;\n\t       end\n\t   end\n\tend\nday_of_month day_of_month_0(.month(month),.day_this_month(day_this_month));\n\t//status\n\twire status_carry;\n\ttime_control #(3,status_show_time) time_control_status(  .clock(clock),  .reset(reset), .add_req(key_mode_negedge),.data_out(status),.max(status_show_day[2:0]),.carry_flag(status_carry));\n\n\n\nwire [3:0]segment_byte_control;\nassign segment_byte_control=status==status_show_time?4'b1111:status==status_show_minute?4'b0011:status==status_show_hour?4'b1100:status==status_show_day?4'b0011:status==status_show_month?4'b1100:0;\nsegment_show segment_show1(.clock(clock),.reset(reset),.data_show(data_show),.segment(uo_out[6:0]),.byte_status(clock_counter[5:3]),.bytee(uio_out[3:0]),.segment_byte_control(segment_byte_control));\nwire[11:0]data_show;\nassign data_show=status==status_show_time?(ui_in[1]==1?{1'd0,hour,minute}:{2'd0,month,1'd0,day[4:0]}):status==status_show_minute?{6'd0,minute}:status==status_show_hour?{1'd0,hour,6'd0}:status==status_show_day?{6'd0,1'd0,day[4:0]}:status==status_show_month?{2'd0,month,6'd0}:0;\nassign uio_out[7:4]=data_show[3:0];\nassign uio_oe[7:0]=8'hff;\nwire segment_D56;\nassign segment_D56=(status==status_show_time)&&clock_counter[13]&&(ui_in[1]==1'd1);\nassign uo_out[7]=segment_D56;\n\t\nendmodule\n/* verilator lint_on UNUSEDSIGNAL */\n\n\n/* verilator lint_off UNUSEDSIGNAL */\nmodule segment_show(input wire clock,input wire reset,input  wire [11:0]data_show,\ninput wire [2:0]byte_status,output wire [3:0]bytee,output wire [6:0]segment,input wire [3:0]segment_byte_control);\n\nwire [5:0]data_showing;\nassign data_showing=byte_status==0?data_show[5:0]:byte_status==2?data_show[5:0]:byte_status==4?data_show[11:6]:byte_status==6?data_show[11:6]:0;\nwire [3:0]segment_show;\nwire [6:0] segment_show_code;\n\t/* verilator lint_off WIDTHTRUNC  */\n\twire [3:0]hundreds;\n\twire [3:0]tens;\n\tassign hundreds= (data_showing / 10) ;\n\tassign tens= (data_showing % 10) ;\n\t\t/* verilator lint_on WIDTHTRUNC  */\n\tassign segment_show = (byte_status == 3'd0) ?tens:\n                      (byte_status == 3'd2) ?hundreds:\n                      (byte_status == 3'd4) ? tens  :\n                      (byte_status == 3'd6) ?hundreds  : 4'd0;\n\n\nsegment_code segment_code_0(.number(segment_show),.code(segment_show_code));\nassign segment=segment_show_code;\nassign bytee=byte_status==0?4'b1110|(~segment_byte_control):byte_status==2?4'b1101|(~segment_byte_control):byte_status==4?4'b1011|(~segment_byte_control):byte_status==6?4'b0111|(~segment_byte_control):4'b1111;\nendmodule\n/* verilator lint_on UNUSEDSIGNAL */\n\n\n\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 2024/05/06 22:47:05\n// Design Name: \n// Module Name: time_control\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule time_control #(parameter BUS_WIDTH = 6,VALUE_INIT   = 0)(\ninput  clock,input  reset,\ninput [BUS_WIDTH-1:0]max,\ninput add_req,output reg carry_flag,\noutput reg [BUS_WIDTH-1:0]data_out\n    );\n\n        \n reg [BUS_WIDTH-1:0]data_old;\n    \talways @(posedge clock or negedge reset)\n\tbegin\n\t\tif(!reset)\n\t\tbegin\n\t\t\tdata_out<=VALUE_INIT;\n\t\t\tcarry_flag<=1'd0;\n\t\tend\n\t\telse\n\t\tbegin\n\n\t\t\t\t\t\tdata_old<=data_out;\n\t\t\tif(add_req)\n\t\t\tbegin\n\t\t\t\t//data<=data+{{BUS_WIDTH-1{1'b0}},{1'd0}};\n\t\t          data_out<=data_out+1;\n\n\t\t\t\tif(data_out==max)\n\t\t\t\tbegin \n\t\t\t\t\tdata_out<=VALUE_INIT;\n\t\t\t\tend\n\t\t\tend\n\t\t\t\tif((data_old==max)&&(data_out==VALUE_INIT))\n\t\t\t     begin\n\t\t\t         carry_flag<=1'd1;\n\t\t\t     end\n\t\t\t     else\n\t\t\t     begin\n\t\t\t         carry_flag<=1'd0;\n\t\t\t     end\n\t\t  end\n\tend\nendmodule\n\n\n\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 2024/05/07 19:49:56\n// Design Name: \n// Module Name: segment_code\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule segment_code(\ninput wire  [3:0]number,output wire [6:0]code\n    );\n    assign code=number==0?7'h3f:number==1?7'h06:number==2?7'h5b:number==3?7'h4f:number==4?7'h66:number==5?7'h6d:number==6?7'h7d:number==7?7'h07:number==8?7'h7f:number==9?7'h6f:7'h0;\nendmodule\n\n\n\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 2024/05/07 21:01:04\n// Design Name: \n// Module Name: day_of_month\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\n\nmodule day_of_month(\ninput wire [3:0]month,\noutput wire[4:0] day_this_month\n    );\nassign day_this_month=month==1?5'd31:month==2?5'd28:month==3?5'd31:month==4?5'd30:month==5?5'd31:month==6?5'd30:month==7?5'd31:month==8?5'd31:month==9?5'd30:month==10?5'd31:month==11?5'd30:5'd31;\nendmodule\n\n\n\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// Engineer: \n// \n// Create Date: 2024/05/06 22:27:13\n// Design Name: \n// Module Name: key\n// Project Name: \n// Target Devices: \n// Tool Versions: \n// Description: \n// \n// Dependencies: \n// \n// Revision:\n// Revision 0.01 - File Created\n// Additional Comments:\n// \n//////////////////////////////////////////////////////////////////////////////////\n\nmodule key(\ninput  clock,input  reset,input time_flag,\ninput key_in,output key_out\n    );\n    \n\treg [3:0]key_filter;\n\talways @(posedge clock or negedge reset)\n\tbegin\n\t   if(reset==1'd0)\n\t   begin\n\t       key_filter<=4'b1111;\n\t   end\n\t   else\n\t   begin\n\t       if(time_flag==1)\n\t       begin\n\t           key_filter<={key_filter[2:0],key_in};\n\t       end\n\t   end\n\tend\n\tassign key_out=(time_flag==1)&&(key_filter==4'b1100);\nendmodule\n", "mask_idx": {"conditional_statement": [[6752, 7226], [1055, 1163], [3269, 3378], [6975, 7038]], "module_program_interface_instantiation": [[2842, 2961], [5635, 5711], [1912, 2107]], "always_construct": [[6702, 7231], [1007, 1167], [9276, 9523]], "ansi_port_declaration": [[633, 686], [6538, 6551], [4908, 4994]], "continuous_assign": [[5712, 5745], [5410, 5632], [9525, 9578], [5336, 5370]], "parameter_declaration": [[829, 861], [931, 962], [862, 896], [897, 930], [796, 828], [6482, 6524]], "nonblocking_assignment": [[7120, 7137], [6845, 6864], [7009, 7030]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1225, 1403], [1449, 1618], [1667, 1870], [1912, 2107], [2171, 2374], [2419, 2615], [2688, 2840], [2842, 2961], [2985, 3106], [3489, 3564], [3596, 3783], [4017, 4215], [5635, 5711]], "continuous_assign": [[723, 740], [741, 760], [3819, 4016], [4237, 4513], [4514, 4549], [4550, 4575], [4594, 4677], [4678, 4707], [5020, 5164], [5296, 5334], [5336, 5370], [5410, 5632], [5712, 5745], [5746, 5955], [7777, 7954], [8505, 8700], [9525, 9578]], "blocking_assignment": [], "nonblocking_assignment": [[1075, 1096], [1123, 1158], [3212, 3233], [3345, 3366], [3442, 3463], [6774, 6795], [6799, 6816], [6845, 6864], [6948, 6969], [7009, 7030], [7120, 7137], [7189, 7206], [9362, 9382], [9461, 9498]], "case_statement": [], "conditional_statement": [[1055, 1163], [3183, 3483], [3269, 3378], [3387, 3475], [6752, 7226], [6868, 7045], [6975, 7038], [7050, 7218], [9328, 9518], [9418, 9510]], "always_construct": [[1007, 1167], [3131, 3488], [6702, 7231], [9276, 9523]], "parameter_declaration": [[796, 828], [829, 861], [862, 896], [897, 930], [931, 962], [6482, 6524]], "ansi_port_declaration": [[206, 253], [258, 306], [311, 357], [362, 409], [414, 494], [499, 587], [592, 628], [633, 686], [4817, 4879], [4834, 4879], [4851, 4879], [4880, 4994], [4908, 4994], [4931, 4994], [4956, 4994], [6525, 6551], [6538, 6551], [6552, 6577], [6578, 6614], [6592, 6614], [6615, 6649], [7720, 7765], [7744, 7765], [8443, 8465], [8466, 8497], [9170, 9212], [9183, 9212], [9196, 9212], [9213, 9240], [9226, 9240]]}}
{"sample_i": "jasonkaufmann-tt07-fulladder8bit", "topmodule": "tt_um_8bitadder", "code": "/*\n * Copyright (c) 2024 Jason Kaufmann\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_8bitadder (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  // Instantiate the rca8 module\n  wire [7:0] sum;\n  wire cout;\n\n  rca8 adder (\n      .A(ui_in),\n      .B(uio_in),\n      .cin(1'b0),    // Assuming no carry-in for simplicity\n      .SUM(sum),\n      .cout(cout)\n  );\n\n  // Assign the sum to the output\n  assign uo_out = sum;\n\n  // All other output pins must be assigned. If not used, assign to 0.\n  assign uio_out = 0;\n  assign uio_oe  = 0;\n\n  // List all unused inputs to prevent warnings\n  wire _unused = &{ena, clk, rst_n, 1'b0};\n\nendmodule\n\nmodule halfadder(input wire a,\n                 input wire b,\n                 output wire s,\n                 output wire cout);\n    assign s = a ^ b;\n    assign cout = a & b;\nendmodule\n\nmodule fulladder(input wire cin,\n                 input wire a,\n                 input wire b,\n                 output wire s,\n                 output wire cout);\n    wire s_tmp, cout_tmp1, cout_tmp2; \n    halfadder h0(.a(a), .b(b), .s(s_tmp), .cout(cout_tmp1));\n    halfadder h1(.a(s_tmp), .b(cin), .s(s), .cout(cout_tmp2));\n    assign cout = cout_tmp1 | cout_tmp2; \nendmodule\n\nmodule rca8(input wire [7:0] A,\n            input wire [7:0] B,\n            input wire       cin,\n            output wire [7:0] SUM,\n            output wire      cout);\n    wire [7:0] carry;\n    \n    fulladder fa0 (.cin(cin),     .a(A[0]), .b(B[0]), .s(SUM[0]), .cout(carry[0]));\n    fulladder fa1 (.cin(carry[0]), .a(A[1]), .b(B[1]), .s(SUM[1]), .cout(carry[1]));\n    fulladder fa2 (.cin(carry[1]), .a(A[2]), .b(B[2]), .s(SUM[2]), .cout(carry[2]));\n    fulladder fa3 (.cin(carry[2]), .a(A[3]), .b(B[3]), .s(SUM[3]), .cout(carry[3]));\n    fulladder fa4 (.cin(carry[3]), .a(A[4]), .b(B[4]), .s(SUM[4]), .cout(carry[4]));\n    fulladder fa5 (.cin(carry[4]), .a(A[5]), .b(B[5]), .s(SUM[5]), .cout(carry[5]));\n    fulladder fa6 (.cin(carry[5]), .a(A[6]), .b(B[6]), .s(SUM[6]), .cout(carry[6]));\n    fulladder fa7 (.cin(carry[6]), .a(A[7]), .b(B[7]), .s(SUM[7]), .cout(carry[7]));\n\n    assign cout = carry[7];\nendmodule\n", "mask_idx": {"module_program_interface_instantiation": [[1508, 1564], [2475, 2555], [2390, 2470]], "ansi_port_declaration": [[241, 287], [1414, 1428], [429, 517]], "continuous_assign": [[1248, 1265], [873, 893], [1632, 1669]]}, "all_mask_idx": {"module_program_interface_instantiation": [[688, 835], [1508, 1564], [1569, 1627], [1881, 1960], [1965, 2045], [2050, 2130], [2135, 2215], [2220, 2300], [2305, 2385], [2390, 2470], [2475, 2555]], "continuous_assign": [[873, 893], [968, 987], [990, 1009], [1248, 1265], [1270, 1290], [1632, 1669], [2561, 2584]], "blocking_assignment": [], "nonblocking_assignment": [], "case_statement": [], "conditional_statement": [], "always_construct": [], "parameter_declaration": [], "ansi_port_declaration": [[136, 183], [188, 236], [241, 287], [292, 339], [344, 424], [429, 517], [522, 558], [563, 616], [1131, 1144], [1162, 1175], [1193, 1207], [1225, 1243], [1319, 1334], [1352, 1365], [1383, 1396], [1414, 1428], [1446, 1464], [1693, 1712], [1725, 1744], [1757, 1778], [1791, 1813], [1826, 1849]]}}
{"sample_i": "jleightcap-tt07", "topmodule": "tt_um_jleightcap", "code": "/*\n * Copyright (c) 2024 Jack Leightcap\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_jleightcap (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  wire we, halt;\n  wire [5:0] count;\n  Fractran ft (\n      .clk(clk),\n      .rst(rst_n),\n      .en(ena),\n      .accumulator(uio_in),\n      .fraction(ui_in),\n      .we(we),\n      .degree(uo_out),\n      .halt(halt),\n      .count(count)\n  );\n  assign uio_out = {we, halt, count};\n  assign uio_oe = {we, we, we, we, we, we, we, we};\n\nendmodule\n\n\n/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE.\n** GENERATED BY CLASH 1.6.3. DO NOT MODIFY.\n*/\nmodule Fractran\n    ( // Inputs\n      input [7:0] accumulator\n    , input [7:0] fraction\n    , input  clk // clock\n    , input  rst // reset\n    , input  en // enable\n\n      // Outputs\n    , output wire [7:0] degree\n    , output wire  we\n    , output wire  halt\n    , output wire [5:0] count\n    );\n  // src/Fractran.hs:148:1-9\n  wire [17:0] \\input ;\n  // src/Fractran.hs:120:1-88\n  reg [16:0] s1 = {1'd0,   {1'b1,{1'b1,8'b00000000}},   6'b000000};\n  wire [7:0] c$case_alt_0;\n  wire [7:0] c$app_arg;\n  wire  c$app_arg_0;\n  wire [0:0] c$app_arg_1;\n  // src/Fractran.hs:37:3-6\n  wire [7:0] a;\n  // src/Fractran.hs:107:1-6\n  wire [8:0] v;\n  wire [16:0] result;\n  wire [9:0] result_0;\n  wire [9:0] c$case_alt_1;\n  wire [9:0] c$case_alt_2;\n  wire [9:0] c$case_alt_3;\n  wire [9:0] c$case_alt_4;\n  // src/Fractran.hs:56:7-8\n  wire [7:0] ipv;\n  wire [7:0] c$app_arg_2;\n  wire [9:0] c$case_alt_5;\n  wire  c$case_scrut;\n  // src/Fractran.hs:56:7-8\n  wire [7:0] f;\n  // src/Fractran.hs:81:1-6\n  wire [8:0] f_0;\n  // src/Fractran.hs:81:1-6\n  wire [8:0] a_0;\n  // src/Fractran.hs:148:1-9\n  reg [8:0] c$input_app_arg;\n  // src/Fractran.hs:148:1-9\n  reg [8:0] c$input_app_arg_0;\n  wire [9:0] c$app_arg_selection_1;\n  wire [9:0] c$app_arg_selection_6;\n  wire [7:0] c$bv;\n  wire [15:0] c$case_alt;\n\n  assign \\input  = {c$input_app_arg_0,\n                    c$input_app_arg};\n\n  // register begin\n  always @(posedge clk or  posedge  rst) begin : s1_register\n    if ( rst) begin\n      s1 <= {1'd0,   {1'b1,{1'b1,8'b00000000}},   6'b000000};\n    end else if (en) begin\n      s1 <= result;\n    end\n  end\n  // register end\n\n  assign c$case_alt_0 = v[8:8] ? (a) : 8'b11111111;\n\n  assign c$app_arg_selection_1 = s1[15:6];\n\n  assign c$app_arg = c$app_arg_selection_1[9:9] ? c$case_alt_0 : (8'b00000000);\n\n  assign c$app_arg_0 = s1[16:16] ? (1'b1) : (1'b0);\n\n  assign c$app_arg_selection_6 = s1[15:6];\n\n  assign c$app_arg_1 = c$app_arg_selection_6[9:9] ? 1'b0 : 1'b1;\n\n  assign c$case_alt = {c$app_arg,   c$app_arg_0,\n                       (c$app_arg_1),   s1[5:0]};\n\n  assign a = v[7:0];\n\n  assign v = s1[14:6];\n\n  assign result = s1[16:16] ? {1'd0,   result_0,\n                               s1[5:0]} : {1'd1,   result_0,\n                                           s1[5:0] + 6'b000001};\n\n  assign result_0 = a_0[8:8] ? c$case_alt_1 : c$case_alt_2;\n\n  assign c$case_alt_1 = f_0[8:8] ? c$case_alt_3 : {1'b1,a_0};\n\n  assign c$case_alt_2 = f_0[8:8] ? c$case_alt_5 : {1'b1,{1'b0,8'bxxxxxxxx}};\n\n  assign c$case_alt_3 = c$case_scrut ? {1'b1,{1'b1,(ipv + f) % 8'b01111110}} : c$case_alt_4;\n\n  assign c$case_alt_4 = (ipv >= c$app_arg_2) ? {1'b1,{1'b1,(ipv - c$app_arg_2) + 8'b00000001}} : {1'b0,9'bxxxxxxxxx};\n\n  assign ipv = a_0[7:0];\n\n  assign c$app_arg_2 = -f;\n\n  assign c$case_alt_5 = c$case_scrut ? {1'b1,{1'b1,f}} : {1'b0,9'bxxxxxxxxx};\n\n  assign c$bv = (f);\n\n  assign c$case_scrut = ( c$bv[8-1] ) == (1'b0);\n\n  assign f = f_0[7:0];\n\n  assign f_0 = \\input [8:0];\n\n  assign a_0 = \\input [17:9];\n\n  always @(*) begin\n    case(fraction)\n      8'b11111111 : c$input_app_arg = {1'b0,8'bxxxxxxxx};\n      default : c$input_app_arg = {1'b1,fraction};\n    endcase\n  end\n\n  always @(*) begin\n    case(accumulator)\n      8'b11111111 : c$input_app_arg_0 = {1'b0,8'bxxxxxxxx};\n      default : c$input_app_arg_0 = {1'b1,accumulator};\n    endcase\n  end\n\n  assign degree = c$case_alt[15:8];\n\n  assign we = c$case_alt[7:7];\n\n  assign halt = c$case_alt[6:6];\n\n  assign count = c$case_alt[5:0];\n\n\nendmodule\n\n", "mask_idx": {"conditional_statement": [[2509, 2641], [2600, 2641]], "blocking_assignment": [[4320, 4359], [4264, 4303], [4094, 4131], [4148, 4182]], "module_program_interface_instantiation": [[661, 860]], "always_construct": [[4204, 4377], [4037, 4200], [2446, 2647]], "case_statement": [[4226, 4371], [4059, 4194]], "ansi_port_declaration": [[1102, 1125], [1255, 1279], [1132, 1152], [1332, 1355]], "continuous_assign": [[2900, 2940], [3773, 3797], [3534, 3624]], "nonblocking_assignment": [[2531, 2586], [2620, 2633]]}, "all_mask_idx": {"module_program_interface_instantiation": [[661, 860]], "continuous_assign": [[863, 898], [901, 950], [2348, 2422], [2669, 2718], [2722, 2762], [2766, 2843], [2847, 2896], [2900, 2940], [2944, 3006], [3010, 3106], [3110, 3128], [3132, 3152], [3156, 3328], [3332, 3389], [3393, 3452], [3456, 3530], [3534, 3624], [3628, 3743], [3747, 3769], [3773, 3797], [3801, 3876], [3880, 3898], [3902, 3948], [3952, 3972], [3976, 4002], [4006, 4033], [4381, 4414], [4418, 4446], [4450, 4480], [4484, 4515]], "blocking_assignment": [[4094, 4131], [4148, 4182], [4264, 4303], [4320, 4359]], "nonblocking_assignment": [[2531, 2586], [2620, 2633]], "case_statement": [[4059, 4194], [4226, 4371]], "conditional_statement": [[2509, 2641], [2600, 2641]], "always_construct": [[2446, 2647], [4037, 4200], [4204, 4377]], "parameter_declaration": [], "ansi_port_declaration": [[137, 184], [189, 237], [242, 288], [293, 340], [345, 425], [430, 518], [523, 559], [564, 617], [1102, 1125], [1132, 1152], [1159, 1178], [1185, 1204], [1211, 1230], [1255, 1279], [1286, 1301], [1308, 1325], [1332, 1355]]}}
{"sample_i": "leeja-j-router_tinytapeout", "topmodule": "tt_um_router", "code": "/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_router (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\nassign uio_oe=8'b11111111;\n\nassign uio_out[7:6]=2'b00;\n\nrouter_top router_top (\n\t\t.clock(clk),\n\t\t.resetn(rst_n),\n\t\t.data_in(ui_in[2:0]),\n\t\t.pkt_valid(ui_in[3]),\n\t\t.read_enb_0(ui_in[4]),\n\t\t.read_enb_1(ui_in[5]),\n\t\t.read_enb_2(ui_in[6]),\n\t\t.data_out_0(uo_out[2:0]),\n\t\t.data_out_1(uo_out[5:3]),\n\t\t.data_out_2(uio_out[2:0]),\n\t\t.vld_out_0(uio_out[3]),\n\t\t.vld_out_1(uio_out[4]),\n\t\t.vld_out_2(uio_out[5]),\n\t\t.err(uo_out[6]),\n\t\t.busy(uo_out[7])\n\t\t);\n\n\nendmodule\n\n\n\n\n\nmodule router_fifo(clock,resetn,soft_reset,write_enb,read_enb,\n                   lfd_state,data_in,full,empty,data_out);\n  \n  input clock,resetn,soft_reset;\n  input write_enb,read_enb,lfd_state;\n  input [2:0]data_in;\n  \n  output reg [2:0] data_out;\n  output full,empty;\n  \n  reg [4:0] rd_pointer,wr_pointer;\n  reg [6:0] count;\n  reg [8:0] mem [15:0];\n\n  integer i;\n  \n   reg lfd_state_t;\n  \n  always@(posedge clock)\n    begin\n      if(!resetn)\n        lfd_state_t <= 0;\n      else\n        lfd_state_t <= lfd_state;\n    end \n   \n  // ------Read Operation-------\n  always@(posedge clock) \n    begin\n      if(!resetn)\n          data_out = 3'b0;\n      else if(soft_reset) \n          data_out = 3'bz;\n      else if((read_enb) && (!empty))\n        data_out = mem[rd_pointer[2:0]][2:0];\n      else if(count == 0)\n           data_out = 3'bz;\n    end\n  \n  // ------Write Operation------ \n  always@(posedge clock) \n    begin\n      if(!resetn || soft_reset)\n         begin\n            for(i=0;i<16;i=i+1)\n            mem[i]<=0;\n         end\n      else if(write_enb&&(~full))   \n         begin\n           if(lfd_state_t)\n\t           begin\n                 mem[wr_pointer[3:0]][8]<=1'b1;\n                 mem[wr_pointer[2:0]][2:0]<=data_in;\n\t           end\n      \n\t      else\n\t           begin\n                 mem[wr_pointer[3:0]][8]<=1'b0;\n                 mem[wr_pointer[2:0]][2:0]<=data_in;\n\t\t\t   end\n         end\n     end\n\n      \n    \n  \n  //----Pointer generation block----\n\n   always@(posedge clock) \n     begin\n       if(!resetn)\n        wr_pointer<=0;\n      else if(write_enb && (~full))\n        wr_pointer<=wr_pointer+1;\n     end\n   \n   always@(posedge clock) //Read address\n     begin\n       if(!resetn)\n         rd_pointer<=0;\n       else if(read_enb && (~empty))\n         rd_pointer<=rd_pointer+1;\n     end\n  \n  \n  //-----counter block while reading------\n  \n  always@(posedge clock)\n    begin\n      if(read_enb && !empty)\n        begin\n          if((mem[rd_pointer[3:0]][8])==1'b1)\n            count <= mem[rd_pointer[3:0]][7:2] + 1'b1;\n          else if(count != 0)\n            count <= count - 1'b1;\n        end\n    end\n  //---------Full & empty condition-----------\n  assign full  = (wr_pointer ==({~rd_pointer[4],rd_pointer[3:0]}));\n  assign empty = (rd_pointer == wr_pointer);\n  \n  \nendmodule\n\n\n\n\nmodule router_fsm(clock,resetn,pkt_valid,data_in,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2,\n                  soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_packet_valid,\n                  write_enb_reg,detect_add,ld_state,laf_state,lfd_state,full_state,rst_int_reg,busy);\n\ninput clock,resetn,pkt_valid,fifo_full,fifo_empty_0,fifo_empty_1,fifo_empty_2;\ninput soft_reset_0,soft_reset_1,soft_reset_2,parity_done,low_packet_valid;\ninput [1:0] data_in;\noutput write_enb_reg,detect_add,ld_state,laf_state,lfd_state,full_state,rst_int_reg,busy;\n  \n  \nparameter DECODE_ADDRESS     = 3'b000,\n          LOAD_FIRST_DATA \t = 3'b001,\n          LOAD_DATA \t\t = 3'b010,\n          WAIT_TILL_EMPTY \t = 3'b011,\n          CHECK_PARITY_ERROR = 3'b100,\n          LOAD_PARITY \t\t = 3'b101,\n          FIFO_FULL_STATE \t = 3'b110,\n          LOAD_AFTER_FULL \t = 3'b111;\n  \n  reg [2:0] PS,NS;\n          \n  always@(posedge clock)\n    begin\n      if(!resetn)\n        PS <= DECODE_ADDRESS;\n      else if(soft_reset_0 || soft_reset_1 || soft_reset_2)\n        PS <= DECODE_ADDRESS;\n      else \n        PS <= NS;\n    end\n  \n  \n  always@(*)\n    begin\n      NS = DECODE_ADDRESS;\n      case(PS)\n        \n        DECODE_ADDRESS : \n                  begin\n                    if((pkt_valid && (data_in[1:0]==0) && fifo_empty_0)||\n                       (pkt_valid && (data_in[1:0]==1) && fifo_empty_1)||\n                       (pkt_valid && (data_in[1:0]==2) && fifo_empty_2))\n                      \n                      NS = LOAD_FIRST_DATA;\n                    \n                    else if((pkt_valid && (data_in[1:0]==0) && (~fifo_empty_0))||\n                            (pkt_valid && (data_in[1:0]==1) && (~fifo_empty_1))||\n                            (pkt_valid && (data_in[1:0]==2) && (~fifo_empty_2)))\n                      \n                      NS = WAIT_TILL_EMPTY;\n                    \n                    else\n                      NS = DECODE_ADDRESS;\n                  end\n        \n        LOAD_FIRST_DATA :  NS = LOAD_DATA;\n        \n        LOAD_DATA       : \n                        begin\n\t\t\t      \t\t\tif(fifo_full)\n\t\t\t\t \t\t\t\tNS=FIFO_FULL_STATE;\n                          else if(!fifo_full && !pkt_valid)\n\t\t\t\t \t\t\t\tNS=LOAD_PARITY;\n\t\t\t      \t\t\telse\n\t\t\t\t \t\t\t\tNS=LOAD_DATA;\n\t\t\t   \t\t\tend \n        \n        WAIT_TILL_EMPTY  : \n                        begin\n                          if((!fifo_empty_0) || (!fifo_empty_1) || (!fifo_empty_2))\n\t\t\t\t \t\t\tNS=WAIT_TILL_EMPTY;\n\t\t\t      \t\t  else if(fifo_empty_0||fifo_empty_1||fifo_empty_2)\n\t\t\t\t \t\t\tNS=LOAD_FIRST_DATA;\n\t\t\t      \t\t  else\n\t\t\t\t \t\t\tNS=WAIT_TILL_EMPTY;\n                         end\n        \n        CHECK_PARITY_ERROR:\n          \t\t\t\tbegin\n\t\t\t    \t\t\tif(fifo_full)\n\t\t\t      \t \t\t\tNS=FIFO_FULL_STATE;\n\t\t\t    \t\t\telse\n\t\t\t         \t\t\tNS=DECODE_ADDRESS;\n\n\t\t\t   \t\t\t end\n\n       LOAD_PARITY     \t  :\tNS=CHECK_PARITY_ERROR;\n\t\t\t \n\n       FIFO_FULL_STATE\t  :\t   \n          \t\t\t\tbegin\n                        \tif(!fifo_full)\n\t\t\t         \t\t\tNS=LOAD_AFTER_FULL;\n\t\t\t      \t\t\telse if(fifo_full)\n\t\t\t         \t\t\tNS=FIFO_FULL_STATE;\n\t\t\t  \t\t \t\tend\n        \n        LOAD_AFTER_FULL:\t   \n          \t\t\t\tbegin\n          \t\t\t\t\tif((!parity_done) && (!low_packet_valid))\n\t\t\t   \t\t\t\t\tNS=LOAD_DATA;\n          \t\t\t\t\telse if((!parity_done) && (low_packet_valid))\n\t\t\t   \t\t\t\t\tNS=LOAD_PARITY;\n          \t\t\t\t\telse if(parity_done)\n\t\t\t   \t\t\t\t\tNS=DECODE_ADDRESS;\n\t\t\t   \t\t\t end\n        \n      endcase\n   end\n  \n  assign detect_add = ((PS==DECODE_ADDRESS)?1:0); \n  assign write_enb_reg=((PS==LOAD_DATA||PS==LOAD_PARITY||PS==LOAD_AFTER_FULL)?1:0);\n  assign full_state=((PS==FIFO_FULL_STATE)?1:0);\n  assign lfd_state=((PS==LOAD_FIRST_DATA)?1:0);\n  assign busy=((PS==FIFO_FULL_STATE||PS==LOAD_AFTER_FULL||PS==WAIT_TILL_EMPTY||PS==LOAD_FIRST_DATA||PS==LOAD_PARITY||PS==CHECK_PARITY_ERROR)?1:0);\n  //assign busy=((PS==LOAD_DATA || PS==DECODE_ADDRESS)?0:1);\n  assign ld_state=((PS==LOAD_DATA)?1:0);\n  assign laf_state=((PS==LOAD_AFTER_FULL)?1:0);\n  assign rst_int_reg=((PS==CHECK_PARITY_ERROR)?1:0);\n  \nendmodule\n  \n\n\n\n\nmodule router_reg(clock,resetn,pkt_valid,data_in,fifo_full,detect_add,\n                  ld_state,laf_state,full_state,lfd_state,rst_int_reg,err,\n                  parity_done,low_packet_valid,dout);\n\ninput clock,resetn,pkt_valid,fifo_full,detect_add,ld_state,laf_state,full_state,lfd_state,rst_int_reg;\ninput [2:0]data_in;\noutput reg err,parity_done,low_packet_valid;\noutput reg [2:0]dout;\nreg [2:0]header,int_reg,int_parity,ext_parity;\n  \n  \n  //------------------------------DATA OUT LOGIC---------------------------------\n\n\talways@(posedge clock)\n   \tbegin\n      if(!resetn)\n      \tbegin\n\t     dout    \t <=0;\n\t     header  \t <=0;\n\t     int_reg \t <=0;\n       \tend\n      else if(detect_add && pkt_valid && data_in[1:0]!=2'b11)\n\t     header<=data_in;\n      else if(lfd_state)\n\t     dout<=header;\n      else if(ld_state && !fifo_full)\n\t     dout<=data_in;\n      else if(ld_state && fifo_full)\n\t     int_reg<=data_in;\n      else if(laf_state)\n\t     dout<=int_reg;\n     end\n\n  //---------------------------LOW PACKET VALID LOGIC----------------------------\n\t\n      \talways@(posedge clock)\n\t   \t\tbegin\n              if(!resetn)\n\t \t\t\t\tlow_packet_valid<=0; \n         \t\telse if(rst_int_reg)\n\t \t\t\t\tlow_packet_valid<=0;\n\n              else if(ld_state && !pkt_valid) \n         \t\t\tlow_packet_valid<=1;\n\t\t\tend\n  //----------------------------PARITY DONE LOGIC--------------------------------\n\t\n\talways@(posedge clock)\n\tbegin\n      if(!resetn)\n\t  parity_done<=0;\n     else if(detect_add)\n\t  parity_done<=0;\n      else if((ld_state && !fifo_full && !pkt_valid)\n              ||(laf_state && low_packet_valid && !parity_done))\n\t  parity_done<=1;\n\tend\n\n//---------------------------PARITY CALCULATE LOGIC----------------------------\n\n\talways@(posedge clock)\n\tbegin\n      if(!resetn)\n\t int_parity<=0;\n\telse if(detect_add)\n\t int_parity<=0;\n\telse if(lfd_state && pkt_valid)\n\t int_parity<=int_parity^header;\n\telse if(ld_state && pkt_valid && !full_state)\n\t int_parity<=int_parity^data_in;\n\telse\n\t int_parity<=int_parity;\n\tend\n\t \n\n//-------------------------------ERROR LOGIC-----------------------------------\n\n\talways@(posedge clock)\n\t\tbegin\n          if(!resetn)\n\t  \t\t\terr<=0;\n\t      else if(parity_done)\n\t       \t\tbegin\n\t \t\t\t\tif (int_parity==ext_parity)\n\t    \t\t\t\terr<=0;\n\t \t\t\t\telse \n\t    \t\t\terr<=1;\n\t \t\t\tend\n\t \t   else\n\t    \t\terr<=0;\n\t      end\n\n//-------------------------------EXTERNAL PARITY LOGIC-------------------------\n\n\talways@(posedge clock)\n\tbegin\n      if(!resetn)\n\t  \t\text_parity<=0;\n      else if(detect_add)\n\t  \t\text_parity<=0;\n      else if((ld_state && !fifo_full && !pkt_valid) || (laf_state && !parity_done && low_packet_valid))\n\t  \t\text_parity<=data_in;\n\t end\n\nendmodule\n\n\n\nmodule router_sync(clock,resetn,data_in,detect_add,full_0,full_1,full_2,empty_0,empty_1,empty_2,write_enb_reg,read_enb_0,read_enb_1,read_enb_2,write_enb,fifo_full,vld_out_0,vld_out_1,vld_out_2,soft_reset_0,soft_reset_1,soft_reset_2);\n\n\ninput clock,resetn,detect_add,full_0,full_1,full_2,empty_0,empty_1,empty_2,write_enb_reg,read_enb_0,read_enb_1,read_enb_2;\ninput [1:0]data_in;\noutput reg[2:0]write_enb;\noutput reg fifo_full,soft_reset_0,soft_reset_1,soft_reset_2;\noutput vld_out_0,vld_out_1,vld_out_2;\n\n  reg [1:0] data_in_tmp;\n  reg[4:0]count0,count1,count2;\n  \n  always@(posedge clock)\n  begin\n    if(~resetn)\n    data_in_tmp<=0;\n    else if(detect_add)\n    data_in_tmp<=data_in;\n  end\n  \n  \n  \n//-----------Address decoding & fifo empty ---------------\nalways@(*)\n  begin\n    case(data_in_tmp)\n    2'b00:begin\n\t  fifo_full<=full_0;\n\t  if(write_enb_reg)\n\t  write_enb<=3'b001;\n\t  else\n\t  write_enb<=0;\n\t  end\n    2'b01:begin\n\t  fifo_full<=full_1;\n\t  if(write_enb_reg)\n\t  write_enb<=3'b010;\n\t  else\n\t  write_enb<=0;\n\t  end\n    2'b10:begin\n\t  fifo_full<=full_2;\n\t  if(write_enb_reg)\n\t  write_enb<=3'b100;\n\t  else\n\t  write_enb<=0;\n\t  end\n    default:begin\n\t  fifo_full<=0;\n\t  write_enb<=0;\n\t  end\n    endcase\n  end\n  \n  \n  \n//-----------------------------------Valid Byte block----------------------------------\n\nassign vld_out_0 = (~empty_0);\nassign vld_out_1 = (~empty_1);\nassign vld_out_2 = (~empty_2);\n\n  \n//-----------------------------------Soft Reset block----------------------------------\n\nalways@(posedge clock)\n  begin\n  \n  if(~resetn)\n  begin\n  count0<=0;\n  soft_reset_0<=0;\n  end\n\n  else if(vld_out_0)\n  begin\n  if(~read_enb_0)\n   \n    begin\n    if(count0==29)\n      begin\n      soft_reset_0<=1'b1;\n      count0<=0;\n      end\n    else\n      begin\n      soft_reset_0<=1'b0;\n      count0<=count0+1'b1;\n      end\n    end\n  else\n  count0<=0;\n  end\n  end\n\nalways@(posedge clock)\n  begin\n  \n  if(~resetn)\n  begin\n  count1<=0;\n  soft_reset_1<=0;\n  end\n\n  else if(vld_out_1)\n  begin\n  if(~read_enb_1)\n   \n    begin\n    if(count1==29)\n      begin\n      soft_reset_1<=1'b1;\n      count1<=0;\n      end\n    else\n      begin\n      soft_reset_1<=1'b0;\n      count1<=count1+1'b1;\n      end\n    end\n  else\n  count1<=0;\n  end\n  end\n\nalways@(posedge clock)\n  begin\n  \n  if(~resetn)\n  begin\n  count2<=0;\n  soft_reset_2<=0;\n  end\n\n  else if(vld_out_2)\n  begin\n  if(~read_enb_2)\n   \n    begin\n    if(count2==29)\n      begin\n      soft_reset_2<=1'b1;\n      count2<=0;\n      end\n    else\n      begin\n      soft_reset_2<=1'b0;\n      count2<=count2+1'b1;\n      end\n    end\n  else\n  count2<=0;\n  end\n  end\n\nendmodule\n  \n\n\n\n\nmodule router_top(clock,resetn,pkt_valid,read_enb_0,read_enb_1,read_enb_2,data_in,\n\t\t\t\t    busy,err,vld_out_0,vld_out_1,vld_out_2,data_out_0,data_out_1,data_out_2);\n  \n  input [2:0]data_in;\n  input pkt_valid,clock,resetn,read_enb_0,read_enb_1,read_enb_2;\n  output [2:0]data_out_0,data_out_1,data_out_2;\n  output vld_out_0,vld_out_1,vld_out_2,err,busy;\n\t\n\twire soft_reset_0,full_0,empty_0,soft_reset_1,full_1,empty_1,soft_reset_2,full_2,empty_2,\n         fifo_full,detect_add,ld_state,laf_state,full_state,lfd_state,rst_int_reg,\n         parity_done,low_packet_valid,write_enb_reg;\n\twire [2:0]write_enb;\n\twire [2:0]d_in;\n\t\n    //-------fifo instantiation-----\n    \n   \n\t\n\trouter_fifo FIFO_0(.clock(clock),\n\t                   .resetn(resetn),\n\t\t           .soft_reset(soft_reset_0),\n\t\t\t   .write_enb(write_enb[0]),\n\t\t\t   .read_enb(read_enb_0),\n                           .lfd_state(lfd_state),\n\t\t\t   .data_in(d_in),\n\t\t\t   .full(full_0),\n\t\t\t   .empty(empty_0),\n\t\t\t   .data_out(data_out_0));\n\t\t\t\t   \n\t\t\t\t   \n\t\t\t\t   \n\t\t\t\t   \n\t\t\t\t   \n\t\n\trouter_fifo FIFO_1(.clock(clock),\n\t                   .resetn(resetn),\n\t\t\t   .soft_reset(soft_reset_1),\n\t\t\t   .write_enb(write_enb[1]),\n\t\t\t   .read_enb(read_enb_1),\n                           .lfd_state(lfd_state),\n\t\t           .data_in(d_in),\n\t\t\t   .full(full_1),\n\t\t\t   .empty(empty_1),\n\t\t\t   .data_out(data_out_1));\n\t\t\t\t\t   \n\t\t\t\t\t   \n\t\n\trouter_fifo FIFO_2(.clock(clock),\n\t                   .resetn(resetn),\n\t\t\t   .soft_reset(soft_reset_2),\n\t\t\t   .write_enb(write_enb[2]),\n\t\t\t   .read_enb(read_enb_2),\n                           .lfd_state(lfd_state),\n\t\t\t   .data_in(d_in),\n\t\t\t   .full(full_2),\n\t\t\t   .empty(empty_2),\n\t\t\t   .data_out(data_out_2));\n    \n    //-------register instantiation-----\t\n    \n\trouter_reg REGISTER(.clock(clock),\n\t                    .resetn(resetn),\n\t\t\t    .pkt_valid(pkt_valid),\n\t        \t    .data_in(data_in),\n\t\t\t    .fifo_full(fifo_full),\n\t        \t    .detect_add(detect_add),\n                            .ld_state(ld_state),\n\t\t\t    .laf_state(laf_state),\n\t\t\t    .full_state(full_state),\n\t       \t\t    .lfd_state(lfd_state),\n\t\t\t    .rst_int_reg(rst_int_reg),\n\t\t\t    .err(err),\n                            .parity_done(parity_done),\n\t\t\t    .low_packet_valid(low_packet_valid),\n\t\t\t    .dout(d_in));\n\t\t\t\t  \n\t\t\t\t  \n\t\t\t\t  \n\t\t\t\t  \n    \t\t\t\t\n    //-------synchronizer instantiation-----\n\n      \n    \n\t\t\t\t\t\t\t \n\trouter_sync SYNCHRONIZER(.clock(clock),\n\t                         .resetn(resetn),\n\t\t\t\t .data_in(data_in[1:0]),\n\t\t\t\t .detect_add(detect_add),\n\t\t\t\t .full_0(full_0),\n\t\t\t\t .full_1(full_1),\n\t\t\t\t .full_2(full_2),\n\t\t\t\t .empty_0(empty_0),\n\t\t\t\t .empty_1(empty_1),\n\t\t\t\t .empty_2(empty_2),\n\t\t\t\t .write_enb_reg(write_enb_reg),\n\t\t\t\t .read_enb_0(read_enb_0),\n\t\t\t\t .read_enb_1(read_enb_1),\n\t\t\t\t .read_enb_2(read_enb_2),\n\t\t\t\t .write_enb(write_enb),\n\t\t\t\t .fifo_full(fifo_full),\n\t\t\t\t .vld_out_0(vld_out_0),\n\t\t\t\t .vld_out_1(vld_out_1),\n\t\t\t\t .vld_out_2(vld_out_2),\n\t\t\t\t .soft_reset_0(soft_reset_0),\n\t\t\t\t .soft_reset_1(soft_reset_1),\n\t\t\t\t .soft_reset_2(soft_reset_2));\t\t\t\t\t\t \n\t\t\t\t\t\t\t \n\t\t\t\t\t\t\t \n\t\t\t\t\t\t\t \n    //-------fsm instantiation-----\n    \n\trouter_fsm FSM(.clock(clock),\n\t               .resetn(resetn),\n\t\t       .pkt_valid(pkt_valid),\n\t\t       .data_in(data_in[1:0]),\n\t\t       .fifo_full(fifo_full),\n\t\t       .fifo_empty_0(empty_0),\n\t\t       .fifo_empty_1(empty_1),\n\t\t       .fifo_empty_2(empty_2),\n                       .soft_reset_0(soft_reset_0),\n\t\t       .soft_reset_1(soft_reset_1),\n\t\t       .soft_reset_2(soft_reset_2),\n\t\t       .parity_done(parity_done),\n\t\t       .low_packet_valid(low_packet_valid),\n                       .write_enb_reg(write_enb_reg),\n\t               .detect_add(detect_add),\n\t\t       .ld_state(ld_state),\n\t\t       .laf_state(laf_state),\n\t\t       .lfd_state(lfd_state),\n\t\t       .full_state(full_state),\n\t               .rst_int_reg(rst_int_reg),\n\t               .busy(busy));\n   \nendmodule\n", "mask_idx": {"conditional_statement": [[8310, 8344], [8844, 9014], [6063, 6159], [9593, 9665], [2762, 2869], [2165, 2463], [8803, 9014]], "blocking_assignment": [[5492, 5511], [6651, 6666], [5375, 5390], [6339, 6358], [5296, 5316], [6405, 6424]], "module_program_interface_instantiation": [[14406, 14930], [13342, 13659], [15036, 15691]], "always_construct": [[7910, 8353], [1465, 1595], [10627, 10749], [8446, 8681], [1953, 2485], [8767, 9019], [11924, 12287], [4485, 6776]], "case_statement": [[4539, 6769], [10841, 11268]], "ansi_port_declaration": [[7501, 7527], [3492, 3560], [3604, 3662]], "continuous_assign": [[3244, 3309], [6917, 6963], [6966, 7011]], "parameter_declaration": [[3935, 4232]], "nonblocking_assignment": [[8862, 8877], [4459, 4468], [11826, 11845]]}, "all_mask_idx": {"module_program_interface_instantiation": [[668, 1053], [13342, 13659], [13703, 14020], [14042, 14352], [14406, 14930], [15036, 15691], [15761, 16525]], "continuous_assign": [[612, 638], [640, 666], [3244, 3309], [3312, 3354], [6782, 6830], [6833, 6914], [6917, 6963], [6966, 7011], [7014, 7158], [7222, 7260], [7263, 7308], [7311, 7361], [11373, 11403], [11404, 11434], [11435, 11465]], "blocking_assignment": [[1697, 1713], [1751, 1767], [1814, 1851], [1889, 1905], [4512, 4532], [4873, 4894], [5206, 5227], [5296, 5316], [5375, 5390], [5492, 5511], [5581, 5596], [5623, 5636], [5810, 5829], [5901, 5920], [5947, 5966], [6091, 6110], [6141, 6159], [6204, 6226], [6339, 6358], [6405, 6424], [6565, 6578], [6651, 6666], [6714, 6732]], "nonblocking_assignment": [[1524, 1541], [1561, 1586], [2078, 2088], [2216, 2246], [2264, 2299], [2370, 2400], [2418, 2453], [2605, 2619], [2664, 2689], [2783, 2797], [2844, 2869], [3067, 3109], [3152, 3174], [4327, 4348], [4417, 4438], [4459, 4468], [7980, 7994], [8001, 8015], [8022, 8036], [8117, 8133], [8165, 8178], [8223, 8237], [8281, 8298], [8330, 8344], [8513, 8534], [8573, 8593], [8654, 8674], [8818, 8833], [8862, 8877], [8999, 9014], [9153, 9167], [9191, 9205], [9241, 9271], [9321, 9352], [9361, 9384], [9535, 9542], [9630, 9637], [9658, 9665], [9693, 9700], [9848, 9862], [9894, 9908], [10019, 10039], [10678, 10693], [10722, 10743], [10878, 10896], [10921, 10939], [10951, 10964], [10991, 11009], [11034, 11052], [11064, 11077], [11104, 11122], [11147, 11165], [11177, 11190], [11219, 11232], [11236, 11249], [11617, 11627], [11630, 11646], [11752, 11771], [11778, 11788], [11826, 11845], [11852, 11872], [11900, 11910], [11982, 11992], [11995, 12011], [12117, 12136], [12143, 12153], [12191, 12210], [12217, 12237], [12265, 12275], [12347, 12357], [12360, 12376], [12482, 12501], [12508, 12518], [12556, 12575], [12582, 12602], [12630, 12640]], "case_statement": [[4539, 6769], [10841, 11268]], "conditional_statement": [[1504, 1586], [1675, 1905], [1725, 1905], [1779, 1905], [1863, 1905], [1993, 2476], [2113, 2476], [2165, 2463], [2585, 2689], [2631, 2689], [2762, 2869], [2810, 2869], [2972, 3186], [3019, 3174], [3125, 3174], [4307, 4468], [4360, 4468], [4627, 5316], [4941, 5316], [5469, 5636], [5543, 5636], [5744, 5966], [5848, 5966], [6063, 6159], [6309, 6424], [6376, 6424], [6512, 6732], [6599, 6732], [6687, 6732], [7949, 8344], [8060, 8344], [8145, 8344], [8190, 8344], [8249, 8344], [8310, 8344], [8495, 8674], [8551, 8674], [8614, 8674], [8803, 9014], [8844, 9014], [8889, 9014], [9139, 9384], [9174, 9384], [9212, 9384], [9278, 9384], [9517, 9700], [9555, 9700], [9593, 9665], [9831, 10039], [9874, 10039], [9920, 10039], [10662, 10743], [10703, 10743], [10900, 10964], [11013, 11077], [11126, 11190], [11595, 11916], [11661, 11916], [11685, 11910], [11719, 11882], [11960, 12281], [12026, 12281], [12050, 12275], [12084, 12247], [12325, 12646], [12391, 12646], [12415, 12640], [12449, 12612]], "always_construct": [[1465, 1595], [1635, 1913], [1953, 2485], [2543, 2698], [2706, 2878], [2933, 3194], [4268, 4476], [4485, 6776], [7910, 8353], [8446, 8681], [8767, 9019], [9103, 9389], [9476, 9711], [9795, 10045], [10627, 10749], [10818, 11274], [11559, 11922], [11924, 12287], [12289, 12652]], "parameter_declaration": [[3935, 4232]], "ansi_port_declaration": [[128, 175], [180, 228], [233, 279], [284, 331], [336, 416], [421, 509], [514, 550], [555, 608], [1090, 1133], [1096, 1133], [1103, 1133], [1114, 1133], [1124, 1133], [1153, 1192], [1163, 1192], [1171, 1192], [1176, 1192], [1182, 1192], [3393, 3473], [3399, 3473], [3406, 3473], [3416, 3473], [3424, 3473], [3434, 3473], [3447, 3473], [3460, 3473], [3492, 3560], [3505, 3560], [3518, 3560], [3531, 3560], [3543, 3560], [3579, 3662], [3593, 3662], [3604, 3662], [3613, 3662], [3623, 3662], [3633, 3662], [3644, 3662], [3656, 3662], [7400, 7452], [7406, 7452], [7413, 7452], [7423, 7452], [7431, 7452], [7441, 7452], [7471, 7527], [7480, 7527], [7490, 7527], [7501, 7527], [7511, 7527], [7523, 7527], [7546, 7581], [7558, 7581], [7575, 7581], [10079, 10293], [10085, 10293], [10092, 10293], [10100, 10293], [10111, 10293], [10118, 10293], [10125, 10293], [10132, 10293], [10140, 10293], [10148, 10293], [10156, 10293], [10170, 10293], [10181, 10293], [10192, 10293], [10203, 10293], [10213, 10293], [10223, 10293], [10233, 10293], [10243, 10293], [10253, 10293], [10266, 10293], [10279, 10293], [12689, 12753], [12695, 12753], [12702, 12753], [12712, 12753], [12723, 12753], [12734, 12753], [12745, 12753], [12762, 12835], [12767, 12835], [12771, 12835], [12781, 12835], [12791, 12835], [12801, 12835], [12812, 12835], [12823, 12835]]}}
{"sample_i": "mitsece-tt07-verilog-mitssdd", "topmodule": "tt_um_mitssdd", "code": "/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_mitssdd (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  // All output pins must be assigned. If not used, assign to 0.\n\n  assign uio_out = 0;\n  assign uio_oe  = 0;\n     co_processor co_processor  (\n    .clk(clk),\n    .reset(rst_n),\n\t.r0(ui_in),\n\t.check(uio_in[1:0]),\n\t     .Q(uo_out[0]),\n\t         .Q1(uo_out[7:6])\n\t\n);\n    fault_pro fault_pro  (\n    .clk(clk),\n    .reset(rst_n),\n\t.r0(ui_in),\n\t.check(uio_in[1:0]),\n\t.out(uo_out[3:1]),\n\t.out1(uo_out[5:4])\n\t\t\n\t\n);\n\nendmodule\n\n\nmodule co_processor (\n    input [7:0] r0, // 8-bit input\n    input [1:0] check, // sensor checking\n    input reset,\n    input clk, // clock input\n    output reg Q, // output Q connected to LED\n    output reg [1:0] Q1\n);\n\n\n\nreg [7:0] proc = 8'b0; // processing register\nreg [7:0] r1 = 8'b0;\nreg [7:0] r2 = 8'b0;\nreg [7:0] r3 = 8'b0;\nreg [7:0] r4 = 8'b0;\nreg [7:0] res = 8'b0;\nreg [7:0] data = 8'b0;\nreg [1:0] sense = 2'b0;\n\n\n\nalways @(posedge clk or posedge reset) begin\n    if (reset) begin\n        r1 <= 8'b0;\n        r2 <= 8'b0;\n        r3 <= 8'b0;\n        r4 <= 8'b0;\n        Q <= 1'b0;\n\t\tQ1 <= 2'b0;\n\t\tdata <= 8'b0;\n\t\tsense <= 2'b0;\n\t\tproc = 8'b0;\n    end else begin\n    data <= r0;\n    sense <= check;\n\n            case (sense)\n                2'b00: proc = r1;\n                2'b01: proc = r2;\n                2'b10: proc = r3;\n                2'b11: proc = r4;\n            endcase\n\n            if (proc == data) begin\n                Q <= 1'b0;\n                Q1 <= 2'b00;\n            end else begin\n                if (proc > data) begin\n                    res = proc - data;\n                end else begin\n                    res = data - proc;\n                end\n\n                if (res > 8'b00000010) begin\n                \n                    if (sense == 2'b00) begin\n                        r1 <= data;\n                        Q1 <= 2'b00; \n                        end\n                    if (sense == 2'b01) begin\n                        r2 <= data;\n                        Q1 <= 2'b01;\n                        end\n                    if (sense == 2'b10) begin\n                        r3 <= data;\n                        Q1 <= 2'b10;\n                        end\n                    if (sense == 2'b11) begin\n                        r4 <= data;\n                        Q1 <= 2'b11;\n                        end\n                        \n                    Q <= 1'b1;\n                end else begin\n                    Q <= 1'b0;\n                    Q1 <= 2'b00;\n                   \n                end\n            end\n        \n    end\nend\n\nendmodule\n\n\nmodule fault_pro(\n\tinput [7:0] r0,\n\tinput [1:0] check,\n\tinput reset,\n\tinput clk,\n\toutput reg [2:0] out,\n\toutput reg [1:0] out1);\n\t\n\t//data storing registers\n\treg [9:0] r1=10'b0;  \n\treg [9:0] r2=10'b0;\n\treg [9:0] r3=10'b0;\n\treg [9:0] r4=10'b0;\n\n\t//1st 4 set mean values\n\treg [9:0] m1=10'b0;\n\treg [9:0] m2=10'b0;\n\treg [9:0] m3=10'b0;\n\treg [9:0] m4=10'b0;\n\n\t//2nd 4 set mean values\n\treg [9:0] w1=10'b0;\n\treg [9:0] w2=10'b0;\n\treg [9:0] w3=10'b0;\n\treg [9:0] w4=10'b0;\n\n\t//Difference storing register\n\treg [9:0] diff1=10'b0;  \n\treg [9:0] diff2=10'b0;\n\treg [9:0] diff3=10'b0;\n\treg [9:0] diff4=10'b0;\n\n\t\n\treg [2:0] counter1 = 3'b0;\n\treg [2:0] counter2 = 3'b0;\n\treg [2:0] counter3 = 3'b0;\n\treg [2:0] counter4 = 3'b0;\n\n\t\n\treg f1 = 1'b0;\n\treg f2 = 1'b0;\n\treg f3 = 1'b0;\n\treg f4 = 1'b0;\n\t\n\talways @(posedge clk or posedge reset) begin\n\t\n\t\tif (reset) begin // Reset\n\t\t\tr1 <= 10'b0;\n\t\t\tr2 <= 10'b0;\n\t\t\tr3 <= 10'b0;\n\t\t\tr4 <= 10'b0;\n\t\t\t\n\t\t\tm1 <= 10'b0;\n\t\t\tm2 <= 10'b0;\n\t\t\tm3 <= 10'b0;\n\t\t\tm4 <= 10'b0;\n\t\t\t\n\t\t\tw1 <= 10'b0;\n\t\t\tw2 <= 10'b0;\n\t\t\tw3 <= 10'b0;\n\t\t\tw4 <= 10'b0;\n\t\t\t\n\t\t\tdiff1 <= 10'b0;\n\t\t\tdiff2 <= 10'b0;\n\t\t\tdiff3 <= 10'b0;\n\t\t\tdiff4 <= 10'b0;\n\t\t\t\n\t\t\tcounter1 <= 3'b0;\n\t\t\tcounter2 <= 3'b0;\n\t\t\tcounter3 <= 3'b0;\n\t\t\tcounter4 <= 3'b0;\n\n\t\t\t\n\t\t\tf1 <= 1'b0;\n\t\t\tf2 <= 1'b0;\n\t\t\tf3 <= 1'b0;\n\t\t\tf4 <= 1'b0;\n\t\t\t\n\t\t\tout <= 3'b0;\n\t\t\tout1 <= 2'b0;\n\t\t\t\n\t\tend else begin\n\t\t\n\n\t\t\t\t\n\t\t\t\tcase (check)\n\t\t\t\t\t2'b00: begin\n\t\t\t\t\t\t\tr1 <= r1 + r0;\n\t\t\t\t\t\t\tcounter1 <= counter1 + 1;\n\t\t\t\t\t\tend\n\t\t\t\t\t2'b01: begin\n\t\t\t\t\t\t\tr2 <= r2 + r0;\n\t\t\t\t\t\t\tcounter2 <= counter2 + 1;\n\t\t\t\t\t\tend\n\t\t\t\t\t2'b10: begin\n\t\t\t\t\t\t\tr3 <= r3 + r0;\n\t\t\t\t\t\t\tcounter3 <= counter3 + 1;\n\t\t\t\t\t\tend\n\t\t\t\t\t2'b11: begin\n\t\t\t\t\t\t\tr4 <= r4 + r0;\n\t\t\t\t\t\t\tcounter4 <= counter4 + 1;\n\t\t\t\t\t\tend\n\t\t\t\tendcase\n\t\t\t\t\n\t\t\t\tif(f1 == 0 && counter1 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tm1 <= r1 >> 2;\n\t\t\t\t\tr1 <= 10'b0;\n\t\t\t\t\tcounter1 <= 3'b0;\n\t\t\t\t\tf1 <= 1'b1;\n\t\t\t\tend\n\t\t\t\tif(f2 == 0 && counter2 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tm2 <= r2 >> 2;\n\t\t\t\t\tr2 <= 10'b0;\n\t\t\t\t\tcounter2 <= 3'b0;\n\t\t\t\t\tf2 <= 1'b1;\n\t\t\t\tend\n\t\t\t\tif(f3 == 0 && counter3 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tm3 <= r3 >> 2;\n\t\t\t\t\tr3 <= 10'b0;\n\t\t\t\t\tcounter3 <= 3'b0;\n\t\t\t\t\tf3 <= 1'b1;\n\t\t\t\tend\n\t\t\t\tif(f4 == 0 && counter4 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tm4 <= r4 >> 2;\n\t\t\t\t\tr4 <= 10'b0;\n\t\t\t\t\tcounter4 <= 3'b0;\n\t\t\t\t\tf4 <= 1'b1;\n\t\t\t\tend\n\t\t\t\t\n////////////////////////////////////////////////////////////////////////////////\t\t\t\t\n\t\t\t\t\n\t\t\t\tif(f1 == 1 && counter1 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tw1 <= r1 >> 2;\n\t\t\t\t\tr1 <= 10'b0;\n\t\t\t\t\tcounter1 <= 3'b0;\n\t\t\t\t\tf1 <= 1'b0;\n\t\t\t\tend\n\t\t\t\tif(f2 == 1 && counter2 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tw2 <= r2 >> 2;\n\t\t\t\t\tr2 <= 10'b0;\n\t\t\t\t\tcounter2 <= 3'b0;\n\t\t\t\t\tf2 <= 1'b0;\n\t\t\t\tend\n\t\t\t\tif(f3 == 1 && counter3 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tw3 <= r3 >> 2;\n\t\t\t\t\tr3 <= 10'b0;\n\t\t\t\t\tcounter3 <= 3'b0;\n\t\t\t\t\tf3 <= 1'b0;\n\t\t\t\tend\n\t\t\t\tif(f4 == 1 && counter4 == 4) begin //checking whether sum of 4 data was calculated \n\t\t\t\t\tw4 <= r4 >> 2;\n\t\t\t\t\tr4 <= 10'b0;\n\t\t\t\t\tcounter4 <= 3'b0;\n\t\t\t\t\tf4 <= 1'b0;\n\t\t\t\tend\n\t\t\t\t\n\t\t\t\tdiff1 <= (w1 > m1) ? (w1 - m1) : (m1 - w1);\n\t\t\t\tdiff2 <= (w2 > m2) ? (w2 - m2) : (m2 - w2);\n\t\t\t\tdiff3 <= (w3 > m3) ? (w3 - m3) : (m3 - w3);\n\t\t\t\tdiff4 <= (w4 > m4) ? (w4 - m4) : (m4 - w4);\n\t\t\t\t\n\t\t\t\tif(diff1 >= 100) begin\n\t\t\t\t\tout <= 3'b100;\n\t\t\t\t\tout1 <= 2'b00;\n\t\t\t\t\tdiff1 <= 10'b0;\n\t\t\t\t\tw1 <= 10'b0;\n\t\t\t\t\tm1 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff1 >= 50 && diff1 < 100) begin\n\t\t\t\t\t\tout <= 3'b011;\n\t\t\t\t\t\tout1 <= 2'b00;\n\t\t\t\t\t\tdiff1 <= 10'b0;\n\t\t\t\t\t\tw1 <= 10'b0;\n\t\t\t\t\t\tm1 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff1 >= 25 && diff1 < 50) begin\n\t\t\t\t\t\tout <= 3'b010;\n\t\t\t\t\t\tout1 <= 2'b00;\n\t\t\t\t\t\tdiff1 <= 10'b0;\n\t\t\t\t\t\tw1 <= 10'b0;\n\t\t\t\t\t\tm1 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff1 >= 10 && diff1 < 25) begin\n\t\t\t\t\t\tout <= 3'b001;\n\t\t\t\t\t\tout1 <= 2'b00;\n\t\t\t\t\t\tdiff1 <= 10'b0;\n\t\t\t\t\t\tw1 <= 10'b0;\n\t\t\t\t\t\tm1 <= 10'b0;\n\t\t\t\tend\n\t\t\t\tif(diff2 >= 100) begin\n\t\t\t\t\tout <= 3'b100;\n\t\t\t\t\tout1 <= 2'b01;\n\t\t\t\t\tdiff2 <= 10'b0;\n\t\t\t\t\tw2 <= 10'b0;\n\t\t\t\t\tm2 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff2 >= 50 && diff2 < 100) begin\n\t\t\t\t\t\tout <= 3'b011;\n\t\t\t\t\t\tout1 <= 2'b01;\n\t\t\t\t\t\tdiff2 <= 10'b0;\n\t\t\t\t\t\tw2 <= 10'b0;\n\t\t\t\t\t\tm2 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff2 >= 25 && diff2 < 50) begin\n\t\t\t\t\t\tout <= 3'b010;\n\t\t\t\t\t\tout1 <= 2'b01;\n\t\t\t\t\t\tdiff2 <= 10'b0;\n\t\t\t\t\t\tw2 <= 10'b0;\n\t\t\t\t\t\tm2 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff2 >= 10 && diff2 < 25) begin\n\t\t\t\t\t\tout <= 3'b001;\n\t\t\t\t\t\tout1 <= 2'b01;\n\t\t\t\t\t\tdiff2 <= 10'b0;\n\t\t\t\t\t\tw2 <= 10'b0;\n\t\t\t\t\t\tm2 <= 10'b0;\n\t\t\t\tend\n\t\t\t\tif(diff3 >= 100) begin\n\t\t\t\t\tout <= 3'b100;\n\t\t\t\t\tout1 <= 2'b10;\n\t\t\t\t\tdiff3 <= 10'b0;\n\t\t\t\t\tw3 <= 10'b0;\n\t\t\t\t\tm3 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff3 >= 50 && diff3 <100) begin\n\t\t\t\t\t\tout <= 3'b011;\n\t\t\t\t\t\tout1 <= 2'b10;\n\t\t\t\t\t\tdiff3 <= 10'b0;\n\t\t\t\t\t\tw3 <= 10'b0;\n\t\t\t\t\t\tm3 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff3 >= 25 && diff3 <50) begin\n\t\t\t\t\t\tout <= 3'b010;\n\t\t\t\t\t\tout1 <= 2'b10;\n\t\t\t\t\t\tdiff3 <= 10'b0;\n\t\t\t\t\t\tw3 <= 10'b0;\n\t\t\t\t\t\tm3 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff3 >= 10 && diff3 <25) begin\n\t\t\t\t\t\tout <= 3'b001;\n\t\t\t\t\t\tout1 <= 2'b10;\n\t\t\t\t\t\tdiff3 <= 10'b0;\n\t\t\t\t\t\tw3 <= 10'b0;\n\t\t\t\t\t\tm3 <= 10'b0;\n\t\t\t\tend\n\t\t\t\tif(diff4 >= 100) begin\n\t\t\t\t\tout <= 3'b100;\n\t\t\t\t\tout1 <= 2'b11;\n\t\t\t\t\tdiff4 <= 10'b0;\n\t\t\t\t\tw4 <= 10'b0;\n\t\t\t\t\tm4 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff4 >= 50 && diff4 <100) begin\n\t\t\t\t\t\tout <= 3'b011;\n\t\t\t\t\t\tout1 <= 2'b11;\n\t\t\t\t\t\tdiff4 <= 10'b0;\n\t\t\t\t\t\tw4 <= 10'b0;\n\t\t\t\t\t\tm4 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff4 >= 25 && diff4 <50) begin\n\t\t\t\t\t\tout <= 3'b010;\n\t\t\t\t\t\tout1 <= 2'b11;\n\t\t\t\t\t\tdiff4 <= 10'b0;\n\t\t\t\t\t\tw4 <= 10'b0;\n\t\t\t\t\t\tm4 <= 10'b0;\n\t\t\t\tend\n\t\t\t\telse if(diff4 >= 10 && diff4 <25) begin\n\t\t\t\t\t\tout <= 3'b001;\n\t\t\t\t\t\tout1 <= 2'b11;\n\t\t\t\t\t\tdiff4 <= 10'b0;\n\t\t\t\t\t\tw4 <= 10'b0;\n\t\t\t\t\t\tm4 <= 10'b0;\n\t\t\t\tend\t\n\t\t\t\t\n\t\t\tend\n\t\t\t\n\t\t\t\t\t\t\t\t\n\tend\t\nendmodule\t\n", "mask_idx": {"conditional_statement": [[5352, 5521], [5004, 5173], [2445, 2571], [8007, 8305], [2297, 2424], [8602, 8901]], "blocking_assignment": [[1895, 1905], [2105, 2123], [2175, 2193], [1793, 1803], [1861, 1871]], "module_program_interface_instantiation": [[884, 1023], [729, 879]], "always_construct": [[1462, 3093], [3885, 8932]], "case_statement": [[1757, 1925], [4464, 4820]], "ansi_port_declaration": [[1098, 1135], [515, 551], [3189, 3210]], "continuous_assign": [[682, 701], [704, 723]], "nonblocking_assignment": [[1556, 1567], [8131, 8143], [8818, 8832], [5305, 5322], [8664, 8678]]}, "all_mask_idx": {"module_program_interface_instantiation": [[729, 879], [884, 1023]], "continuous_assign": [[682, 701], [704, 723]], "blocking_assignment": [[1676, 1688], [1793, 1803], [1827, 1837], [1861, 1871], [1895, 1905], [2105, 2123], [2175, 2193]], "nonblocking_assignment": [[1536, 1547], [1556, 1567], [1576, 1587], [1596, 1607], [1616, 1626], [1629, 1640], [1643, 1656], [1659, 1673], [1712, 1723], [1728, 1743], [1979, 1989], [2006, 2018], [2347, 2358], [2383, 2396], [2495, 2506], [2531, 2543], [2642, 2653], [2678, 2690], [2789, 2800], [2825, 2837], [2911, 2921], [2973, 2983], [3004, 3016], [3963, 3975], [3979, 3991], [3995, 4007], [4011, 4023], [4031, 4043], [4047, 4059], [4063, 4075], [4079, 4091], [4099, 4111], [4115, 4127], [4131, 4143], [4147, 4159], [4167, 4182], [4186, 4201], [4205, 4220], [4224, 4239], [4247, 4264], [4268, 4285], [4289, 4306], [4310, 4327], [4336, 4347], [4351, 4362], [4366, 4377], [4381, 4392], [4400, 4412], [4416, 4429], [4502, 4516], [4524, 4549], [4585, 4599], [4607, 4632], [4668, 4682], [4690, 4715], [4751, 4765], [4773, 4798], [4919, 4933], [4939, 4951], [4957, 4974], [4980, 4991], [5093, 5107], [5113, 5125], [5131, 5148], [5154, 5165], [5267, 5281], [5287, 5299], [5305, 5322], [5328, 5339], [5441, 5455], [5461, 5473], [5479, 5496], [5502, 5513], [5710, 5724], [5730, 5742], [5748, 5765], [5771, 5782], [5884, 5898], [5904, 5916], [5922, 5939], [5945, 5956], [6058, 6072], [6078, 6090], [6096, 6113], [6119, 6130], [6232, 6246], [6252, 6264], [6270, 6287], [6293, 6304], [6322, 6365], [6370, 6413], [6418, 6461], [6466, 6509], [6547, 6561], [6567, 6581], [6587, 6602], [6608, 6620], [6626, 6638], [6699, 6713], [6720, 6734], [6741, 6756], [6763, 6775], [6782, 6794], [6854, 6868], [6875, 6889], [6896, 6911], [6918, 6930], [6937, 6949], [7009, 7023], [7030, 7044], [7051, 7066], [7073, 7085], [7092, 7104], [7145, 7159], [7165, 7179], [7185, 7200], [7206, 7218], [7224, 7236], [7297, 7311], [7318, 7332], [7339, 7354], [7361, 7373], [7380, 7392], [7452, 7466], [7473, 7487], [7494, 7509], [7516, 7528], [7535, 7547], [7607, 7621], [7628, 7642], [7649, 7664], [7671, 7683], [7690, 7702], [7743, 7757], [7763, 7777], [7783, 7798], [7804, 7816], [7822, 7834], [7894, 7908], [7915, 7929], [7936, 7951], [7958, 7970], [7977, 7989], [8048, 8062], [8069, 8083], [8090, 8105], [8112, 8124], [8131, 8143], [8202, 8216], [8223, 8237], [8244, 8259], [8266, 8278], [8285, 8297], [8338, 8352], [8358, 8372], [8378, 8393], [8399, 8411], [8417, 8429], [8489, 8503], [8510, 8524], [8531, 8546], [8553, 8565], [8572, 8584], [8643, 8657], [8664, 8678], [8685, 8700], [8707, 8719], [8726, 8738], [8797, 8811], [8818, 8832], [8839, 8854], [8861, 8873], [8880, 8892]], "case_statement": [[1757, 1925], [4464, 4820]], "conditional_statement": [[1511, 3089], [1939, 3072], [2062, 2213], [2231, 3056], [2297, 2424], [2445, 2571], [2592, 2718], [2739, 2865], [3934, 8913], [4830, 4999], [5004, 5173], [5178, 5347], [5352, 5521], [5621, 5790], [5795, 5964], [5969, 6138], [6143, 6312], [6519, 7112], [6656, 7112], [6812, 7112], [6967, 7112], [7117, 7710], [7254, 7710], [7410, 7710], [7565, 7710], [7715, 8305], [7852, 8305], [8007, 8305], [8161, 8305], [8310, 8901], [8447, 8901], [8602, 8901], [8756, 8901]], "always_construct": [[1462, 3093], [3885, 8932]], "parameter_declaration": [], "ansi_port_declaration": [[129, 176], [181, 229], [234, 280], [285, 332], [337, 417], [422, 510], [515, 551], [556, 609], [1063, 1093], [1098, 1135], [1140, 1152], [1157, 1182], [1187, 1229], [1234, 1253], [3126, 3141], [3143, 3161], [3163, 3175], [3177, 3187], [3189, 3210], [3212, 3235]]}}
{"sample_i": "rejunity-vga-checkers", "topmodule": "tt_um_rejunity_vga", "code": "/*\n * Copyright (c) 2024 ReJ aka Renaldas Zioma\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\n/*\nVideo sync generator, used to drive a VGA monitor.\nTiming from: https://en.wikipedia.org/wiki/Video_Graphics_Array\nTo use:\n- Wire the hsync and vsync signals to top level outputs\n- Add a 3-bit (or more) \"rgb\" output to the top level\n*/\n\nmodule hvsync_generator(clk, reset, hsync, vsync, display_on, hpos, vpos);\n\n  input clk;\n  input reset;\n  output reg hsync, vsync;\n  output display_on;\n  output reg [9:0] hpos;\n  output reg [9:0] vpos;\n\n  // declarations for TV-simulator sync parameters\n  // horizontal constants\n  parameter H_DISPLAY       = 640; // horizontal display width\n  parameter H_BACK          =  48; // horizontal left border (back porch)\n  parameter H_FRONT         =  16; // horizontal right border (front porch)\n  parameter H_SYNC          =  96; // horizontal sync width\n  // vertical constants\n  parameter V_DISPLAY       = 480; // vertical display height\n  parameter V_TOP           =  33; // vertical top border\n  parameter V_BOTTOM        =  10; // vertical bottom border\n  parameter V_SYNC          =   2; // vertical sync # lines\n  // derived constants\n  parameter H_SYNC_START    = H_DISPLAY + H_FRONT;\n  parameter H_SYNC_END      = H_DISPLAY + H_FRONT + H_SYNC - 1;\n  parameter H_MAX           = H_DISPLAY + H_BACK + H_FRONT + H_SYNC - 1;\n  parameter V_SYNC_START    = V_DISPLAY + V_BOTTOM;\n  parameter V_SYNC_END      = V_DISPLAY + V_BOTTOM + V_SYNC - 1;\n  parameter V_MAX           = V_DISPLAY + V_TOP + V_BOTTOM + V_SYNC - 1;\n\n  wire hmaxxed = (hpos == H_MAX) || reset;  // set when hpos is maximum\n  wire vmaxxed = (vpos == V_MAX) || reset;  // set when vpos is maximum\n  \n  // horizontal position counter\n  always @(posedge clk)\n  begin\n    hsync <= (hpos>=H_SYNC_START && hpos<=H_SYNC_END);\n    if(hmaxxed)\n      hpos <= 0;\n    else\n      hpos <= hpos + 1;\n  end\n\n  // vertical position counter\n  always @(posedge clk)\n  begin\n    vsync <= (vpos>=V_SYNC_START && vpos<=V_SYNC_END);\n    if(hmaxxed)\n      if (vmaxxed)\n        vpos <= 0;\n      else\n        vpos <= vpos + 1;\n  end\n  \n  // display_on is set when beam is in \"safe\" visible frame\n  assign display_on = (hpos<H_DISPLAY) && (vpos<V_DISPLAY);\n\nendmodule\n\n\nmodule tt_um_rejunity_vga(\n  input  wire [7:0] ui_in,    // Dedicated inputs\n  output wire [7:0] uo_out,   // Dedicated outputs\n  input  wire [7:0] uio_in,   // IOs: Input path\n  output wire [7:0] uio_out,  // IOs: Output path\n  output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n  input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n  input  wire       clk,      // clock\n  input  wire       rst_n     // reset_n - low to reset\n);\n\n  // VGA signals\n  wire hsync;\n  wire vsync;\n  wire [1:0] R;\n  wire [1:0] G;\n  wire [1:0] B;\n  wire video_active;\n  wire [9:0] pix_x;\n  wire [9:0] pix_y;\n\n  // TinyVGA PMOD\n  assign uo_out = {hsync, B[0], G[0], R[0], vsync, B[1], G[1], R[1]};\n\n  // Unused outputs assigned to 0.\n  assign uio_out = 0;\n  assign uio_oe  = 0;\n\n  // Suppress unused signals warning\n  wire _unused_ok = &{ena, ui_in, uio_in};\n\n  reg [9:0] counter;\n\n  hvsync_generator hvsync_gen(\n    .clk(clk),\n    .reset(~rst_n),\n    .hsync(hsync),\n    .vsync(vsync),\n    .display_on(video_active),\n    .hpos(pix_x),\n    .vpos(pix_y)\n  );\n  \n  wire [9:0] moving_x = pix_x + counter*16;\n  wire [9:0] moving_y = pix_y + counter*2;\n\n  wire [9:0] moving_x2 = pix_x + counter*7;\n  wire [9:0] moving_y2 = pix_y + counter + counter/2;\n\n  wire [9:0] moving_x3 = pix_x + counter*4;\n  wire [9:0] moving_y3 = pix_y + counter/2;\n\n  wire [9:0] moving_x4 = pix_x + counter*2;\n  wire [9:0] moving_y4 = pix_y + counter/4;\n\n  wire [9:0] moving_x5 = pix_x + counter/2;\n  wire [9:0] moving_y5 = pix_y + counter/6;\n\n  wire a = moving_x[8] ^ moving_y[8];\n  wire b = moving_x2[7] ^ moving_y2[7];\n  wire c = moving_x3[6] ^ moving_y3[6];\n  wire d = moving_x4[5] ^ moving_y4[5];\n  wire e = moving_x5[4] ^ moving_y5[4];\n\n  // wire x = a | b | c | d | e;\n\n  // assign {R, G, B} = \n  //     video_active ? \n  //       (a ? 6'b11_11_01 :\n  //         (b ? 6'b11_10_01 : \n  //           (c ? 6'b11_01_00 : \n  //             (d ? 6'b10_00_00 : 6'b00_00_00)))) : 6'b00_00_00;\n\n  wire [5:0] white = ~ui_in[5:0];\n  wire [5:0] grey = white ^ 6'b00_10_10;\n\n  assign {R, G, B} = \n      video_active ? \n        // (a ? (pix_y[0] ^ pix_x[0] ? 6'b11_11_11 : 6'b00_00_00) :\n        ((a & (pix_y[1] ^ pix_x[0])) ? white :\n          (b & (~pix_y[0] ^ pix_x[1]) ? grey : \n            (c ? 6'b10_00_00 : \n              (d ? 6'b01_00_00 :\n                (e & (pix_y[1] ^ pix_x[0]) ? 6'b01_00_00 : 6'b00_00_00))))) : 6'b00_00_00;\n\n  // assign {R, G, B} = \n  //     video_active ? \n  //       // (a ? (pix_y[0] ^ pix_x[0] ? 6'b11_11_11 : 6'b00_00_00) :\n  //       ((a & (pix_y[1] ^ pix_x[0])) ? 6'b11_11_11 :\n  //         (b & (~pix_y[0] ^ pix_x[1]) ? 6'b11_10_10 : \n  //           (c ? 6'b10_00_00 : \n  //             (d ? 6'b01_00_00 :\n  //               (e ? 6'b01_00_00 : 6'b00_00_00))))) : 6'b00_00_00;\n\n\n  // assign {R, G, B} = \n  //     video_active ? \n  //       // (a ? (pix_y[0] ^ pix_x[0] ? 6'b11_11_11 : 6'b00_00_00) :\n  //       ((a & (pix_y[1] ^ pix_x[0])) ? 6'b11_11_11 :\n  //         (b & (~pix_y[0] ^ pix_x[1]) ? 6'b11_10_10 : \n  //           (c ? 6'b10_00_00 : \n  //             (d ? 6'b01_00_00 : 6'b00_00_00)))) : 6'b00_00_00;\n\n\n  // assign {R, G, B} = \n  //     video_active ? \n  //       // (a ? (pix_y[0] ^ pix_x[0] ? 6'b11_11_11 : 6'b00_00_00) :\n  //       ((a & (pix_y[0] ^ pix_x[0])) ? 6'b11_11_11 :\n  //         (b ? 6'b11_00_01 : \n  //           (c ? 6'b10_00_00 : \n  //             (d ? 6'b01_00_00 : 6'b00_00_00)))) : 6'b00_00_00;\n\n\n    // video_active ? \n    //   a ? 6'b11_11_00 : 6'b00_00_00;\n  \n\n  // assign R = video_active ? {moving_x[6], moving_y[6]} : 2'b00;\n  // assign R = video_active ? x * 2'b11 : 2'b00;\n  // assign G = 2'b00;//video_active ? {moving_x[6], pix_y[2]} : 2'b00;\n  // assign B = 2'b00;//video_active ? {moving_x[7], pix_y[5]} : 2'b00;\n  \n  always @(posedge vsync) begin\n    if (~rst_n) begin\n      counter <= 0;\n    end else begin\n      counter <= counter + 1;\n    end\n  end\n  \nendmodule\n", "mask_idx": {"conditional_statement": [[2037, 2123], [6112, 6206], [1846, 1907]], "module_program_interface_instantiation": [[3195, 3367]], "always_construct": [[1757, 1913], [6078, 6212], [1948, 2129]], "ansi_port_declaration": [[2669, 2705], [2708, 2761], [391, 429]], "continuous_assign": [[2195, 2252], [3069, 3088], [2941, 3008]], "parameter_declaration": [[637, 697], [1054, 1112], [700, 771], [850, 907], [1386, 1435], [1198, 1246], [1438, 1500], [774, 847], [1313, 1383]], "nonblocking_assignment": [[6175, 6198], [1982, 2032], [1864, 1874]]}, "all_mask_idx": {"module_program_interface_instantiation": [[3195, 3367]], "continuous_assign": [[2195, 2252], [2941, 3008], [3047, 3066], [3069, 3088], [4352, 4712]], "blocking_assignment": [], "nonblocking_assignment": [[1791, 1841], [1864, 1874], [1890, 1907], [1982, 2032], [2076, 2086], [2106, 2123], [6136, 6149], [6175, 6198]], "case_statement": [], "conditional_statement": [[1846, 1907], [2037, 2123], [2055, 2123], [6112, 6206]], "always_construct": [[1757, 1913], [1948, 2129], [6078, 6212]], "parameter_declaration": [[637, 697], [700, 771], [774, 847], [850, 907], [934, 993], [996, 1051], [1054, 1112], [1115, 1172], [1198, 1246], [1249, 1310], [1313, 1383], [1386, 1435], [1438, 1500], [1503, 1573]], "ansi_port_declaration": [[379, 429], [384, 429], [391, 429], [398, 429], [405, 429], [417, 429], [423, 429], [2295, 2342], [2345, 2393], [2396, 2442], [2445, 2492], [2495, 2575], [2578, 2666], [2669, 2705], [2708, 2761]]}}
{"sample_i": "shadow1229-tt07-vga-player", "topmodule": "tt_um_shadow1229_vga_player", "code": "`default_nettype none\nmodule tt_um_shadow1229_vga_player (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n    );\n    \n    wire hsync;\n    wire vsync;\n    reg [3:0] spi_uio_out; //wire ->reg is this right?\n    wire [5:0] rrggbb;\n    wire [5:0] color_on;\n    wire [5:0] color_off;    \n\n\n    /*ui_in\n    0: 74880Hz 1-bit PCM(0) / 9360Hz 8-bit PWM(1)\n    1: Tiny VGA(0) / VGA clock PMOD(1)\n    2: color_off(0) - R\n    3: color_off(0) - G\n    4: color_off(0) - B\n    5: color_on(1)  - R\n    6: color_on(1)  - G\n    7: color_on(1)  - B\n\n    // https://github.com/mole99/tiny-vga\n    // https://github.com/TinyTapeout/tt-vga-clock-pmod\n    */\n    assign color_on[5:0]  = {ui_in[5], ui_in[5], ui_in[6], ui_in[6], ui_in[7], ui_in[7]}; \n    assign color_off[5:0] = {ui_in[2], ui_in[2], ui_in[3], ui_in[3], ui_in[4], ui_in[4]}; \n    assign uo_out[0] = ui_in[1] ? hsync_q   :rrggbb[5];\n    assign uo_out[1] = ui_in[1] ? vsync_q   :rrggbb[3];\n    assign uo_out[2] = ui_in[1] ? rrggbb[0] :rrggbb[1];\n    assign uo_out[3] = ui_in[1] ? rrggbb[1] :vsync_q;\n    assign uo_out[4] = ui_in[1] ? rrggbb[2] :rrggbb[4];\n    assign uo_out[5] = ui_in[1] ? rrggbb[3] :rrggbb[2];\n    assign uo_out[6] = ui_in[1] ? rrggbb[4] :rrggbb[0];\n    assign uo_out[7] = ui_in[1] ? rrggbb[5] :hsync_q;\n    \n    assign uio_out = ui_in[0] ? {spi_sel,spi_clk,spi_uio_out[3:0],sound_p_pwm,sound_n_pwm}: {spi_sel,spi_clk,spi_uio_out[3:0],sound_p_pcm,sound_n_pcm};\n    assign uio_oe = rst_n ? {2'b11,spi_oe[3:0] ,2'b11} : 8'b11000000;  \n\n    //PWM modulation: LTC2644\n    //W25Q128JVSSIQ address: FFFFFF https://www.adafruit.com/product/5634\n    wire reset = ~rst_n;\n\n    reg [127:0] cache_row; //10Byte for line / 3x2 byte for sound\n    reg [127:0] data_row;\n    reg cache_done;\n    reg data_done;\n\n    wire [9:0] x_px;          // X position for actual pixel.\n    wire [9:0] y_px;          // Y position for actual pixel.\n    wire [9:0] vc;          // vertical counter (0 ~480+40-1)\n    //wire [9:0] hc;          // horizontal counter (0 ~ 640+192-1) (52*16-1)\n    // blocks are 16 x 16 px. (40 x 30 -> 640 x 480)\n    /* verilator lint_off WIDTH */\n    wire [6:0] x_block = (x_px) >> 3;\n    wire [6:0] v_block = (vc) >> 3;\n    /* verilator lint_on WIDTH */\n    wire activevideo;    \n    reg [1:0]frame_iter; //24fps - show same frame for three times\n    reg [15:0] n_frame;\n    //reg [6:0] x_block_q; //to match up signals using x_block_q\n    reg [6:0] v_block_q;\n    reg hsync_q;\n    reg vsync_q;\n    reg activevideo_q;\n    //reg draw;\n    reg overflow;\n\n    wire px_clk;\n    wire spi_clk;\n    reg [7:0] read_cmd = 8'b01101011; //Fast Read Quad Output (6Bh, MSB -> LSB, read at rising clk of spi_clk. = falling clk of px_clk)\n    wire spi_sel;\n    assign px_clk = clk;\n    assign spi_clk = ~clk && spi_clk_on;\n    assign spi_sel = ~spi_sel_on;   \n    reg  [3:0] spi_oe;\n    reg spi_sel_on;\n    reg spi_clk_on;\n    reg spi_cmd_on;\n    reg spi_addr_on;\n    reg spi_dummy_on;\n    reg spi_read_on;\n    reg [3:0] spi_cmd_n;\n    reg [6:0] spi_addr_n;\n    reg [3:0] spi_dummy_n;\n    reg [5:0] spi_read_n;\n    reg [23:0] addr; // this addr tells byte address, not bit address! keep in mind that\n\n    //sound\n    reg  [15:0] sound_reg;\n    //PCM\n    reg  [3:0] sound_block_pcm; //+1 (x_px = 223 / 639 (+1 each 8*52 clocks))/ resets at next data\n    reg        pcm_0_aux; //auxilliary register for pcm sound, used at sound_block updating clock\n    reg sound_p_pcm;\n    reg sound_n_pcm;\n    //PWM\n    reg [7:0] counter_pwm; //+1 per each clk\n    reg [7:0] threshold_pwm;\n    reg sound_p_pwm;\n    reg sound_n_pwm;\n\n    VgaSyncGen vga_0 (.data_done(data_done), .px_clk(px_clk), .hsync(hsync), .vsync(vsync), .x_px(x_px), .y_px(y_px),.vc(vc), .activevideo(activevideo), .reset(reset));\n    assign rrggbb = activevideo_q &&  data_row[79 - x_block] ? color_on : color_off; \n \n    always @(posedge px_clk) begin\n        //$display(\"x_px %d %b | y_px %d %b | hsync %d | vsync %d | activevideo %d | cache_done %d | data_done %d\", x_px, x_px, y_px, y_px, hsync, vsync, activevideo, cache_done, data_done);\n        if(reset || overflow == 1) begin\n\n            cache_row <= 0;\n            data_row <= 0;\n            cache_done <= 0;\n            data_done <= 0;\n\n            frame_iter <= 0;\n            n_frame <= 0;\n            //x_block_q <= 0;\n            v_block_q <= 0;\n            hsync_q <= 1;\n            vsync_q <= 1;\n            activevideo_q <= 0;\n            //draw <= 0;\n            overflow <= 0;\n\n            spi_oe <= 0;\n            spi_sel_on <= 0;\n            spi_clk_on <= 0;\n            spi_cmd_on <= 0;\n            spi_addr_on <= 0;\n            spi_dummy_on <= 0;\n            spi_read_on <= 0;\n            spi_cmd_n <= 0;\n            spi_addr_n <= 0;\n            spi_dummy_n <= 0;\n            spi_read_n <= 0;\n            addr <= 0;\n\n            sound_reg <= 0;\n            sound_block_pcm <= 0;\n            pcm_0_aux <= 0;\n            sound_p_pcm <=0;\n            sound_n_pcm <= 1;    \n            counter_pwm <= 0; //+1 per each clk\n            threshold_pwm <= 0;\n            sound_p_pwm <=0;\n            sound_n_pwm <= 1; \n\t\t\tspi_uio_out <= 0;\n        end\n\n\n        //SPI flash module\n        if (cache_done == 0) begin\n\n            if (spi_sel_on == 0) begin\n                spi_sel_on <= 1'b1;\n                \n            end else begin\n                if (spi_clk_on == 0 && spi_cmd_on == 0 && spi_addr_on == 0 && spi_dummy_on == 0 && spi_read_on == 0 ) begin\n                    //$display(\"x_px %d %b | y_px %d %b | hsync %d | vsync %d | activevideo %d | cache_done %d | data_done %d\", x_px, x_px, y_px, y_px, hsync, vsync, activevideo, cache_done, data_done);\n\n                    //spi_clk_on <= 1'b1;\n                    spi_oe[0] <= 1'b1;\n                    spi_cmd_on <= 1'b1;\n                    spi_cmd_n <= 0;\n                    cache_row <= 0;\n\n                end else if (spi_cmd_on == 1 && spi_addr_on == 0 && spi_dummy_on == 0 && spi_read_on == 0 ) begin\n                    spi_clk_on <= 1'b1; //cmd and clk should work simultaneously\n                    \n                    spi_uio_out[0] <= read_cmd[7-spi_cmd_n];\n                    spi_uio_out[1] <= 0;\n                    spi_uio_out[2] <= 0;\n                    spi_uio_out[3] <= 0;\n                    //$display(\"cmd is %d | %b\", spi_cmd_n, read_cmd[7-spi_cmd_n]); //01101011. works fine         //read_cmd = 8'b01101011\n                    spi_cmd_n <= spi_cmd_n + 1;\n\n                    if (spi_cmd_n == 7) begin\n                        spi_cmd_on <= 0;\n                        spi_addr_on <= 1;\n                        spi_addr_n <= 0;\n                        if (frame_iter <2 && v_block_q == 64) begin \n                            //bit_addr <= n_frame * 128*65 + v_block_q*128 + data_done*128 - 8320; \n                            addr <= n_frame * 16*65 + v_block_q*16 + data_done*16 - 1040;\n                        end else begin \n                            //bit_addr <= n_frame * 128*65 + v_block_q*128 + data_done*128 ;\n                            addr <= n_frame * 16*65 + v_block_q*16 + data_done*16;\n                        end\n                        //$display(\"n_frame %d | frame_iter %d | y_px %d %b | v_block_q %d %b | addr%d\",n_frame, frame_iter, y_px, y_px, v_block_q, v_block_q, addr); //01101011. works fine         //read_cmd = 8'b01101011\n                    end\n                end else if (spi_clk_on == 1 && spi_cmd_on == 0 && spi_addr_on == 1 && spi_dummy_on == 0 && spi_read_on == 0 ) begin\n                    spi_uio_out[0] <= addr[23-spi_addr_n];\n                    spi_uio_out[1] <= 0;\n                    spi_uio_out[2] <= 0;\n                    spi_uio_out[3] <= 0;\n                    //$display(\"addr is %d | %d | %b | %b\", spi_addr_n, addr, addr, addr[23-spi_addr_n]); //01101011. works fine         //read_cmd = 8'b01101011\n                    spi_addr_n <= spi_addr_n + 1;\n\n                    if (spi_addr_n == 23) begin\n                        //$display(\"addr is %d | %d | %b | %b\", spi_addr_n, addr, addr, addr[23-spi_addr_n]); //01101011. works fine         //read_cmd = 8'b01101011\n\n                        spi_addr_on <= 0;\n                        spi_dummy_on <= 1;\n                        spi_dummy_n <= 0;\n                    end\n                end else if (spi_clk_on == 1 && spi_cmd_on == 0 && spi_addr_on == 0 && spi_dummy_on == 1 && spi_read_on == 0 ) begin\n                    spi_oe[0] <= 1'b0;\n\n                    //$display(\"dummy_n is %d \", spi_dummy_n); //01101011. works fine         //read_cmd = 8'b01101011\n                    spi_dummy_n <= spi_dummy_n + 1;\n                    //$display(\"veri dummy_n %d\", spi_dummy_n);\n\n                    if (spi_dummy_n == 7) begin\n                        spi_dummy_on <= 0;\n                        spi_read_on <= 1;\n                        spi_read_n <= 0;\n                        //$display(\"veri dummy_n last\");\n                    end\n                end else if (spi_clk_on == 1 && spi_cmd_on == 0 && spi_addr_on == 0 && spi_dummy_on == 0 && spi_read_on == 1 ) begin\n                    //1 clk delay in uio_in\n                    //$display(\"read_n %d %b\", spi_read_n,uio_in[5:2]);\n                    if (spi_read_n > 0 && spi_read_n <= 32) begin\n                        cache_row <= {cache_row[123:0], uio_in[5:2]};\n                    end\n                    \n                    if (spi_read_n == 32) begin\n                        spi_read_on <= 0;\n                        cache_done <= 1;\n                        //$display(\"read end cache_row  : %b\", cache_row);\n                        //$display(\"read end data_row   : %b\\n\", data_row);\n                    end\n\n                    spi_read_n <= spi_read_n + 1;\n                    \n                    //$display(\"read_n is %d \", spi_read_n); //01101011. works fine         //read_cmd = 8'b01101011\n                    //$display(\"spi_uio_in: %b %b\", uio_in, uio_in[5:2]);\n                    //$display(\"cache_row: %b\\n\", cache_row);\n                    \n                end\n            end\n        end else begin\n            if (spi_clk_on == 1 && spi_cmd_on == 0 && spi_addr_on == 0 && spi_dummy_on == 0 && spi_read_on == 0) begin\n                spi_clk_on <= 0;\n                spi_sel_on <= 0;\n\n                //$display(\"spi_sel_off\");\n            end\n        end\n        //SPI flash module end\n\n        //happens only once, at the first time\n        if(data_done == 1'b0 && cache_done == 1'b1) begin\n            data_done <= 1'b1;\n            cache_done <= 1'b0;\n            data_row[127:0] <= cache_row[127:0];\n        end\n\n        //cache to data\n        //x_block_q <= x_block; //is this correct? using reg here\n        v_block_q <= v_block;\n        hsync_q <= hsync;\n        vsync_q <= vsync;\n        activevideo_q <= activevideo;  \n        //$display(\"  n_frame %d frame_iter %d x_px %d y_px %d sound_reg %b sound_block_pcm %d sound_reg[15-sound_block_pcm] %b sound_p_pcm %b\", n_frame, frame_iter, x_px, y_px, sound_reg, sound_block_pcm, sound_reg, sound_p_pcm);     \n        //$display(\"data_row: %b\", data_row);        \n       \n        if (x_px == 639 && y_px%8 == 7 && cache_done == 1'b1) begin //right before the sound_reg update, used for pcm\n            case (frame_iter)\n                0: begin\n                    pcm_0_aux <= cache_row[127];\n                end\n                1: begin\n                    pcm_0_aux <= cache_row[111];\n                end\n                2: begin\n                    pcm_0_aux <=  cache_row[95];\n                end\n            endcase\n            //$display(\"  n_frame %d frame_iter %d x_px %d y_px %d sound_reg %b sound_block_pcm %d sound_reg[15-sound_block_pcm] %b sound_p_pcm %b\", n_frame, frame_iter, x_px, y_px, sound_reg, sound_block_pcm, sound_reg, sound_p_pcm);     \n    \n        end\n        //update sound and video data        \n        if (x_px == 832 && y_px%8 == 0 && cache_done == 1'b1) begin\n            cache_done <= 1'b0;\n            data_row[127:0] <= cache_row[127:0]; // video update\n            sound_block_pcm <= 0;\n            //sound_block_pwm <= 0;\n            case (frame_iter)\n                0: begin\n                    sound_reg[15:0] <= cache_row[127:112];\n                    threshold_pwm[7:0] <= cache_row[127:120]; \n                end\n                1: begin\n                    sound_reg[15:0] <= cache_row[111:96];\n                    threshold_pwm[7:0] <= cache_row[111:104]; \n                end\n                2: begin\n                    sound_reg[15:0] <= cache_row[95:80];\n                    threshold_pwm[7:0] <= cache_row[95:88]; \n                end\n            endcase\n            sound_p_pcm <= pcm_0_aux; \n            sound_n_pcm <= ~pcm_0_aux;             \n            //$display(\"x_px %d %b | y_px %d %b | hsync %d | vsync %d | activevideo %d | cache_done %d | data_done %d\", x_px, x_px, y_px, y_px, hsync, vsync, activevideo, cache_done, data_done);\n            //$display(\"cache->data\"); //01101011. works fine         //read_cmd = 8'b01101011\n            //$display(\"cache2data cache_row: %b\", cache_row);\n            //$display(\"cache2data data_row:  %b\\n\", data_row);\n            //$display(\"  n_frame %d frame_iter %d x_px %d y_px %d sound_reg %b sound_block_pcm %d sound_reg[15-sound_block_pcm] %b sound_p_pcm %b\", n_frame, frame_iter, x_px, y_px, sound_reg, sound_block_pcm, sound_reg, sound_p_pcm);     \n\n        end else begin\n            sound_p_pcm <= sound_reg[15-sound_block_pcm]; \n            sound_n_pcm <= ~sound_reg[15-sound_block_pcm]; \n        end\n\n        if (x_px == 832 && y_px%8 == 4) begin\n            threshold_pwm[7:0] <= sound_reg[7:0];\n        end\n\n        \n        //PCM update\n        if (x_px == 223) begin\n            sound_block_pcm <= sound_block_pcm + 1;\n        end\n        if (x_px == 639) begin\n            sound_block_pcm <= sound_block_pcm + 1;\n        end\n\n\n     \n        //PWM update (y 4px / each 256 clk)\n        counter_pwm <= counter_pwm + 1;\n        if (counter_pwm[7:0] < threshold_pwm[7:0] ) begin\n            sound_p_pwm <= 1;\n            sound_n_pwm <= 0;\n        end else begin\n            sound_p_pwm <= 0;\n            sound_n_pwm <= 1;\n        end\n        //update frame_iter\n        //1. frame_iter_need_update becomes 1 at y_px = -40 \n        // 480 - 1   /  -192 mod 1024\n        if (y_px == 479 && x_px == 832 ) begin\n            frame_iter <= frame_iter + 1'b1;\n        end\n\n        //72Hz -> 24 fps\n        if(y_px == 479 && x_px == 833 && frame_iter == 2'b11) begin\n            n_frame <= n_frame + 1'b1;\n            frame_iter <= 2'b00;\n        end\n\n        if(y_px == 479 && x_px == 834 && n_frame == 16131) begin\n            overflow <= 1; //(2^24 byte / 1040 byte per frame = 16131.9384615 -> overflow happens at 16131th frame)\n        end\n  \n    end\n\nendmodule\n\n\n\n`default_nettype none\n//////////////////////////////////////////////////////////////////////////////////\n// Company: Ridotech\n// Engineer: Juan Manuel Rico\n// \n// Create Date:    09:34:23 30/09/2017 \n// Module Name:    vga_controller\n// Description:    Basic control for 640x480@72Hz VGA signal.\n//\n// Dependencies: \n//\n// Revision: \n// Revision 0.01 - File Created for Roland Coeurjoly (RCoeurjoly) in 640x480@85Hz.\n// Revision 0.02 - Change for 640x480@60Hz.\n// Revision 0.03 - Solved some mistakes.\n// Revision 0.04 - Change for 640x480@72Hz and output signals 'activevideo'\n//                 and 'px_clk'.\n//\n// Additional Comments: \n//\n//////////////////////////////////////////////////////////////////////////////////\nmodule VgaSyncGen (\n            input wire        data_done,        // Input clock: 31.5MHz\n            input wire       px_clk,        // Input clock: 31.5MHz\n            input wire       reset,         // reset\n            output wire      hsync,         // Horizontal sync out\n            output wire      vsync,         // Vertical sync out\n            output reg [9:0] x_px,          // X position for actual pixel.\n            output reg [9:0] y_px,          // Y position for actual pixel.\n            output reg [9:0] vc,          //Y(vertical) counter.\n            output wire      activevideo\n         );\n\n    /*\n    http://www.epanorama.net/faq/vga2rgb/calc.html\n    [*User-Defined_mode,(640X480)]\n    PIXEL_CLK   =   31500\n    H_DISP      =   640\n    V_DISP      =   480\n    H_FPORCH    =   24\n    H_SYNC      =   40\n    H_BPORCH    =   128\n    V_FPORCH    =   9\n    V_SYNC      =   3\n    V_BPORCH    =   28\n    */\n\n    // Video structure constants.\n    parameter activeHvideo = 640;               // Width of visible pixels.\n    parameter activeVvideo =  480;              // Height of visible lines.\n    parameter hfp = 24;                         // Horizontal front porch length.\n    parameter hpulse = 40;                      // Hsync pulse length.\n    parameter hbp = 128;                        // Horizontal back porch length.\n    parameter vfp = 9;                          // Vertical front porch length.\n    parameter vpulse = 3;                       // Vsync pulse length.\n    parameter vbp = 28;                         // Vertical back porch length.\n    parameter blackH = hfp + hpulse + hbp;      // Hide pixels in one line.\n    parameter blackV = vfp + vpulse + vbp;      // Hide lines in one frame.\n    parameter hpixels = blackH + activeHvideo;  // Total horizontal pixels.\n    parameter vlines = blackV + activeVvideo;   // Total lines.\n\n    // Registers for storing the horizontal & vertical counters.\n    \n    reg [9:0] hc;\n    //reg [9:0] vc;\n\n    // Counting pixels.\n    always @(posedge px_clk)\n    begin\n        if(reset) begin\n            hc <= 0;\n            vc <= 0;\n        end if(data_done == 1'b1) begin\n            // Keep counting until the end of the line.\n            if (hc < hpixels - 1)\n                hc <= hc + 1;\n            else\n            // When we hit the end of the line, reset the horizontal\n            // counter and increment the vertical counter.\n            // If vertical counter is at the end of the frame, then\n            // reset that one too.\n            begin\n                hc <= 0;\n                if (vc < vlines - 1)\n                vc <= vc + 1;\n            else\n               vc <= 0;\n            end\n        end\n     end\n\n    // Generate sync pulses (active low) and active video.\n    assign hsync = (hc >= hfp && hc < hfp + hpulse) ? 0:1; \n    assign vsync = (vc >= vfp && vc < vfp + vpulse) ? 0:1; \n    assign activevideo = (hc >= blackH && vc >= blackV) ? 1:0;\n\n    // Generate color.\n    always @(posedge px_clk)\n    begin\n        if(reset) begin\n            x_px <= 0;\n            y_px <= 0;\n        end if(data_done == 1'b1) begin\n            x_px <= hc - blackH;\n            y_px <= vc - blackV;\n        end\n     end\n endmodule\n`default_nettype wire\n", "mask_idx": {"conditional_statement": [[10813, 10986], [6287, 10429], [18499, 18590], [18140, 18606], [9093, 9327]], "module_program_interface_instantiation": [[4003, 4167]], "always_construct": [[4260, 15183], [18899, 19130], [17931, 18627]], "case_statement": [[11628, 11947], [12498, 13031]], "ansi_port_declaration": [[168, 214], [16497, 16525], [16356, 16419]], "continuous_assign": [[18752, 18807], [18812, 18870], [3210, 3242]], "parameter_declaration": [[17123, 17189], [17505, 17576], [17426, 17500], [16889, 16960], [17733, 17792], [16965, 17036], [17355, 17421]], "nonblocking_assignment": [[4649, 4665], [12728, 12765], [10938, 10974], [6559, 6579]]}, "all_mask_idx": {"module_program_interface_instantiation": [[4003, 4167]], "continuous_assign": [[1078, 1164], [1169, 1255], [1260, 1311], [1316, 1367], [1372, 1423], [1428, 1477], [1482, 1533], [1538, 1589], [1594, 1645], [1650, 1699], [1709, 1856], [1861, 1928], [3144, 3164], [3169, 3205], [3210, 3242], [4172, 4253], [18692, 18747], [18752, 18807], [18812, 18870]], "blocking_assignment": [], "nonblocking_assignment": [[4536, 4551], [4564, 4578], [4591, 4607], [4620, 4635], [4649, 4665], [4678, 4691], [4734, 4749], [4762, 4775], [4788, 4801], [4814, 4833], [4871, 4885], [4899, 4911], [4924, 4940], [4953, 4969], [4982, 4998], [5011, 5028], [5041, 5059], [5072, 5089], [5102, 5117], [5130, 5146], [5159, 5176], [5189, 5205], [5218, 5228], [5242, 5257], [5270, 5291], [5304, 5319], [5332, 5348], [5361, 5382], [5395, 5430], [5443, 5462], [5475, 5491], [5504, 5522], [5526, 5543], [5676, 5695], [6130, 6148], [6169, 6188], [6209, 6224], [6245, 6260], [6396, 6456], [6498, 6538], [6559, 6579], [6600, 6620], [6641, 6661], [6822, 6849], [6921, 6937], [6962, 6979], [7004, 7020], [7218, 7279], [7441, 7495], [7923, 7961], [7982, 8002], [8023, 8043], [8064, 8084], [8267, 8296], [8537, 8554], [8579, 8597], [8622, 8639], [8817, 8835], [8976, 9007], [9145, 9163], [9188, 9205], [9230, 9246], [9667, 9712], [9830, 9847], [9872, 9888], [10085, 10114], [10604, 10620], [10637, 10653], [10875, 10893], [10906, 10925], [10938, 10974], [11086, 11107], [11116, 11133], [11142, 11159], [11168, 11199], [11691, 11719], [11785, 11813], [11879, 11907], [12331, 12350], [12363, 12415], [12428, 12449], [12561, 12599], [12620, 12662], [12728, 12765], [12786, 12828], [12894, 12930], [12951, 12991], [13044, 13070], [13083, 13122], [13816, 13862], [13875, 13922], [13994, 14031], [14118, 14157], [14213, 14252], [14325, 14356], [14427, 14444], [14457, 14474], [14510, 14527], [14540, 14557], [14756, 14788], [14907, 14933], [14946, 14966], [15057, 15160], [18002, 18010], [18023, 18031], [18178, 18191], [18474, 18482], [18536, 18549], [18582, 18590], [18970, 18980], [18993, 19003], [19056, 19076], [19089, 19109]], "case_statement": [[11628, 11947], [12498, 13031]], "conditional_statement": [[4490, 5555], [5593, 10725], [5633, 10445], [5756, 10429], [6287, 10429], [6871, 7769], [7045, 7523], [7795, 10429], [8318, 8663], [8689, 10429], [9093, 9327], [9353, 10429], [9597, 9736], [9778, 10063], [10481, 10713], [10813, 10986], [11506, 12204], [12259, 13934], [13944, 14043], [14083, 14169], [14178, 14264], [14365, 14569], [14705, 14800], [14835, 14978], [14988, 15172], [17974, 18071], [18044, 18618], [18140, 18606], [18499, 18590], [18942, 19043], [19016, 19121]], "always_construct": [[4260, 15183], [17931, 18627], [18899, 19130]], "parameter_declaration": [[16889, 16960], [16965, 17036], [17041, 17118], [17123, 17189], [17194, 17270], [17275, 17350], [17355, 17421], [17426, 17500], [17505, 17576], [17581, 17652], [17657, 17728], [17733, 17792]], "ansi_port_declaration": [[63, 110], [115, 163], [168, 214], [219, 266], [271, 351], [356, 444], [449, 485], [490, 543], [15955, 16014], [16027, 16082], [16095, 16135], [16148, 16202], [16215, 16267], [16280, 16343], [16356, 16419], [16432, 16484], [16497, 16525]]}}
{"sample_i": "shivam7086-tt07-verilog-RO_PUF", "topmodule": "tt_um_PUF", "code": "\n/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_PUF (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  // All output pins must be assigned. If not used, assign to 0.\n  // assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in\n  assign uio_out = 0;\n  assign uio_oe  = 0;\n\n  // List all unused inputs to prevent warnings\n  // wire _unused = &{ena, clk, rst_n, 1'b0};\n\n// module top (output [7:0] response, input en, reset, input [9:0] challenge);\n    wire [7:0] count1, count2;\n    top_f2g uut1(count1, ena,  rst_n, ui_in[4:0]);\n    top_f2g uut2(count2, ena,  rst_n, ui_in[4:0]);\ncomp uut3(count1, count2, uo_out);\nendmodule\n\nmodule f2g (output p, q, r, input a, b, c);\nassign p=a;\nassign q=a^b;\nassign r=a^c;   \nendmodule\n\nmodule osc_f2g (output out, input ena);\nwire [4:0] p, q, r;\nwire A;\nf2g g0(p[0], q[0], r[0], A, 1'b1, 1'b1);\nf2g g1(p[1], q[1], r[1], r[0], 1'b1, 1'b1);\nf2g g2(p[2], q[2], r[2], q[1], 1'b1, 1'b1);\nf2g g3(p[3], q[3], r[3], r[2], 1'b1, 1'b1);\nf2g g4(p[4], q[4], r[4], q[3], 1'b1, 1'b1);\nand a0(out, ena, r[4]);\nassign A=out;\nendmodule\n\nmodule top_f2g (output [7:0] count, input ena,  rst_n, input [4:0] ui_in);\nwire [31:0] i;\nwire mux_out;\ngenvar x;\ngenerate\n    for(x=0; x<32; x=x+1)\n    begin\n        (* S= \"TRUE\"*)(* ALLOW_COMBINATORIAL_LOOPS = \"true\", KEEP = \"true\" *)\n        osc_f2g f0(i[x], ena);\n    end\nendgenerate\n\nmux32 uut(i, ui_in, mux_out);\n\ncounter c(mux_out,  rst_n, count);   \nendmodule\n\n\nmodule mux32(\n    input wire[32:1] i,\n    input wire[4:0] ui_in,\n    output reg m_out\n    );\n    \n    (* S= \"TRUE\"*)(* ALLOW_COMBINATORIAL_LOOPS = \"true\", KEEP = \"true\" *)\n    always @(*)\n\n    begin\n    case(ui_in)\n        5'b00000: m_out=i[1];\n        5'b00001: m_out=i[2];\n        5'b00010: m_out=i[3];\n        5'b00011: m_out=i[4];\n        5'b00100: m_out=i[5];\n        5'b00101: m_out=i[6];\n        5'b00110: m_out=i[7];\n        5'b00111: m_out=i[8];\n        5'b01000: m_out=i[9];\n        5'b01001: m_out=i[10];\n        5'b01010: m_out=i[11];\n        5'b01011: m_out=i[12];\n        5'b01100: m_out=i[13];\n        5'b01101: m_out=i[14];\n        5'b01110: m_out=i[15];\n        5'b01111: m_out=i[16];\n        5'b10000: m_out=i[17];\n        5'b10001: m_out=i[18];\n        5'b10010: m_out=i[19];\n        5'b10011: m_out=i[20];\n        5'b10100: m_out=i[21];\n        5'b10101: m_out=i[22];\n        5'b10110: m_out=i[23];\n        5'b10111: m_out=i[24];\n        5'b11000: m_out=i[25];\n        5'b11001: m_out=i[26];\n        5'b11010: m_out=i[27];\n        5'b11011: m_out=i[28];\n        5'b11100: m_out=i[29];\n        5'b11101: m_out=i[30];\n        5'b11110: m_out=i[31];\n        5'b11111: m_out=i[32];\n    endcase   \n    end\nendmodule\n\nmodule counter(\n    input m_out,\n    input  rst_n,\n    output reg[7:0] count\n    );\n    \n    (* S= \"TRUE\"*)(* ALLOW_COMBINATORIAL_LOOPS = \"true\", KEEP = \"true\" *)\n    initial count=8'h00;\n    always @(posedge m_out or posedge  rst_n)\n    begin\n        if( rst_n)\n            begin\n                count = 0;\n            end\n        else\n            begin\n                count = count + 1;\n            end\n    end\nendmodule\n\nmodule comp(\n    input [7:0] count1,\n    input [7:0] count2,\n    output reg[7:0] uo_out\n    );\n    \n    (* S= \"TRUE\"*)(* ALLOW_COMBINATORIAL_LOOPS = \"true\", KEEP = \"true\" *)\n    \n    always @(count1 or count2)\n        begin\n            if(&count1 > &count2)\n                begin\n                    uo_out <= count1;\n                end\n            else\n                begin\n                    uo_out <= count2;\n                end\n        end\nendmodule\n", "mask_idx": {"conditional_statement": [[3858, 4056]], "blocking_assignment": [[2561, 2573], [2378, 2389], [2438, 2449], [2840, 2852], [2902, 2914], [2933, 2945], [2685, 2697]], "module_program_interface_instantiation": [[1370, 1413], [1117, 1151], [1840, 1862], [1414, 1457]], "always_construct": [[2141, 3185], [3805, 4068]], "ansi_port_declaration": [[1185, 1206], [2034, 2050], [1611, 1669]], "continuous_assign": [[1570, 1583], [789, 808], [1207, 1218]], "nonblocking_assignment": [[4019, 4036]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1019, 1065], [1070, 1116], [1117, 1151], [1329, 1369], [1370, 1413], [1414, 1457], [1458, 1501], [1502, 1545], [1840, 1862], [1884, 1913], [1915, 1952]], "continuous_assign": [[767, 786], [789, 808], [1207, 1218], [1219, 1232], [1233, 1249], [1570, 1583]], "blocking_assignment": [[2198, 2209], [2228, 2239], [2258, 2269], [2288, 2299], [2318, 2329], [2348, 2359], [2378, 2389], [2408, 2419], [2438, 2449], [2468, 2480], [2499, 2511], [2530, 2542], [2561, 2573], [2592, 2604], [2623, 2635], [2654, 2666], [2685, 2697], [2716, 2728], [2747, 2759], [2778, 2790], [2809, 2821], [2840, 2852], [2871, 2883], [2902, 2914], [2933, 2945], [2964, 2976], [2995, 3007], [3026, 3038], [3057, 3069], [3088, 3100], [3119, 3131], [3150, 3162], [3372, 3384], [3494, 3504], [3568, 3586]], "nonblocking_assignment": [[3922, 3939], [4019, 4036]], "case_statement": [[2168, 3177]], "conditional_statement": [[3449, 3602], [3858, 4056]], "always_construct": [[2141, 3185], [3389, 3610], [3805, 4068]], "parameter_declaration": [], "ansi_port_declaration": [[126, 173], [178, 226], [231, 277], [282, 329], [334, 414], [419, 507], [512, 548], [553, 606], [1175, 1206], [1185, 1206], [1188, 1206], [1191, 1206], [1200, 1206], [1203, 1206], [1277, 1300], [1289, 1300], [1611, 1669], [1631, 1669], [1643, 1669], [1650, 1669], [1983, 2002], [2007, 2029], [2034, 2050], [3217, 3229], [3234, 3247], [3252, 3273], [3639, 3658], [3663, 3682], [3687, 3709]]}}
{"sample_i": "sreeramtirumalasetty-major", "topmodule": "tt_um_multiplier_mbm", "code": "/*\n * Copyright (c) 2024 Your Name\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\n\n\nmodule tt_um_multiplier_mbm (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\nassign uio_oe=0;\n\n\n\n\nwire [7:0]mcand,mlier;\nwire [15:0]ans;\nlatchh lat1(ui_in,clk,mcand);\nlatchh lat2(uio_in,clk,mlier);\n\nwire [22:1]s;\nwire [21:1]c;\n\nwire [7:0]two_compl;\nassign two_compl=~mcand+1;\n\nreg [15:0]p0;\nreg [13:0]p1;\nreg [11:0]p2;\nreg [9:0]p3;\n \nwire [4:0]x1,x2,x3,x4;\n//partial 1\n booth_encoding cod1(mlier[1],mlier[0],1'b0,x1[4],x1[3],x1[2],x1[1],x1[0]);\n always @( * )\n        begin\n          p0=16'd0;\n          case (x1)\n              5'b10000: p0=16'd0;\n              5'b01000: p0={{8{mcand[7]}},mcand};\n              5'b00100: p0={{8{two_compl[7]}},two_compl};\n              5'b00010: p0={{7{mcand[7]}},mcand,1'b0};\n              5'b00001: \n              begin\n                p0={{7{two_compl[7]}},two_compl,1'b0};\n               end\n              default: p0=16'd0;\n          endcase\n      end   \n\n//partial 2\n    \n    booth_encoding cod2(mlier[3],mlier[2],mlier[1],x2[4],x2[3],x2[2],x2[1],x2[0]);\n always @( * )\n        begin\n          p1=14'd0;\n          case (x2)\n              5'b10000: p1=14'd0;\n              5'b01000: p1={{6{mcand[7]}},mcand};\n              5'b00100: p1={{6{two_compl[7]}},two_compl};\n              5'b00010: p1={{5{mcand[7]}},mcand,1'd0};\n              5'b00001: \n              begin\n                p1={{5{two_compl[7]}},two_compl,1'd0};\n               end\n              default: p1=14'd0;\n          endcase\n      end \n      \n //partial 3\n booth_encoding cod3(mlier[5],mlier[4],mlier[3],x3[4],x3[3],x3[2],x3[1],x3[0]);\n always @( * )\n        begin\n          p2=12'd0;\n          case (x3)\n              5'b10000: p2=12'd0;\n              5'b01000: p2={{4{mcand[7]}},mcand};\n              5'b00100: p2={{4{two_compl[7]}},two_compl};\n              5'b00010: p2={{3{mcand[7]}},mcand,1'd0};\n              5'b00001: \n              begin\n                p2={{3{two_compl[7]}},two_compl,1'd0};\n               end\n              default: p2=12'd0;\n          endcase\n      end \n \n//partial 4\nbooth_encoding cod4(mlier[7],mlier[6],mlier[5],x4[4],x4[3],x4[2],x4[1],x4[0]);\nalways @( * )\n        begin\n          p3=10'd0;\n          case (x4)\n              5'b10000: p3=10'd0;\n              5'b01000: p3={{2{mcand[7]}},mcand};\n              5'b00100: p3={{2{two_compl[7]}},two_compl};\n              5'b00010: p3={{1{mcand[7]}},mcand,1'd0};\n              5'b00001: \n              begin\n                p3={{1{two_compl[7]}},two_compl,1'd0};\n               end\n              default: p3=10'd0;\n          endcase\n      end \n\n//1st reduction 4 to 3\nassign s[1]=p2[2] ^ p3[0];\nassign c[1]=p2[2] & p3[0];\n\nassign s[2]=(p1[5] ^p2[3]) ^ p3[1];\nassign c[2]= (p1[5] & p2[3]) | (p2[3] & p3[1]) | (p3[1] & p1[5]);\n\nassign s[3]=( p1[6] ^p2[4] ) ^ p3[2];\nassign c[3]= (p1[6] & p2[4]) | (p2[4] & p3[2]) | (p3[2] & p1[6]);\n\nassign s[4]=( p1[7] ^p2[5] ) ^ p3[3];\nassign c[4]= (p1[7] & p2[5]) | (p2[5] & p3[3]) | (p3[3] & p1[7]);\n\nassign s[5]=( p1[8] ^p2[6] ) ^ p3[4];\nassign c[5]= (p1[8] & p2[6]) | (p2[6] & p3[4]) | (p3[4] & p1[8]);\n\nassign s[6]=( p1[9] ^p2[7] ) ^ p3[5];\nassign c[6]= (p1[9] & p2[7]) | (p2[7] & p3[5]) | (p3[5] & p1[9]);\n\nassign s[7]=( p1[10] ^p2[8] ) ^ p3[6];\nassign c[7]= (p1[10] & p2[8]) | (p2[8] & p3[6]) | (p3[6] & p1[10]);\n\nassign s[8]=( p1[11] ^p2[9] ) ^ p3[7];\nassign c[8]= (p1[11] & p2[9]) | (p2[9] & p3[7]) | (p3[7] & p1[11]);\n\nassign s[9]=( p1[12] ^p2[10] ) ^ p3[8];\nassign c[9]= (p1[12] & p2[10]) | (p2[10] & p3[8]) | (p3[8] & p1[12]);\n\nassign s[10]=( p1[13] ^p2[11] ) ^ p3[9];\n//assign c[10]= (p1[13] & p2[11]) | (p2[11] & p3[9]) | (p3[9] & p1[13]);\n\n//2nd reduction 3 to 2\nassign s[11]=p1[2] ^ p2[0];\nassign c[11]=p1[2] & p2[0];\n\nassign s[12]=( p0[5] ^p1[3] ) ^ p2[1];\nassign c[12]= (p0[5] & p1[3]) | (p1[3] & p2[1]) | (p2[1] & p0[5]);\n\nassign s[13]=( p0[6] ^p1[4] ) ^ s[1];\nassign c[13]= (p0[6] & p1[4]) | (p1[4] & s[1]) | (s[1] & p0[6]);\n\nassign s[14]=( p0[7] ^c[1] ) ^ s[2];\nassign c[14]= (p0[7] & c[1]) | (c[1] & s[2]) | (s[2] & p0[7]);\n\nassign s[15]=( p0[8] ^c[2] ) ^ s[3];\nassign c[15]= (p0[8] & c[2]) | (c[2] & s[3]) | (s[3] & p0[8]);\n\nassign s[16]=( p0[9] ^c[3] ) ^ s[4];\nassign c[16]= (p0[9] & c[3]) | (c[3] & s[4]) | (s[4] & p0[9]);\n\nassign s[17]=( p0[10] ^c[4] ) ^ s[5];\nassign c[17]= (p0[10] & c[4]) | (c[4] & s[5]) | (s[5] & p0[10]);\n\nassign s[18]=( p0[11] ^c[5] ) ^ s[6];\nassign c[18]= (p0[11] & c[5]) | (c[5] & s[6]) | (s[6] & p0[11]);\n\nassign s[19]=( p0[12] ^c[6] ) ^ s[7];\nassign c[19]= (p0[12] & c[6]) | (c[6] & s[7]) | (s[7] & p0[12]);\n\nassign s[20]=( p0[13] ^c[7] ) ^ s[8];\nassign c[20]= (p0[13] & c[7]) | (c[7] & s[8]) | (s[8] & p0[13]);\n\nassign s[21]=( p0[14] ^c[8] ) ^ s[9];\nassign c[21]= (p0[14] & c[8]) | (c[8] & s[9]) | (s[9] & p0[14]);\n\nassign s[22]=( p0[15] ^c[9] ) ^ s[10];\n\n\ncla cla1(.x({c[21:11],p0[4:0]}),.y({s[22:11],p1[1],p1[0]}),.cin(1'b0),.sum({ans}));\n\nlatchh lat3(ans[7:0],clk,uo_out);\nlatchh lat4(ans[15:8],clk,uio_out);\n\n  // List all unused inputs to prevent warnings\n  wire _unused = &{ena, rst_n, 1'b0};\n\nendmodule\n\n\nmodule latchh(input [7:0]d,           // 1-bit input pin for data  \n             input clk,          // 1-bit input pin for enabling the latch\n              output reg [7:0]q);     // 1-bit output pin for data output  \n  \n   always @ (posedge clk)  \n    q <= d;  \nendmodule\n\nmodule booth_encoding(input a,b,c,\n                output zero,one,minus_one,two, minus_two);\nwire a_n,b_n,c_n,a1,a2,a3,a4,a5,a6;\nwire [7:0]i;\n\ndecoder_3_8 dec({a,b,c},i);\n\nassign a_n=~a;\nassign b_n=~b;\nassign c_n=~c;\n\nassign a1= a_n & b_n & c_n & i[0];\nassign a2=a & b & c & i[7];\nassign a3= a_n & b_n & c & i[1];\nassign a4= a_n & b & c_n & i[2];\n\nassign zero= a1 | a2;\nassign one= a3 | a4;\n\nassign a5= a & b_n & c & i[5];\nassign a6= a & b & c_n & i[6];\nassign minus_one= a5 | a6;\n\nassign two= a_n & b & c & i[3];\nassign minus_two=a & b_n & c_n & i[4];\n\nendmodule\n\nmodule decoder_3_8(input [2:0]din,\n                    output reg[7:0]dout);\n always @( din )\n        begin\n          dout=8'd0;\n          case (din)\n              3'b000: dout[0]=1'b1;\n              3'b001: dout[1]=1'b1;\n              3'b010: dout[2]=1'b1;\n              3'b011: dout[3]=1'b1;\n              3'b100: dout[4]=1'b1;\n              3'b101: dout[5]=1'b1;\n              3'b110: dout[6]=1'b1;\n              3'b111: dout[7]=1'b1;\n              default: dout=8'd0;\n          endcase\n      end               \nendmodule\n\nmodule cla(input [15:0]x, input [13:0]y, input cin, output  [15:0]sum);\nwire [13:0] p;\nwire [13:0]g;\nwire [13:1] c;\n\nassign sum[0]= x[0];\nassign sum[1]= x[1];\n\nassign p[0]= x[2] ^ y[0];\nassign g[0]= x[2] & y[0];\nassign c[1]= g[0] | (p[0] & cin);\nassign sum[2]= p[0] ^ cin;\n\nassign p[1]= x[3] ^ y[1];\nassign g[1]= x[3] & y[1];\nassign c[2]= g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin);\nassign sum[3]= p[1] ^ c[1];\n\nassign p[2]= x[4] ^ y[2];\nassign g[2]= x[4] & y[2];\nassign c[3]= g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin);\nassign sum[4]= p[2] ^ c[2]; \n\nassign p[3]= x[5] ^ y[3];\nassign g[3]= x[5] & y[3];\nassign c[4]= g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1]) | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[5]= p[3] ^ c[3];\n\nassign p[4]= x[6] ^ y[4];\nassign g[4]= x[6] & y[4];\nassign c[5]= g[4] | (p[4] & g[3]) |(p[4] & p[3] & g[2]) |(p[4] & p[3] & p[2] & g[1]) | (p[4] & p[3] & p[2] & p[1] & g[0]) | (p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[6]= p[4] ^ c[4];\n\nassign p[5]= x[7] ^ y[5];\nassign g[5]= x[7] & y[5];\nassign c[6]= g[5] | (p[5] & g[4]) |(p[5] & p[4] & g[3]) |(p[5] & p[4] & p[3] & g[2]) | (p[5] & p[4] & p[3] & p[2] & g[1]) | (p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[7]= p[5] ^ c[5];\n\nassign p[6]= x[8] ^ y[6];\nassign g[6]= x[8] & y[6];\nassign c[7]= g[6] | (p[6] & g[5]) | (p[6] & p[5] & g[4]) |(p[6] & p[5] & p[4] & g[3]) |(p[6] & p[5] & p[4] & p[3] & g[2]) | (p[6]  & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[8]= p[6] ^ c[6];\n\nassign p[7]= x[9] ^ y[7];\nassign g[7]= x[9] & y[7];\nassign c[8]= g[7] | (p[7] & g[6]) | (p[7] & p[6] & g[5]) | (p[7] & p[6] & p[5] & g[4]) |(p[7] & p[6] & p[5] & p[4] & g[3]) |(p[7] & p[6] & p[5] & p[4] & p[3] & g[2]) | (p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[9]= p[7] ^ c[7];\n\nassign p[8]= x[10] ^ y[8];\nassign g[8]= x[10] & y[8];\nassign c[9]= g[8] | (p[8] & g[7]) | (p[8] & p[7] & g[6]) | (p[8] & p[7] & p[6] & g[5]) | (p[8] & p[7] & p[6] & p[5] & g[4]) |(p[8] & p[7] & p[6] & p[5] & p[4] & g[3]) |(p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & g[2]) | (p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[10]= p[8] ^ c[8];\n\nassign p[9]= x[11] ^ y[9];\nassign g[9]= x[11] & y[9];\nassign c[10]= g[9] | (p[9] & g[8]) | (p[9] & p[8] & g[7]) | (p[9] & p[8] & p[7] & g[6]) | (p[9] & p[8] & p[7] & p[6] & g[5]) | (p[9] & p[8] & p[7] & p[6] & p[5] & g[4]) |(p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & g[3]) |(p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & g[2]) | (p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[11]= p[9] ^ c[9];\n\nassign p[10]= x[12] ^ y[10];\nassign g[10]= x[12] & y[10];\nassign c[11]= g[10] | (p[10] & g[9]) | (p[10] & p[9] & g[8]) | (p[10] & p[9] & p[8] & g[7]) | (p[10] & p[9] & p[8] & p[7] & g[6]) | (p[10] & p[9] & p[8] & p[7] & p[6] & g[5]) | (p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & g[4]) |(p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & g[3]) |(p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & g[2]) | (p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[12]= p[10] ^ c[10];\n\nassign p[11]= x[13] ^ y[11];\nassign g[11]= x[13] & y[11];\nassign c[12]= g[11] | (p[11] & g[10]) | (p[11] & p[10] & g[9]) | (p[11] & p[10] & p[9] & g[8]) | (p[11] & p[10] & p[9] & p[8] & g[7]) | (p[11] & p[10] & p[9] & p[8] & p[7] & g[6]) | (p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & g[5]) | (p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & g[4]) |(p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & g[3]) |(p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & g[2]) | (p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[13]= p[11] ^ c[11];\n\nassign p[12]= x[14] ^ y[12];\nassign g[12]= x[14] & y[12];\nassign c[13]= g[12] | (p[12] & g[11]) | (p[12] & p[11] & g[10]) | (p[12] & p[11] & p[10] & g[9]) | (p[12] & p[11] & p[10] & p[9] & g[8]) | (p[12] & p[11] & p[10] & p[9] & p[8] & g[7]) | (p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & g[6]) | (p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & g[5]) | (p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & g[4]) |(p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & g[3]) |(p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & g[2]) | (p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & g[1]) | (p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & g[0]) | (p[12] & p[11] & p[10] & p[9] & p[8] & p[7] & p[6] & p[5] & p[4] & p[3] & p[2] & p[1] & p[0] & cin);\nassign sum[14]= p[12] ^ c[12];\n\nassign p[13]= x[15] ^ y[13];\nassign g[13]= x[15] & y[13];\nassign sum[15]= p[13] ^ c[13];\n\nendmodule\n", "mask_idx": {"blocking_assignment": [[6613, 6626], [2415, 2453], [2862, 2892], [1868, 1906], [2215, 2240], [6793, 6806]], "module_program_interface_instantiation": [[5273, 5356], [1462, 1540], [2549, 2627]], "always_construct": [[2089, 2534], [6447, 6883], [1542, 1987], [992, 1439]], "case_statement": [[2147, 2523], [2686, 3062], [1050, 1426], [6508, 6858], [1600, 1976]], "ansi_port_declaration": [[6388, 6403], [5685, 5746], [6424, 6445]], "continuous_assign": [[4712, 4749], [4648, 4710], [10134, 10723], [6286, 6317]], "nonblocking_assignment": [[5782, 5791]]}, "all_mask_idx": {"module_program_interface_instantiation": [[683, 712], [713, 743], [916, 990], [1462, 1540], [2009, 2087], [2549, 2627], [5273, 5356], [5358, 5391], [5392, 5427], [5947, 5974]], "continuous_assign": [[623, 639], [795, 821], [3098, 3124], [3125, 3151], [3153, 3188], [3189, 3254], [3256, 3293], [3294, 3359], [3361, 3398], [3399, 3464], [3466, 3503], [3504, 3569], [3571, 3608], [3609, 3674], [3676, 3714], [3715, 3782], [3784, 3822], [3823, 3890], [3892, 3931], [3932, 4001], [4003, 4043], [4141, 4168], [4169, 4196], [4198, 4236], [4237, 4303], [4305, 4342], [4343, 4407], [4409, 4445], [4446, 4508], [4510, 4546], [4547, 4609], [4611, 4647], [4648, 4710], [4712, 4749], [4750, 4814], [4816, 4853], [4854, 4918], [4920, 4957], [4958, 5022], [5024, 5061], [5062, 5126], [5128, 5165], [5166, 5230], [5232, 5270], [5976, 5990], [5991, 6005], [6006, 6020], [6022, 6056], [6057, 6084], [6085, 6117], [6118, 6150], [6152, 6173], [6174, 6194], [6196, 6226], [6227, 6257], [6258, 6284], [6286, 6317], [6318, 6356], [7012, 7032], [7033, 7053], [7055, 7080], [7081, 7106], [7107, 7140], [7141, 7167], [7169, 7194], [7195, 7220], [7221, 7277], [7278, 7305], [7307, 7332], [7333, 7358], [7359, 7445], [7446, 7474], [7476, 7501], [7502, 7527], [7528, 7651], [7652, 7679], [7681, 7706], [7707, 7732], [7733, 7898], [7899, 7926], [7928, 7953], [7954, 7979], [7980, 8196], [8197, 8224], [8226, 8251], [8252, 8277], [8278, 8553], [8554, 8581], [8583, 8608], [8609, 8634], [8635, 8974], [8975, 9002], [9004, 9030], [9031, 9057], [9058, 9469], [9470, 9498], [9500, 9526], [9527, 9553], [9554, 10045], [10046, 10074], [10076, 10104], [10105, 10133], [10134, 10723], [10724, 10754], [10756, 10784], [10785, 10813], [10814, 11509], [11510, 11540], [11542, 11570], [11571, 11599], [11600, 12409], [12410, 12440], [12442, 12470], [12471, 12499], [12500, 12530]], "blocking_assignment": [[1030, 1039], [1084, 1093], [1118, 1143], [1168, 1201], [1226, 1256], [1318, 1356], [1399, 1408], [1580, 1589], [1634, 1643], [1668, 1693], [1718, 1751], [1776, 1806], [1868, 1906], [1949, 1958], [2127, 2136], [2181, 2190], [2215, 2240], [2265, 2298], [2323, 2353], [2415, 2453], [2496, 2505], [2666, 2675], [2720, 2729], [2754, 2779], [2804, 2837], [2862, 2892], [2954, 2992], [3035, 3044], [6487, 6497], [6541, 6554], [6577, 6590], [6613, 6626], [6649, 6662], [6685, 6698], [6721, 6734], [6757, 6770], [6793, 6806], [6830, 6840]], "nonblocking_assignment": [[5782, 5791]], "case_statement": [[1050, 1426], [1600, 1976], [2147, 2523], [2686, 3062], [6508, 6858]], "conditional_statement": [], "always_construct": [[992, 1439], [1542, 1987], [2089, 2534], [2628, 3073], [5753, 5791], [6447, 6883]], "parameter_declaration": [], "ansi_port_declaration": [[138, 185], [190, 238], [243, 289], [294, 341], [346, 426], [431, 519], [524, 560], [565, 618], [5542, 5595], [5609, 5670], [5685, 5746], [5825, 5837], [5833, 5837], [5835, 5837], [5854, 5896], [5866, 5896], [5870, 5896], [5880, 5896], [5885, 5896], [6388, 6403], [6424, 6445], [6906, 6966], [6921, 6966], [6936, 6966], [6947, 6966]]}}
{"sample_i": "urish-tt07-mandelbrot-accelarator", "topmodule": "tt_um_mandelbrot_accel", "code": "/*\n * Copyright (c) 2024 Uri Shaked\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\nmodule tt_um_mandelbrot_accel (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // always 1 when the design is powered, so you can ignore it\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  assign uo_out  = {o_iter, o_unbounded};\n  assign uio_oe  = 0;\n  assign uio_out = 0;\n\n  wire i_start = ui_in[0];\n  wire i_load_Cr = ui_in[1];\n  wire i_load_Ci = ui_in[2];\n  wire [7:0] data_in = uio_in;\n\n  reg o_unbounded;\n  reg [6:0] o_iter;\n\n  reg [23:0] data_in_reg;\n  wire [31:0] data_in_word = {data_in, data_in_reg};\n\n  reg [31:0] Cr_next;\n  reg [31:0] Ci_next;\n\n  reg [31:0] Zr;\n  reg [31:0] Zi;\n  reg [31:0] Cr;\n  reg [31:0] Ci;\n  wire [31:0] Rr;\n  wire [31:0] Ri;\n  wire unbounded;\n\n  mandelbrot_func mandelbrot (\n      .Ci(Ci),\n      .Cr(Cr),\n      .Zr(Zr),\n      .Zi(Zi),\n      .Rr(Rr),\n      .Ri(Ri),\n      .unbounded(unbounded)\n  );\n\n  always @(posedge clk or negedge rst_n)\n    if (~rst_n) begin\n      Zr <= 0;\n      Zi <= 0;\n      Cr <= 0;\n      Ci <= 0;\n      Cr_next <= 0;\n      Ci_next <= 0;\n      o_unbounded <= 0;\n      data_in_reg <= 0;\n      o_iter <= 0;\n    end else begin\n      if (i_load_Cr) begin\n        Cr_next <= data_in_word;\n      end\n      if (i_load_Ci) begin\n        Ci_next <= data_in_word;\n      end\n      if (i_start) begin\n        Zr <= i_load_Cr ? data_in_word : Cr_next;\n        Zi <= i_load_Ci ? data_in_word : Ci_next;\n        Cr <= i_load_Cr ? data_in_word : Cr_next;\n        Ci <= i_load_Ci ? data_in_word : Ci_next;\n        o_unbounded <= 0;\n        o_iter <= 1;\n      end else begin\n        Zr <= Rr;\n        Zi <= Ri;\n        data_in_reg <= {data_in, data_in_reg[23:8]};\n        if (unbounded) begin\n          o_unbounded <= 1;\n        end else if (!o_unbounded) begin\n          o_iter <= o_iter + 1;\n        end\n      end\n    end\n\n  // List all unused inputs to prevent warnings\n  wire _unused = &{ena, ui_in[7:3], 1'b0};\n\nendmodule\n\n\n// SPDX-FileCopyrightText: 2020 Efabless Corporation\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\");\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//\n//      http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n// SPDX-License-Identifier: Apache-2.0\n\n`default_nettype none\nmodule fp_add_sub (\n    input  wire [31:0] a_operand,\n    input  wire [31:0] b_operand,\n    input  wire op_subtract,\n    output reg  [31:0] o_result\n);\n\n\n  add_sub a(\n    .in_x(a_operand),\n    .in_y(b_operand),\n    .operation(op_subtract),\n    .round_mode(3'b000),\n    .out_z(o_result)\n  );\n\nendmodule\n\nmodule add_sub( \n  input  wire [31:0] in_x,\n  input  wire [31:0] in_y,\n  input  wire        operation,\n  input  wire [2:0]  round_mode,\n  output wire [31:0] out_z,\n  output wire [4:0]  exceptions);\n\n  wire        sign_x, sign_y;\n  wire [7:0]  exp_x, exp_y, exp_a, exp_b, subnorm_exp, norm_exp;\n  wire [22:0] mant_x, mant_y, mant_a, mant_b;\n\n  wire        x_is_zero, x_is_inf, x_is_qNaN, x_is_sNaN;\n  wire        y_is_zero, y_is_inf, y_is_qNaN, y_is_sNaN;\n  wire        a_is_subnorm, b_is_subnorm;\n  wire        hd_bit_a, hd_bit_b;\n\n  wire [26:0] arg1, arg2;\n  wire [26:0] rt_shift_mant;\n  wire [26:0] lt_shft_mant, norm_sum;\n  wire [26:0] mant_sum;\n  wire [23:0] rounded_mant;\n  wire [31:0] inter_result, of_result;\n\n  wire        comp, exp_shft_comp;\n  wire        operator_y, subtract;\n  wire        cout, cout_check;\n\n  wire [7:0]  exp_diff;\n  wire [4:0]  ld_zero_cnt, inc_dec_exp_amt;\n  wire [7:0]  inter_shft_amt, shft_amt;\n  wire        round_of;\n\n  wire        sign_z;\n  wire [7:0]  exp_z;\n  wire [22:0] mant_z;\n\t\n  wire        invalid_operation;\n  wire        divide_by_zero;\n  wire        overflow;\n  wire        underflow;\n  wire        inexact;\n  wire [9:0]  x_check_res, y_check_res;\n\n  // checking inputs for special values\n  special_check #(8, 24) check_x (.in(in_x), .result(x_check_res));\n  special_check #(8, 24) check_y (.in(in_y), .result(y_check_res));\n\n  assign x_is_zero = x_check_res[3] | x_check_res[4];\n  assign x_is_inf  = x_check_res[0] | x_check_res[7];\n  assign x_is_qNaN = x_check_res[9];\n  assign x_is_sNaN = x_check_res[8];\n\n  assign y_is_zero = y_check_res[3] | y_check_res[4];\n  assign y_is_inf  = y_check_res[0] | y_check_res[7];\n  assign y_is_qNaN = y_check_res[9];\n  assign y_is_sNaN = y_check_res[8];\n\n  // unpacking inputs\n  assign sign_x = in_x[31];\n  assign sign_y = in_y[31];\n  assign exp_x  = in_x[30:23];\n  assign exp_y  = in_y[30:23];\n  assign mant_x = in_x[22:0];\n  assign mant_y = in_y[22:0];\n\n  // comparing both numbers\n  assign comp = (exp_y > exp_x) ? 1'b1 : (exp_y != exp_x) ? 1'b0 : (mant_y > mant_x);\n\n  // determining operation to be performed\n  assign operator_y = sign_y ^ operation;\n  assign subtract   = sign_x ^ operator_y;\n\n  // determining output sign\n  assign sign_z = x_is_zero ? (operator_y) : (y_is_zero ? sign_x : \n                  (subtract ? (comp ? operator_y : sign_x) : sign_x));\n\t\n  // swapping operands\n  assign {exp_a, mant_a} = comp ? {exp_y, mant_y} : {exp_x, mant_x};\n  assign {exp_b, mant_b} = comp ? {exp_x, mant_x} : {exp_y, mant_y};\n\n  // checking for subnormal numbers\n  assign a_is_subnorm = (|exp_a == 0);\n  assign b_is_subnorm = (|exp_b == 0);\n\n  // checking difference in exponents\n  assign exp_diff = (a_is_subnorm | b_is_subnorm) & (exp_a != exp_b) ? (exp_a - exp_b - 1) \n                    : (exp_a - exp_b);\n\n  // generating hidden bits\n  assign hd_bit_a = !a_is_subnorm;\n  assign hd_bit_b = !b_is_subnorm;\n\t\n  // right shifting mantissa to make exponents equal\n  right_shifter exp_equalizer (.mantisa({hd_bit_b, mant_b, 3'b000}), .shift_amount(exp_diff), \n                               .out(rt_shift_mant));\n\t\n  // computing sum of the mantissas\n  assign arg1 = {hd_bit_a, mant_a, 3'b0};\n  assign arg2 = subtract ? (~rt_shift_mant + 27'b1) : rt_shift_mant;\n\n  assign {cout, mant_sum} = {1'b0,arg1} + {1'b0,arg2};\n  assign cout_check       = cout & ~subtract;\n\n  leading_zero norm_dist_checker (.in(mant_sum[26:3]), .out(ld_zero_cnt));\n\t\n  // computing the shift amount\n  assign inter_shft_amt = a_is_subnorm ? 8'b0 : {3'b0, ld_zero_cnt};\n  assign exp_shft_comp  = (exp_a <= inter_shft_amt);\n  assign shft_amt       = exp_shft_comp ? (exp_a - |exp_a) : inter_shft_amt;\n\n  left_shifter #(27) norm_shifter (.mantisa(mant_sum), .shift_amount(shft_amt), \n                             .out(lt_shft_mant));\n\n  // determining the exponent increment/decrement\n  assign norm_sum        = cout_check ? {cout, mant_sum[26:2], |mant_sum[1:0]} : lt_shft_mant;\n  assign inc_dec_exp_amt = a_is_subnorm ? 5'b0 : cout_check ? 5'b1 : shft_amt;\n\t\n  rounding add_sub_rounder (.sign(sign_z), .mantisa(norm_sum), .round_mode(round_mode), \n                            .rounded_mantisa(rounded_mant), .rounding_overflow(round_of));\n\n  // determine exponent in case of normal numbers\n  assign norm_exp = cout_check ? (exp_a + inc_dec_exp_amt + round_of) : \n                    (exp_a - inc_dec_exp_amt + round_of);\n\n  // determine exponent in case of subnormal numbers\n  assign subnorm_exp = (rounded_mant[23] & !(|norm_exp)) ? 8'b1 : \n                       (norm_exp - ((hd_bit_a | hd_bit_b) & exp_shft_comp & !rounded_mant[23]));\n\t\n  assign {exp_z, mant_z} = x_is_zero ? {exp_y, mant_y} : (y_is_zero ? {exp_x, mant_x} : \n                           ((mant_x == mant_y) & (exp_x == exp_y) & subtract ? 'd0 : \n                           {subnorm_exp, rounded_mant[22:0]}));\n\n  // result check for special numbers\n  assign inter_result = (x_is_qNaN | y_is_qNaN) ? {1'h0, 8'hff, 23'h400000} : \n                        ((x_is_inf | y_is_inf) ? {sign_z, 8'hff, 23'h0} : ((exp_z == 8'hff) ? \n                        {sign_z, exp_z, 23'd0} : {sign_z, exp_z, mant_z}));\n\n  assign invalid_operation = !(x_is_qNaN | y_is_qNaN) & (x_is_inf & y_is_inf & subtract) | \n                               x_is_sNaN | y_is_sNaN;\n\n  // does not occur in addition subtraction\n  assign divide_by_zero = 0;\n\n  assign overflow = !(x_is_qNaN | y_is_qNaN) & &exp_z & !(x_is_inf | y_is_inf | x_is_qNaN | \n                      y_is_qNaN | x_is_sNaN | y_is_sNaN);\n\t\n  // determining result in case of overflow\n  assign of_result = ({32{(round_mode == 3'h0) | (round_mode == 3'h4)}} & {sign_z, 8'hff, 23'h0}) |\n                     ({32{round_mode == 3'h1}} & {sign_z, 8'hfe, 23'h7fffff}) |\n                     ({32{round_mode == 3'h2}} & (sign_z ? {1'h1, 8'hff, 23'h0} : \n                                                 {1'h0, 8'hfe, 23'h7fffff})) |\n                     ({32{round_mode == 3'h3}} & (sign_z ? {1'h1, 8'hfe, 23'h7fffff} : \n                                                 {1'h0, 8'hff, 23'h0}));\n\n  // does not occur in addition subtraction\n  assign underflow = 0;\n\n  assign inexact = !(x_is_qNaN | y_is_qNaN) & (|norm_sum[2:0] | overflow | underflow) & \n                   !(x_is_zero | y_is_zero | x_is_qNaN | y_is_qNaN | x_is_sNaN | y_is_sNaN | \n                     x_is_inf  | y_is_inf);\n\n  assign exceptions = {invalid_operation, divide_by_zero, overflow, underflow, inexact};\n\n  // assign output\n  assign out_z = overflow ? of_result : underflow ? 32'd0 : invalid_operation ? \n                 {1'h0, 8'hff, 23'h400000} : inter_result;\n\nendmodule\n\n\nmodule left_shifter #(parameter mant = 24) \n(\n\tinput  wire [mant-1:0] mantisa,\n\tinput  wire [7:0] shift_amount,\n\n\toutput wire [mant-1:0] out\n);\n\n\twire [mant-1:0] temp;\n\n\tassign temp  = mantisa << shift_amount;\n\tassign out   = {temp[mant-1:1], mantisa[0]};\n\nendmodule\n\nmodule right_shifter \n(\n  input  wire [26:0] mantisa,\n  input  wire [7:0] shift_amount,\n\n  output wire [26:0] out\n);\n\n  assign out = ({27{(shift_amount[7:0]==8'd0)}}  &         mantisa)                          |\n              ({27{(shift_amount[7:0]==8'd1)}}  & {1'd0,  mantisa[26:2],   |mantisa[1:0]})  |\n              ({27{(shift_amount[7:0]==8'd2)}}  & {2'd0,  mantisa[26:3],   |mantisa[2:0]})  |\n              ({27{(shift_amount[7:0]==8'd3)}}  & {3'd0,  mantisa[26:4],   |mantisa[3:0]})  |\n              ({27{(shift_amount[7:0]==8'd4)}}  & {4'd0,  mantisa[26:5],   |mantisa[4:0]})  |\n              ({27{(shift_amount[7:0]==8'd5)}}  & {5'd0,  mantisa[26:6],   |mantisa[5:0]})  |\n              ({27{(shift_amount[7:0]==8'd6)}}  & {6'd0,  mantisa[26:7],   |mantisa[6:0]})  |\n              ({27{(shift_amount[7:0]==8'd7)}}  & {7'd0,  mantisa[26:8],   |mantisa[7:0]})  |\n              ({27{(shift_amount[7:0]==8'd8)}}  & {8'd0,  mantisa[26:9],   |mantisa[8:0]})  |\n              ({27{(shift_amount[7:0]==8'd9)}}  & {9'd0,  mantisa[26:10],  |mantisa[9:0]})  |\n              ({27{(shift_amount[7:0]==8'd10)}} & {10'd0, mantisa[26:11],  |mantisa[10:0]}) |\n              ({27{(shift_amount[7:0]==8'd11)}} & {11'd0, mantisa[26:12],  |mantisa[11:0]}) |\n              ({27{(shift_amount[7:0]==8'd12)}} & {12'd0, mantisa[26:13],  |mantisa[12:0]}) |\n              ({27{(shift_amount[7:0]==8'd13)}} & {13'd0, mantisa[26:14],  |mantisa[13:0]}) |\n              ({27{(shift_amount[7:0]==8'd14)}} & {14'd0, mantisa[26:15],  |mantisa[14:0]}) |\n              ({27{(shift_amount[7:0]==8'd15)}} & {15'd0, mantisa[26:16],  |mantisa[15:0]}) |\n              ({27{(shift_amount[7:0]==8'd16)}} & {16'd0, mantisa[26:17],  |mantisa[16:0]}) |\n              ({27{(shift_amount[7:0]==8'd17)}} & {17'd0, mantisa[26:18],  |mantisa[17:0]}) |\n              ({27{(shift_amount[7:0]==8'd18)}} & {18'd0, mantisa[26:19],  |mantisa[18:0]}) |\n              ({27{(shift_amount[7:0]==8'd19)}} & {19'd0, mantisa[26:20],  |mantisa[19:0]}) |\n              ({27{(shift_amount[7:0]==8'd20)}} & {20'd0, mantisa[26:21],  |mantisa[20:0]}) |\n              ({27{(shift_amount[7:0]==8'd21)}} & {21'd0, mantisa[26:22],  |mantisa[21:0]}) |\n              ({27{(shift_amount[7:0]==8'd22)}} & {22'd0, mantisa[26:23],  |mantisa[22:0]}) |\n              ({27{(shift_amount[7:0]==8'd23)}} & {23'd0, mantisa[26:24],  |mantisa[23:0]}) |\n              ({27{(shift_amount[7:0]==8'd24)}} & {24'd0, mantisa[26:25],  |mantisa[24:0]}) |\n              ({27{(shift_amount[7:0]==8'd25)}} & {25'd0, mantisa[26],     |mantisa[25:0]}) |\n              ({27{(shift_amount[7:0]>=8'd26)}} & {26'd0,                  |mantisa[26:0]});\nendmodule\n\n\nmodule rounding\n(\n  input  wire sign,\n  input  wire [26:0] mantisa,\n  input  wire [2:0] round_mode,\n\n  output wire [23:0] rounded_mantisa,\n  output wire rounding_overflow\n);\n  \n  wire [23:0] rne, rtz, rdn, rup, rmm;\n  wire rne_overflow, rtz_overflow, rdn_overflow, rup_overflow, rmm_overflow;\n\n  assign {rne_overflow, rne} = mantisa[2] ? (|mantisa[1:0] ? ({1'b0, mantisa[26:3]} + 1'b1) \n                               : ({1'b0, mantisa[26:3]} + mantisa[3])) : {1'b0, mantisa[26:3]};\n\n  assign {rtz_overflow, rtz} = {1'b0, mantisa[26:3]};\n\n  assign {rdn_overflow, rdn} = |mantisa[2:0] ? (sign ? ({1'b0, mantisa[26:3]} + 1'b1) \n                                : {1'b0, mantisa[26:3]}) : {1'b0, mantisa[26:3]};\n\n  assign {rup_overflow, rup} = |mantisa[2:0] ? (sign ? {1'b0, mantisa[26:3]} \n                                  : ({1'b0, mantisa[26:3]} + 1'b1)) : {1'b0, mantisa[26:3]};\n  assign {rmm_overflow, rmm} = mantisa[2] ? ({1'b0, mantisa[26:3]} + 1'b1) : {1'b0, mantisa[26:3]};\n\n  assign rounded_mantisa     = ({24{round_mode == 3'b000}} & rne) |\n                               ({24{round_mode == 3'b001}} & rtz) |\n                               ({24{round_mode == 3'b010}} & rdn) |\n                               ({24{round_mode == 3'b011}} & rup) |\n                               ({24{round_mode == 3'b100}} & rmm);\n\n  assign rounding_overflow   = ((round_mode == 3'b000) & rne_overflow) |\n                               ((round_mode == 3'b001) & rtz_overflow) |\n                               ((round_mode == 3'b010) & rdn_overflow) |\n                               ((round_mode == 3'b011) & rup_overflow) |\n                               ((round_mode == 3'b100) & rmm_overflow);\n\nendmodule\n\nmodule leading_zero\n(\n  input  wire [23:0] in,\n\n  output wire [4:0] out\n);\n  assign out[4:0]       = ({5{(in[22]  & (&(~(in[23]))))}}    & 5'd1)  |\t\t\t \n \t\t                      ({5{(in[21]  & (&(~(in[23:22]))))}} & 5'd2)  |\n \t\t                      ({5{(in[20]  & (&(~(in[23:21]))))}} & 5'd3)  |\n \t\t                      ({5{(in[19]  & (&(~(in[23:20]))))}} & 5'd4)  |\n \t\t                      ({5{(in[18]  & (&(~(in[23:19]))))}} & 5'd5)  |\n \t\t                      ({5{(in[17]  & (&(~(in[23:18]))))}} & 5'd6)  |\n \t\t                      ({5{(in[16]  & (&(~(in[23:17]))))}} & 5'd7)  |\n \t\t                      ({5{(in[15]  & (&(~(in[23:16]))))}} & 5'd8)  |\n \t\t                      ({5{(in[14]  & (&(~(in[23:15]))))}} & 5'd9)  |\n \t\t                      ({5{(in[13]  & (&(~(in[23:14]))))}} & 5'd10) |\n \t\t                      ({5{(in[12]  & (&(~(in[23:13]))))}} & 5'd11) |\n \t\t                      ({5{(in[11]  & (&(~(in[23:12]))))}} & 5'd12) |\n \t\t                      ({5{(in[10]  & (&(~(in[23:11]))))}} & 5'd13) |\n \t\t                      ({5{(in[9]   & (&(~(in[23:10]))))}} & 5'd14) |\n \t\t                      ({5{(in[8]   & (&(~(in[23: 9]))))}} & 5'd15) |\n \t\t                      ({5{(in[7]   & (&(~(in[23: 8]))))}} & 5'd16) |\n \t\t                      ({5{(in[6]   & (&(~(in[23: 7]))))}} & 5'd17) |\n \t\t                      ({5{(in[5]   & (&(~(in[23: 6]))))}} & 5'd18) |\n \t\t                      ({5{(in[4]   & (&(~(in[23: 5]))))}} & 5'd19) |\n \t\t                      ({5{(in[3]   & (&(~(in[23: 4]))))}} & 5'd20) |\n \t\t                      ({5{(in[2]   & (&(~(in[23: 3]))))}} & 5'd21) |\n \t\t                      ({5{(in[1]   & (&(~(in[23: 2]))))}} & 5'd22) |\n \t\t                      ({5{(in[0]   & (&(~(in[23: 1]))))}} & 5'd23);\n\nendmodule\n\nmodule special_check #(parameter  exp_width = 8, parameter mant_width = 24) \n(\n  input  wire [(exp_width + mant_width-1):0] in,\n\n  output wire [9:0] result\n);\n\n  wire is_pos_zero;\n  wire is_neg_zero;\n  wire is_pos_inf;\n  wire is_neg_inf;\n  wire is_pos_subnorm;\n  wire is_neg_subnorm;\n  wire is_pos_norm;\n  wire is_neg_norm;\n  wire is_qNaN;\n  wire is_sNaN;\n\n  wire                    sign;\n  wire [exp_width-1:0]    exp;\n  wire [(mant_width-2):0] sig;\n\n  wire exp_zero, exp_one, sig_zero; \n\n\n  assign {sign, exp, sig} = in;\n\n  assign exp_zero         = |exp ? 1'b0 : 1'b1;\n  assign sig_zero         = |sig ? 1'b0 : 1'b1;     \n  assign exp_one          = &exp ? 1'b1 : 1'b0;\n\n  assign is_pos_zero      = !sign     & exp_zero  & sig_zero;\n  assign is_neg_zero      =  sign     & exp_zero  & sig_zero;\n  assign is_pos_subnorm   = !sign     & exp_zero  & !sig_zero;\n  assign is_neg_subnorm   =  sign     & exp_zero  & !sig_zero;\n  assign is_pos_inf       = !sign     & exp_one   & sig_zero; \n  assign is_neg_inf       =  sign     & exp_one   & sig_zero; \n  assign is_qNaN          =  exp_one  & !sig_zero & sig[22];\n  assign is_sNaN          =  exp_one  & !sig_zero & !sig[22];\n\n  assign is_pos_norm      = (is_pos_zero | is_neg_zero | is_pos_subnorm | is_neg_subnorm | is_pos_inf | is_neg_inf | \n\t\t\t                      is_qNaN | is_sNaN) ? 1'b0 : ~sign ? 1'b1 : 1'b0;\n \n  assign is_neg_norm      = (is_pos_zero | is_neg_zero | is_pos_subnorm | is_neg_subnorm | is_pos_inf | is_neg_inf | \n\t\t\t                      is_qNaN | is_sNaN) ? 1'b0 : sign ? 1'b1 : 1'b0; \n\n  assign result           = {is_qNaN, is_sNaN, is_pos_inf, is_pos_norm, is_pos_subnorm, is_pos_zero, is_neg_zero, \n                            is_neg_subnorm, is_neg_norm, is_neg_inf};\nendmodule\n\n\n// The following module was generated by GPT-4o. Prompt:\n// \n// ```\n// module fp_multiply (\n//     input wire [31:0] a_operand,\n//     input wire [31:0] b_operand,\n//     output reg o_exception,\n//     output reg o_overflow,\n//     output reg o_underflow,\n//     output reg [31:0] o_result\n// );\n// \n// Implement IEEE-754 floating point multiplication.\n// ```\n\n`default_nettype none\n\nmodule fp_multiply (\n    input wire [31:0] a_operand,\n    input wire [31:0] b_operand,\n    output reg o_exception,\n    output reg o_overflow,\n    output reg o_underflow,\n    output reg [31:0] o_result\n);\n\n  // Split the inputs into sign, exponent, and mantissa\n  wire sign_a, sign_b, sign_result;\n  wire [7:0] exponent_a, exponent_b, exponent_result;\n  wire [23:0] mantissa_a, mantissa_b;\n\n  assign sign_a = a_operand[31];\n  assign sign_b = b_operand[31];\n  assign exponent_a = a_operand[30:23];\n  assign exponent_b = b_operand[30:23];\n  assign mantissa_a = {1'b1, a_operand[22:0]};\n  assign mantissa_b = {1'b1, b_operand[22:0]};\n\n  // Calculate the result sign\n  assign sign_result = sign_a ^ sign_b;\n\n  // Calculate the result exponent\n  assign exponent_result = exponent_a + exponent_b - 8'd127;\n\n  // Multiply the mantissas\n  wire [47:0] product_mantissa;\n  assign product_mantissa = mantissa_a * mantissa_b;\n\n  // Normalize the result mantissa and adjust the exponent if necessary\n  wire [22:0] normalized_mantissa;\n  wire [ 7:0] adjusted_exponent;\n\n  assign adjusted_exponent = (product_mantissa[47]) ? (exponent_result + 1) : exponent_result;\n  assign normalized_mantissa = (product_mantissa[47]) ? product_mantissa[46:24] : product_mantissa[45:23];\n\n  // Handle special cases\n  always @(*) begin\n    o_exception = 0;\n    o_overflow = 0;\n    o_underflow = 0;\n    o_result = 32'd0;\n\n    // Check for NaN and Infinity\n    if ((exponent_a == 8'd255 && mantissa_a[22:0] != 0) || (exponent_b == 8'd255 && mantissa_b[22:0] != 0)) begin\n      // NaN\n      o_exception = 1;\n      o_result = 32'h7FC00000;  // Quiet NaN\n    end else if (exponent_a == 8'd255 || exponent_b == 8'd255) begin\n      // Infinity\n      o_result = {sign_result, 8'd255, 23'd0};\n    end else if (exponent_a == 0 || exponent_b == 0) begin\n      // Zero\n      o_result = {sign_result, 8'd0, 23'd0};\n    end else begin\n      // Normal case\n      if (adjusted_exponent >= 8'd255) begin\n        // Overflow\n        o_overflow = 1;\n        o_result   = {sign_result, 8'd255, 23'd0};\n      end else if (adjusted_exponent <= 8'd0) begin\n        // Underflow\n        o_underflow = 1;\n        o_result = {sign_result, 8'd0, 23'd0};\n      end else begin\n        o_result = {sign_result, adjusted_exponent[7:0], normalized_mantissa[22:0]};\n      end\n    end\n  end\n\nendmodule\n\n\n/*\n * Copyright (c) 2024 Uri Shaked\n * SPDX-License-Identifier: Apache-2.0\n */\n\n`default_nettype none\n\n/** \n * This module calculates one iteration of the Mandelbrot set function:\n * R = Z^2 + C\n * \n * In addition, it checks if the given input Z is not a member of the Mandelbrot set, setting\n * unbounded to 1 when |Z| > 2.\n */\nmodule mandelbrot_func (\n    input wire [31:0] Ci,\n    input wire [31:0] Cr,\n    input wire [31:0] Zr,\n    input wire [31:0] Zi,\n    output wire [31:0] Rr,\n    output wire [31:0] Ri,\n    output wire unbounded\n);\n\n  // ZrZi = Zr * Zi\n  wire [31:0] ZrZi;\n  fp_multiply m1 (\n      .a_operand(Zr),\n      .b_operand(Zi),\n      .o_result(ZrZi),\n      .o_exception(),\n      .o_overflow(),\n      .o_underflow()\n  );\n\n  // Zr_squared = Zr * Zr\n  wire [31:0] Zr_squared;\n  fp_multiply m2 (\n      .a_operand(Zr),\n      .b_operand(Zr),\n      .o_result(Zr_squared),\n      .o_exception(),\n      .o_overflow(),\n      .o_underflow()\n  );\n\n  // Zi_squared = Zi * Zi\n  wire [31:0] Zi_squared;\n  fp_multiply m3 (\n      .a_operand(Zi),\n      .b_operand(Zi),\n      .o_result(Zi_squared),\n      .o_exception(),\n      .o_overflow(),\n      .o_underflow()\n  );\n\n\n  wire [31:0] Z2r;\n  wire [31:0] Z2i;\n\n  // Z2r = Zr_squared - Zi_squared\n  fp_add_sub sub1 (\n      .a_operand(Zr_squared),\n      .b_operand(Zi_squared),\n      .op_subtract(1'b1),\n      .o_result(Z2r)\n  );\n\n  // Z2i = 2 * Zr * Zi\n  fp_add_sub add1 (\n      .a_operand(ZrZi),\n      .b_operand(ZrZi),\n      .op_subtract(1'b0),\n      .o_result(Z2i)\n  );\n\n  // Rr = Z2r + Cr\n  fp_add_sub add2 (\n      .a_operand(Z2r),\n      .b_operand(Cr),\n      .op_subtract(1'b0),\n      .o_result(Rr)\n  );\n\n  // Ri = Z2i + Ci\n  fp_add_sub add3 (\n      .a_operand(Z2i),\n      .b_operand(Ci),\n      .op_subtract(1'b0),\n      .o_result(Ri)\n  );\n\n  wire [31:0] Z_abs_squared;\n  wire [31:0] four_ieee754 = 32'h40800020;  // ~4.0\n\n  // |Z|^2 = Zr^2 + Zi^2\n  fp_add_sub add4 (\n      .a_operand(Zr_squared),\n      .b_operand(Zi_squared),\n      .op_subtract(1'b0),\n      .o_result(Z_abs_squared)\n  );\n\n  wire [31:0] Z_minus_four;\n  // calculate |Z|^2 - 4\n  fp_add_sub sub3 (\n      .a_operand(Z_abs_squared),\n      .b_operand(four_ieee754),\n      .op_subtract(1'b1),\n      .o_result(Z_minus_four)\n  );\n\n  assign unbounded = ~Z_minus_four[31];  // |Z| > 2\nendmodule\n", "mask_idx": {"conditional_statement": [[1526, 1589], [20185, 20738], [2050, 2183]], "blocking_assignment": [[19728, 19744]], "module_program_interface_instantiation": [[22657, 22796], [1118, 1269], [22853, 22996], [21342, 21494]], "always_construct": [[1273, 2201], [19706, 20744]], "ansi_port_declaration": [[191, 239], [14581, 14602], [10257, 10279]], "continuous_assign": [[4660, 4711], [19084, 19121], [4951, 4985], [19282, 19332], [6750, 6816], [14157, 14518]], "parameter_declaration": [[16301, 16354], [16327, 16354], [9920, 9941]], "nonblocking_assignment": [[2150, 2171], [1997, 2041], [1488, 1500]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1118, 1269], [3137, 3271], [4523, 4588], [4591, 4656], [6241, 6386], [6641, 6713], [6950, 7078], [7308, 7485], [21342, 21494], [21550, 21708], [21764, 21922], [22001, 22130], [22157, 22274], [22297, 22410], [22433, 22546], [22657, 22796], [22853, 22996]], "continuous_assign": [[626, 665], [668, 687], [690, 709], [4660, 4711], [4714, 4765], [4768, 4802], [4805, 4839], [4843, 4894], [4897, 4948], [4951, 4985], [4988, 5022], [5048, 5073], [5076, 5101], [5104, 5132], [5135, 5163], [5166, 5193], [5196, 5223], [5255, 5338], [5385, 5424], [5427, 5467], [5500, 5636], [5664, 5730], [5733, 5799], [5839, 5875], [5878, 5914], [5956, 6084], [6116, 6148], [6151, 6183], [6427, 6466], [6469, 6535], [6539, 6591], [6594, 6637], [6750, 6816], [6819, 6869], [6872, 6946], [7132, 7224], [7227, 7303], [7539, 7667], [7724, 7885], [7890, 8126], [8168, 8415], [8419, 8562], [8610, 8636], [8640, 8788], [8837, 9337], [9385, 9406], [9410, 9634], [9638, 9724], [9747, 9884], [10068, 10107], [10109, 10153], [10286, 12821], [13130, 13316], [13320, 13371], [13375, 13541], [13545, 13713], [13716, 13813], [13817, 14153], [14157, 14518], [14608, 16265], [16771, 16800], [16804, 16849], [16852, 16902], [16905, 16950], [16954, 17013], [17016, 17075], [17078, 17138], [17141, 17201], [17204, 17264], [17267, 17327], [17330, 17388], [17391, 17450], [17454, 17643], [17648, 17837], [17841, 18023], [18812, 18842], [18845, 18875], [18878, 18915], [18918, 18955], [18958, 19002], [19005, 19049], [19084, 19121], [19160, 19218], [19282, 19332], [19477, 19569], [19572, 19676], [23000, 23049]], "blocking_assignment": [[19728, 19744], [19749, 19764], [19769, 19785], [19790, 19807], [19976, 19992], [19999, 20037], [20131, 20171], [20251, 20289], [20403, 20418], [20427, 20469], [20551, 20567], [20576, 20614], [20644, 20720]], "nonblocking_assignment": [[1340, 1348], [1355, 1363], [1370, 1378], [1385, 1393], [1400, 1413], [1420, 1433], [1440, 1457], [1464, 1481], [1488, 1500], [1555, 1579], [1625, 1649], [1693, 1734], [1743, 1784], [1793, 1834], [1843, 1884], [1893, 1910], [1919, 1931], [1961, 1970], [1979, 1988], [1997, 2041], [2081, 2098], [2150, 2171]], "case_statement": [], "conditional_statement": [[1316, 2201], [1526, 1589], [1596, 1659], [1666, 2193], [2050, 2183], [2116, 2183], [19847, 20738], [20051, 20738], [20185, 20738], [20336, 20730], [20485, 20730]], "always_construct": [[1273, 2201], [19706, 20744]], "parameter_declaration": [[9920, 9941], [16301, 16354], [16327, 16354]], "ansi_port_declaration": [[139, 186], [191, 239], [244, 290], [295, 342], [347, 427], [432, 520], [525, 561], [566, 619], [3005, 3034], [3039, 3068], [3073, 3097], [3102, 3129], [3303, 3327], [3330, 3354], [3357, 3386], [3389, 3419], [3422, 3447], [3450, 3481], [9945, 9976], [9978, 10009], [10012, 10038], [10192, 10219], [10222, 10253], [10257, 10279], [12854, 12871], [12874, 12901], [12904, 12933], [12937, 12972], [12975, 13004], [14555, 14577], [14581, 14602], [16359, 16405], [16409, 16433], [18445, 18473], [18478, 18506], [18511, 18534], [18539, 18561], [18566, 18589], [18594, 18620], [21116, 21137], [21142, 21163], [21168, 21189], [21194, 21215], [21220, 21242], [21247, 21269], [21274, 21295]]}}
{"sample_i": "urish-tt07-spell", "topmodule": "tt_um_urish_spell", "code": "// SPDX-FileCopyrightText: © 2024 Uri Shaked <uri@wokwi.com>\n// SPDX-License-Identifier: MIT\n\n`default_nettype none\n\nmodule tt_um_urish_spell (\n    input  wire [7:0] ui_in,    // Dedicated inputs\n    output wire [7:0] uo_out,   // Dedicated outputs\n    input  wire [7:0] uio_in,   // IOs: Input path\n    output wire [7:0] uio_out,  // IOs: Output path\n    output wire [7:0] uio_oe,   // IOs: Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // will go high when the design is enabled\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  localparam StateFetch = 3'd0;\n  localparam StateFetchData = 3'd1;\n  localparam StateExecute = 3'd2;\n  localparam StateStore = 3'd3;\n  localparam StateDelay = 3'd4;\n  localparam StateSleep = 3'd5;\n  localparam StateStop = 3'd6;\n\n  localparam REG_PC = 2'd0;\n  localparam REG_SP = 2'd1;\n  localparam REG_EXEC = 2'd2;\n  localparam REG_STACK_TOP = 2'd3;\n\n  wire o_sleep = state == StateSleep;\n  wire o_stop = state == StateStop || state == StateSleep;\n  wire o_wait_delay = state == StateDelay;\n  reg o_shift_out;\n\n  wire [7:0] porta_oe;\n  wire [7:0] porta_out;\n  assign uo_out = (\n    (~porta_oe & {4'b0000, o_shift_out, o_wait_delay, o_stop, o_sleep})\n    | (porta_oe & porta_out)\n  );\n\n  wire i_run = ui_in[0];\n  wire i_step = ui_in[1];\n  wire i_load = ui_in[2];\n  wire i_dump = ui_in[3];\n  wire i_shift_in = ui_in[4];\n  wire [1:0] i_reg_sel = ui_in[6:5];\n\n  reg past_i_run;\n  reg [2:0] state;\n  reg [7:0] pc;\n  reg [4:0] sp;\n  reg [7:0] opcode;\n  reg [7:0] memory_input;\n  reg [7:0] stack[31:0];\n\n  wire [7:0] next_pc;\n  wire [4:0] next_sp;\n  wire [1:0] stack_write_count;\n  wire [7:0] set_stack_top;\n  wire [7:0] set_stack_belowtop;\n  wire memory_write_en;\n  wire memory_write_type_data;\n  wire [7:0] memory_write_addr;\n  wire [7:0] memory_write_data;\n  wire [7:0] delay_amount;\n  wire sleep;\n  wire stop;\n\n  // shift register for loading data / dumping debug info\n  reg [7:0] shift_reg;\n\n  // Out of order execution\n  reg single_step;\n  reg out_of_order_exec;\n\n  wire [4:0] stack_top_index = sp - 1;\n  wire [7:0] stack_top = stack[stack_top_index];\n\n  // Memory related registers\n  reg mem_select;\n  reg mem_type_data;\n  reg [7:0] mem_addr;\n  reg [7:0] mem_write_value;\n  reg mem_write_en;\n  wire [7:0] mem_read_value;\n  wire mem_data_ready;\n\n  // Delay related registers\n  reg [23:0] cycles_per_ms;\n  reg [23:0] delay_cycles;\n  reg [7:0] delay_counter;\n\n  // Debug stuff\n  reg [63:0] reg_name;\n  reg [63:0] state_name;\n\n  // To avoid linter warnings about unused wires\n  wire _unused_ok = &{1'b0, ena, ui_in[7], state_name, reg_name, 1'b0};\n\n  always @(*) begin\n    case (state)\n      StateFetch: state_name = \"Fetch\";\n      StateFetchData: state_name = \"FetchDat\";\n      StateExecute: state_name = \"Execute\";\n      StateStore: state_name = \"Store\";\n      StateDelay: state_name = \"Delay\";\n      StateSleep: state_name = \"Sleep\";\n      StateStop: state_name = \"Stop\";\n      default: state_name = \"Invalid\";\n    endcase\n  end\n\n  always @(*) begin\n    case (i_reg_sel)\n      REG_PC: reg_name = \"PC\";\n      REG_SP: reg_name = \"SP\";\n      REG_EXEC: reg_name = \"Exec\";\n      REG_STACK_TOP: reg_name = \"StackTop\";\n    endcase\n  end\n\n  spell_execute exec (\n      .opcode(opcode),\n      .pc(pc),\n      .sp(sp),\n      .stack_top(stack_top),\n      .stack_belowtop(stack[sp-2]),\n      .memory_input(memory_input),\n      .next_pc(next_pc),\n      .next_sp(next_sp),\n      .out_of_order_exec(out_of_order_exec),\n      .stack_write_count(stack_write_count),\n      .set_stack_top(set_stack_top),\n      .set_stack_belowtop(set_stack_belowtop),\n      .memory_write_en(memory_write_en),\n      .memory_write_type_data(memory_write_type_data),\n      .memory_write_addr(memory_write_addr),\n      .memory_write_data(memory_write_data),\n      .delay_amount(delay_amount),\n      .sleep(sleep),\n      .stop(stop)\n  );\n\n  spell_mem mem (\n      .rst_n(rst_n),\n      .clk(clk),\n      .select(mem_select),\n      .addr(mem_addr),\n      .data_in(mem_write_value),\n      .memory_type_data(mem_type_data),\n      .write(mem_write_en),\n      .data_out(mem_read_value),\n      .data_ready(mem_data_ready),\n      // IO\n      .porta_out(porta_out),\n      .porta_oe(porta_oe),\n      .portb_in(uio_in),\n      .portb_out(uio_out),\n      .portb_oe(uio_oe)\n  );\n\n  function is_data_opcode(input [7:0] opcode_to_test);\n    is_data_opcode = (opcode_to_test == \"?\" || opcode_to_test == \"r\");\n  endfunction\n\n  integer j;\n\n  // Main logic\n  always @(posedge clk) begin\n    if (~rst_n) begin\n      state <= StateSleep;\n      pc    <= 0;\n      sp    <= 0;\n      for (j = 0; j < 32; j++) stack[j] <= 0;\n      opcode <= 0;\n      mem_select <= 0;\n      mem_write_en <= 0;\n      single_step <= 0;\n      out_of_order_exec <= 0;\n      cycles_per_ms <= 24'd10000;  /* we assume a 10MHz clock */\n      delay_cycles <= 0;\n      shift_reg <= 0;\n      o_shift_out <= 0;\n      past_i_run <= 0;\n    end else begin\n      shift_reg   <= {shift_reg[6:0], i_shift_in};\n      o_shift_out <= shift_reg[7];\n      past_i_run  <= i_run;\n\n      if (i_load) begin\n        case (i_reg_sel)\n          REG_PC: pc <= shift_reg;\n          REG_SP: sp <= shift_reg[4:0];\n          REG_EXEC: begin\n            opcode <= shift_reg;\n            state <= is_data_opcode(shift_reg) ? StateFetchData : StateExecute;\n            single_step <= 1;\n            out_of_order_exec <= 1;\n          end\n          REG_STACK_TOP: begin\n            stack[sp] <= shift_reg;\n            sp <= sp + 1;\n          end\n        endcase\n      end\n\n      if (i_dump) begin\n        case (i_reg_sel)\n          REG_PC: shift_reg <= pc;\n          REG_SP: shift_reg <= {3'b000, sp};\n          REG_EXEC: shift_reg <= opcode;\n          REG_STACK_TOP: shift_reg <= stack[sp-1];\n        endcase\n      end\n\n      if (i_run && !past_i_run && (state == StateSleep || state == StateStop)) begin\n        single_step <= i_step;\n        out_of_order_exec <= 0;\n        state <= StateFetch;\n      end\n\n      case (state)\n        StateFetch: begin\n          // Read next instruction from code memory\n          mem_select <= 1;\n          mem_type_data <= 0;\n          mem_addr <= pc;\n          mem_write_en <= 0;\n          if (mem_select && mem_data_ready) begin\n            mem_select <= 0;\n            opcode <= mem_read_value;\n            state <= is_data_opcode(mem_read_value) ? StateFetchData : StateExecute;\n          end\n        end\n        StateFetchData: begin\n          // Read data for instruction from either code or data memory\n          mem_select <= 1;\n          mem_type_data <= (opcode == \"r\") ? 1'b1 : 1'b0;\n          mem_addr <= stack_top;\n          mem_write_en <= 0;\n          if (mem_select && mem_data_ready) begin\n            mem_select <= 0;\n            memory_input <= mem_read_value;\n            state <= StateExecute;\n          end\n        end\n        StateExecute: begin\n          // Execute a single instruction\n          pc <= next_pc;\n          sp <= next_sp;\n          mem_type_data <= memory_write_type_data;\n          mem_addr <= memory_write_addr;\n          mem_write_value <= memory_write_data;\n          if (stack_write_count == 1 || stack_write_count == 2) begin\n            stack[next_sp-1] <= set_stack_top;\n          end\n          if (stack_write_count == 2) begin\n            stack[next_sp-2] <= set_stack_belowtop;\n          end\n          if (memory_write_en) begin\n            state <= StateStore;\n          end else if (stop || single_step) begin\n            state <= StateStop;\n          end else if (sleep) begin\n            state <= StateSleep;\n          end else if (delay_amount != 8'b0 && cycles_per_ms != 24'b0) begin\n            delay_counter <= delay_amount - 1;\n            delay_cycles <= 0;\n            state <= StateDelay;\n          end else begin\n            state <= StateFetch;\n          end\n        end\n        StateStore: begin\n          // Store data from instruction into either code or data memory\n          mem_select   <= 1;\n          mem_write_en <= 1;\n          if (mem_data_ready) begin\n            mem_select <= 0;\n            mem_write_en <= 0;\n            state <= single_step ? StateSleep : StateFetch;\n          end\n        end\n        StateSleep: begin\n          // The only way to leave this state is via external intervention.\n        end\n        StateStop: begin\n          // The only way to leave this state is via external intervention.\n        end\n        StateDelay: begin\n          if (delay_cycles + 1 >= cycles_per_ms) begin\n            delay_counter <= delay_counter - 1;\n            delay_cycles  <= 0;\n            if (delay_counter == 0) begin\n              state <= single_step ? StateSleep : StateFetch;\n            end\n          end else begin\n            delay_cycles <= delay_cycles + 1;\n          end\n        end\n        default: state <= 3'bx;\n      endcase\n    end\n  end\n\n`ifdef FORMAL\n  reg f_init = 1;\n  always @(posedge clk) begin\n    if (f_init) assume (~rst_n);\n    if (rst_n) begin\n      assert (!sleep || !stop);\n      assert(\n        state == StateFetch ||\n        state == StateFetchData ||\n        state == StateExecute ||\n        state == StateStore ||\n        state == StateDelay ||\n        state == StateSleep ||\n        state == StateStop\n      );\n      if (state == StateDelay) begin\n        assume (cycles_per_ms > 0);\n        assert (delay_counter != 8'hff);\n        assert (delay_cycles < cycles_per_ms);\n      end\n      if (state != StateFetch && state != StateFetchData && state != StateStore) begin\n        assert (!mem_select);\n      end\n      if (state != StateStore) begin\n        assert (!mem_write_en);\n      end\n    end\n    f_init <= 0;\n  end\n`endif  /* FORMAL */\n\nendmodule\n\n\n// SPDX-FileCopyrightText: © 2021 Uri Shaked <uri@wokwi.com>\n// SPDX-License-Identifier: MIT\n\n`default_nettype none\n\nmodule spell_execute (\n    input wire [7:0] opcode,\n    input wire [7:0] pc,\n    input wire [4:0] sp,\n    input wire [7:0] stack_top,\n    input wire [7:0] stack_belowtop,\n    input wire [7:0] memory_input,\n    input wire out_of_order_exec,\n    output reg [7:0] next_pc,\n    output reg [4:0] next_sp,\n    output reg [1:0] stack_write_count,\n    output reg [7:0] set_stack_top,\n    output reg [7:0] set_stack_belowtop,\n    output reg memory_write_en,\n    output reg memory_write_type_data,\n    output reg [7:0] memory_write_data,\n    output reg [7:0] memory_write_addr,\n    output reg [7:0] delay_amount,\n    output reg sleep,\n    output reg stop\n);\n\n  always @(*) begin\n    next_pc = out_of_order_exec ? pc : pc + 8'd1;\n    next_sp = sp;\n    stack_write_count = 2'd0;\n    set_stack_top = 8'dx;\n    set_stack_belowtop = 8'dx;\n    memory_write_en = 1'b0;\n    memory_write_type_data = 1'b0;\n    memory_write_addr = 8'dx;\n    memory_write_data = 8'dx;\n    sleep = 0;\n    stop = 0;\n    delay_amount = 0;\n\n    case (opcode)\n      \"+\": begin\n        set_stack_top = stack_belowtop + stack_top;\n        stack_write_count = 1;\n        next_sp = sp - 1;\n      end\n      \"-\": begin\n        set_stack_top = stack_belowtop - stack_top;\n        stack_write_count = 1;\n        next_sp = sp - 1;\n      end\n      \"&\": begin\n        set_stack_top = stack_belowtop & stack_top;\n        stack_write_count = 1;\n        next_sp = sp - 1;\n      end\n      \"^\": begin\n        set_stack_top = stack_belowtop ^ stack_top;\n        stack_write_count = 1;\n        next_sp = sp - 1;\n      end\n      \"|\": begin\n        set_stack_top = stack_belowtop | stack_top;\n        stack_write_count = 1;\n        next_sp = sp - 1;\n      end\n      \">\": begin\n        set_stack_top = {1'b0, stack_top[7:1]};\n        stack_write_count = 1;\n      end\n      \"<\": begin\n        set_stack_top = {stack_top[6:0], 1'b0};\n        stack_write_count = 1;\n      end\n      \"=\": begin\n        next_pc = stack_top;\n        next_sp = sp - 1;\n      end\n      \"@\": begin\n        if (stack_belowtop != 8'd0) begin\n          next_pc = stack_top;\n          next_sp = sp - 1;\n          set_stack_top = stack_belowtop - 1;\n          stack_write_count = 1;\n        end else begin\n          next_sp = sp - 2;\n        end\n      end\n      \",\": begin\n        delay_amount = stack_top;\n        next_sp = sp - 1;\n      end\n      \"2\": begin\n        set_stack_top = stack_top;\n        stack_write_count = 1;\n        next_sp = sp + 1;\n      end\n      \"!\": begin\n        memory_write_en = 1'b1;\n        memory_write_type_data = 1'b0;\n        memory_write_addr = stack_top;\n        memory_write_data = stack_belowtop;\n        next_sp = sp - 2;\n      end\n      \"?\", \"r\": begin\n        set_stack_top = memory_input;\n        stack_write_count = 1;\n      end\n      \"w\": begin\n        memory_write_en = 1'b1;\n        memory_write_type_data = 1'b1;\n        memory_write_addr = stack_top;\n        memory_write_data = stack_belowtop;\n        next_sp = sp - 2;\n      end\n      \"x\": begin\n        set_stack_top = stack_belowtop;\n        set_stack_belowtop = stack_top;\n        stack_write_count = 2;\n      end\n      \"z\":   sleep = 1'b1;\n      8'hff: stop = 1'b1;\n      default: begin\n        set_stack_top = opcode;\n        stack_write_count = 1;\n        next_sp = sp + 1;\n      end\n    endcase\n  end\nendmodule\n\n\n// SPDX-FileCopyrightText: © 2021 Uri Shaked <uri@wokwi.com>\n// SPDX-License-Identifier: MIT\n\n`default_nettype none\n\nmodule spell_mem (\n    input wire rst_n,\n    input wire clk,\n    input wire select,\n    input wire [7:0] addr,\n    input wire [7:0] data_in,\n    input wire memory_type_data,\n    input wire write,\n    output reg [7:0] data_out,\n    output wire data_ready,\n\n    /* IO */\n    output wire [7:0] porta_out,\n    output wire [7:0] porta_oe, // out enable\n    input  wire [7:0] portb_in,\n    output wire [7:0] portb_out,\n    output wire [7:0] portb_oe  // out enable\n);\n\n  wire code_select = select && !memory_type_data;\n\n  wire data_select = select && memory_type_data;\n  wire data_mem_select = data_select && (addr < 8'h20 || addr >= 8'h60);\n  wire data_io_select = data_select && (addr >= 8'h20 && addr < 8'h60);\n\n  wire mem_select = code_select || data_mem_select;\n\n  wire io_data_ready;\n  wire internal_data_ready;\n  assign data_ready = io_data_ready | internal_data_ready;\n\n  wire [7:0] io_data_out;\n  wire [7:0] internal_data_out;\n\n  spell_mem_io mem_io (\n      .rst_n(rst_n),\n      .clk(clk),\n      .select(data_io_select),\n      .addr(addr),\n      .data_in(data_in),\n      .write(write),\n      .data_out(io_data_out),\n      .data_ready(io_data_ready),\n\n      /* IO */\n      .porta_out(porta_out),\n      .porta_oe(porta_oe),\n      .portb_in (portb_in),\n      .portb_out(portb_out),\n      .portb_oe(portb_oe)\n  );\n\n  spell_mem_internal mem_internal (\n      .rst_n(rst_n),\n      .clk(clk),\n      .select(mem_select),\n      .addr(addr),\n      .data_in(data_in),\n      .memory_type_data(memory_type_data),\n      .write(write),\n      .data_out(internal_data_out),\n      .data_ready(internal_data_ready)\n  );\n\n  always @(*) begin\n    if (data_io_select) begin\n      data_out = io_data_out;\n    end else begin\n      data_out = internal_data_out;\n    end\n  end\n\nendmodule\n\n\n// SPDX-FileCopyrightText: © 2021-2024 Uri Shaked <uri@wokwi.com>\n// SPDX-License-Identifier: MIT\n\n`default_nettype none\n\nmodule spell_mem_internal (\n    input wire rst_n,\n    input wire clk,\n    input wire select,\n    input wire [7:0] addr,\n    input wire [7:0] data_in,\n    input wire memory_type_data,\n    input wire write,\n    output wire [7:0] data_out,\n    output reg data_ready\n);\n\n  localparam data_mem_size = 32;\n\n  wire code_mem_lo_sel = !memory_type_data && addr[7] == 1'b0;\n  wire code_mem_hi_sel = !memory_type_data && addr[7] == 1'b1;\n\n  reg code_mem_ready;\n  reg [4:0] code_mem_init_addr;\n\n  wire [4:0] code_mem_addr = code_mem_ready ? addr[6:2] : code_mem_init_addr;\n  wire [31:0] code_mem_lo_do;\n  wire [31:0] code_mem_hi_do;\n  wire [31:0] code_mem_di = code_mem_ready ? {data_in, data_in, data_in, data_in} : 32'hffffffff;\n  wire [31:0] code_mem_do = code_mem_lo_sel ? code_mem_lo_do : code_mem_hi_do;\n\n  wire [4:0] word_index = {addr[1:0], 3'b000};\n  wire [7:0] code_mem_out = code_mem_do[word_index+:8];\n  reg [7:0] data_mem_out;\n  wire [7:0] data_out_byte = memory_type_data ? data_mem_out : code_mem_out;\n  assign data_out = data_ready ? data_out_byte : 8'bx;\n\n\n  wire we = select && write;\n  wire [3:0] we_sel = we ? (1 << addr[1:0]) : 0;\n  wire [3:0] code_mem_we0 = code_mem_ready ? we_sel : 4'b1111;\n\n  RAM32 code_mem_lo (\n      .CLK(clk),\n      .EN0(rst_n),\n      .WE0(code_mem_lo_sel || !code_mem_ready ? code_mem_we0 : 4'b0000),\n      .A0 (code_mem_addr),\n      .Di0(code_mem_di),\n      .Do0(code_mem_lo_do)\n  );\n\n  RAM32 code_mem_hi (\n      .CLK(clk),\n      .EN0(rst_n),\n      .WE0(code_mem_hi_sel || !code_mem_ready ? code_mem_we0 : 4'b0000),\n      .A0 (code_mem_addr),\n      .Di0(code_mem_di),\n      .Do0(code_mem_hi_do)\n  );\n\n  localparam data_mem_bits = $clog2(data_mem_size);\n  reg [7:0] data_mem[data_mem_size-1:0];\n  wire [data_mem_bits-1:0] data_addr = addr[data_mem_bits-1:0];\n\n  reg [1:0] cycles;\n\n  integer i;\n\n  always @(posedge clk) begin\n    if (~rst_n) begin\n      cycles <= 0;\n      data_ready <= 0;\n      data_mem_out <= 0;\n      for (i = 0; i < data_mem_size; i++) data_mem[i] <= 8'h00;\n      code_mem_ready <= 0;\n      code_mem_init_addr <= 0;\n    end else begin\n      if (!code_mem_ready) begin\n        code_mem_init_addr <= code_mem_init_addr + 1;\n        if (code_mem_init_addr == 5'b11111) begin\n          code_mem_ready <= 1;\n        end\n      end else if (!select) begin\n        data_ready <= 1'b0;\n`ifdef SPELL_INTERNAL_MEM_DELAY\n        cycles <= 2'b11;\n`endif  /* SPELL_INTERNAL_MEM_DELAY */\n      end else if (cycles > 0) begin\n        cycles <= cycles - 1;\n      end else begin\n        data_ready <= 1'b1;\n        if (write) begin\n          if (memory_type_data && addr < data_mem_size) begin\n            data_mem[data_addr] <= data_in;\n          end\n        end else begin\n          data_mem_out <= 8'h00;\n          if (memory_type_data && addr < data_mem_size) begin\n            data_mem_out <= data_mem[data_addr];\n          end\n        end\n      end\n    end\n  end\nendmodule\n\n\n// SPDX-FileCopyrightText: © 2021 Uri Shaked <uri@wokwi.com>\n// SPDX-License-Identifier: MIT\n\n`default_nettype none\n\nmodule spell_mem_io (\n    input wire rst_n,\n    input wire clk,\n    input wire select,\n    input wire [7:0] addr,\n    input wire [7:0] data_in,\n    input wire write,\n    output reg [7:0] data_out,\n    output reg data_ready,\n\n    /* porta */\n    output reg [7:0] porta_out,\n    output reg [7:0] porta_oe,   // out enable (active high)\n\n    /* porta */\n    input  wire [7:0] portb_in,\n    output reg  [7:0] portb_out,\n    output reg  [7:0] portb_oe    // out enable (active high)\n);\n\n  localparam REG_PINB = 8'h36;\n  localparam REG_DDRB = 8'h37;\n  localparam REG_PORTB = 8'h38;\n  localparam REG_PINA = 8'h39;\n  localparam REG_DDRA = 8'h3a;\n  localparam REG_PORTA = 8'h3b;\n\n  reg past_write;\n\n  always @(posedge clk) begin\n    if (~rst_n) begin\n      porta_out  <= 8'b00000000;\n      porta_oe   <= 8'b00000000;\n      portb_out  <= 8'b00000000;\n      portb_oe   <= 8'b00000000;\n      data_out   <= 8'b0;\n      data_ready <= 1'b0;\n      past_write <= 1'b0;\n    end else begin\n      past_write <= select & write;\n      if (select) begin\n        data_out   <= 8'b0;\n        data_ready <= 1'b1;\n\n        case (addr)\n          REG_PINB: begin\n            if (write) begin\n              if (~past_write) portb_out <= portb_out ^ data_in;\n            end else begin\n              data_out <= portb_in;\n            end\n          end\n          REG_DDRB: begin\n            if (write) begin\n              portb_oe <= data_in;\n            end else begin\n              data_out <= portb_oe;\n            end\n          end\n          REG_PORTB: begin\n            if (write) begin\n              portb_out <= data_in;\n            end else begin\n              data_out <= portb_out;\n            end\n          end\n          REG_PINA: begin\n            if (write) begin\n              if (~past_write) porta_out <= porta_out ^ data_in;\n            end else begin\n              data_out <= 8'h00;\n            end\n          end\n          REG_DDRA: begin\n            if (write) begin\n              porta_oe <= data_in;\n            end else begin\n              data_out <= porta_oe;\n            end\n          end\n          REG_PORTA: begin\n            if (write) begin\n              porta_out <= data_in;\n            end else begin\n              data_out <= porta_out;\n            end\n          end\n          default: begin\n            if (~write) data_out <= 8'hff;\n          end\n        endcase\n      end else data_ready <= 1'b0;\n    end\n  end\nendmodule\n\n\n/// sta-blackbox\n\n`default_nettype none\n\nmodule RAM32 (\n`ifdef USE_POWER_PINS\n    input VPWR,\n    input VGND,\n`endif\n    input CLK,\n    input [3:0] WE0,\n    input EN0,\n    input [4:0] A0,\n    input [31:0] Di0,\n    output reg [31:0] Do0\n);\n  reg [31:0] RAM[31:0];\n\n  always @(posedge CLK)\n    if (EN0) begin\n      Do0 <= RAM[A0];\n      if (WE0[0]) RAM[A0][7:0] <= Di0[7:0];\n      if (WE0[1]) RAM[A0][15:8] <= Di0[15:8];\n      if (WE0[2]) RAM[A0][23:16] <= Di0[23:16];\n      if (WE0[3]) RAM[A0][31:24] <= Di0[31:24];\n    end else begin\n      Do0 <= 32'b0;\n    end\n\nendmodule\n", "mask_idx": {"conditional_statement": [[17236, 18031], [7135, 7255], [8598, 8705], [20895, 21164]], "blocking_assignment": [[12946, 12959], [13078, 13095], [4396, 4462], [3164, 3182], [11043, 11065], [12973, 12985], [11127, 11170], [2887, 2908], [10938, 10955], [3002, 3025], [14913, 14936], [2716, 2737]], "module_program_interface_instantiation": [[16563, 16775], [16347, 16559], [3914, 4335]], "always_construct": [[16972, 18045], [10464, 13123], [18867, 20590]], "case_statement": [[5592, 5796], [10816, 13117], [6002, 8848]], "ansi_port_declaration": [[18201, 18218], [18266, 18288], [304, 351], [13368, 13393]], "continuous_assign": [[1176, 1299], [14067, 14123], [16148, 16200]], "nonblocking_assignment": [[5964, 5984], [4796, 4854], [7087, 7124], [4861, 4879], [5627, 5643]]}, "all_mask_idx": {"module_program_interface_instantiation": [[3248, 3910], [3914, 4335], [14186, 14565], [14569, 14855], [16347, 16559], [16563, 16775]], "continuous_assign": [[1176, 1299], [14067, 14123], [16148, 16200]], "blocking_assignment": [[2716, 2737], [2760, 2784], [2805, 2828], [2847, 2868], [2887, 2908], [2927, 2948], [2966, 2986], [3002, 3025], [3100, 3116], [3131, 3147], [3164, 3182], [3204, 3226], [4396, 4462], [10486, 10531], [10536, 10549], [10554, 10579], [10584, 10605], [10610, 10636], [10641, 10664], [10669, 10699], [10704, 10729], [10734, 10759], [10764, 10774], [10779, 10788], [10793, 10810], [10855, 10898], [10907, 10929], [10938, 10955], [10991, 11034], [11043, 11065], [11074, 11091], [11127, 11170], [11179, 11201], [11210, 11227], [11263, 11306], [11315, 11337], [11346, 11363], [11399, 11442], [11451, 11473], [11482, 11499], [11535, 11574], [11583, 11605], [11641, 11680], [11689, 11711], [11747, 11767], [11776, 11793], [11873, 11893], [11904, 11921], [11932, 11967], [11978, 12000], [12034, 12051], [12099, 12124], [12133, 12150], [12186, 12212], [12221, 12243], [12252, 12269], [12305, 12328], [12337, 12367], [12376, 12406], [12415, 12450], [12459, 12476], [12517, 12546], [12555, 12577], [12613, 12636], [12645, 12675], [12684, 12714], [12723, 12758], [12767, 12784], [12820, 12851], [12860, 12891], [12900, 12922], [12946, 12959], [12973, 12985], [13015, 13038], [13047, 13069], [13078, 13095], [14913, 14936], [14962, 14991]], "nonblocking_assignment": [[4566, 4586], [4593, 4604], [4611, 4622], [4654, 4668], [4675, 4687], [4694, 4710], [4717, 4735], [4742, 4759], [4766, 4789], [4796, 4854], [4861, 4879], [4886, 4901], [4908, 4925], [4932, 4948], [4974, 5018], [5025, 5053], [5060, 5081], [5150, 5166], [5185, 5206], [5245, 5265], [5278, 5345], [5358, 5375], [5388, 5411], [5469, 5492], [5505, 5518], [5627, 5643], [5662, 5688], [5709, 5729], [5755, 5780], [5901, 5923], [5932, 5955], [5964, 5984], [6103, 6119], [6130, 6149], [6160, 6175], [6186, 6204], [6267, 6283], [6296, 6321], [6334, 6406], [6544, 6560], [6571, 6618], [6629, 6651], [6662, 6680], [6743, 6759], [6772, 6803], [6816, 6838], [6945, 6959], [6970, 6984], [6995, 7035], [7046, 7076], [7087, 7124], [7207, 7241], [7312, 7351], [7415, 7435], [7498, 7517], [7566, 7586], [7676, 7710], [7723, 7741], [7754, 7774], [7812, 7832], [7968, 7986], [7997, 8015], [8064, 8080], [8093, 8111], [8124, 8171], [8518, 8553], [8566, 8585], [8642, 8689], [8743, 8776], [8820, 8834], [17028, 17040], [17047, 17063], [17070, 17088], [17131, 17152], [17159, 17179], [17186, 17210], [17271, 17316], [17377, 17397], [17452, 17471], [17613, 17634], [17664, 17683], [17783, 17814], [17862, 17884], [17959, 17995], [18923, 18949], [18956, 18982], [18989, 19015], [19022, 19048], [19055, 19074], [19081, 19100], [19107, 19126], [19152, 19181], [19214, 19233], [19242, 19261], [19369, 19402], [19444, 19465], [19565, 19585], [19627, 19648], [19749, 19770], [19812, 19834], [19951, 19984], [20026, 20044], [20144, 20164], [20206, 20227], [20328, 20349], [20391, 20413], [20493, 20511], [20557, 20576], [20916, 20931], [20950, 20975], [20994, 21021], [21040, 21069], [21088, 21117], [21143, 21156]], "case_statement": [[2685, 3037], [3069, 3238], [5115, 5548], [5592, 5796], [6002, 8848], [10816, 13117], [19271, 20541]], "conditional_statement": [[4542, 8856], [5089, 5558], [5566, 5806], [5814, 5994], [6215, 6420], [6691, 6852], [7135, 7255], [7266, 7365], [7376, 7846], [7455, 7846], [7537, 7846], [7606, 7846], [8026, 8185], [8461, 8790], [8598, 8705], [11829, 12063], [14881, 14999], [17004, 18039], [17236, 18031], [17325, 17409], [17425, 18031], [17583, 18031], [17692, 18021], [17719, 17828], [17895, 18009], [18899, 20584], [19188, 20576], [19321, 19481], [19352, 19402], [19534, 19664], [19718, 19850], [19903, 20060], [19934, 19984], [20113, 20243], [20297, 20429], [20481, 20511], [20895, 21164], [20938, 20975], [20982, 21021], [21028, 21069], [21076, 21117]], "always_construct": [[2663, 3043], [3047, 3244], [4510, 8862], [10464, 13123], [14859, 15005], [16972, 18045], [18867, 20590], [20869, 21164]], "parameter_declaration": [], "ansi_port_declaration": [[148, 195], [200, 248], [253, 299], [304, 351], [356, 436], [441, 511], [516, 552], [557, 610], [9840, 9864], [9869, 9889], [9894, 9914], [9919, 9946], [9951, 9983], [9988, 10018], [10023, 10052], [10057, 10082], [10087, 10112], [10117, 10152], [10157, 10188], [10193, 10229], [10234, 10261], [10266, 10300], [10305, 10340], [10345, 10380], [10385, 10415], [10420, 10437], [10442, 10457], [13276, 13293], [13298, 13313], [13318, 13336], [13341, 13363], [13368, 13393], [13398, 13426], [13431, 13448], [13453, 13479], [13484, 13507], [13526, 13554], [13559, 13600], [13605, 13632], [13637, 13665], [13670, 13711], [15173, 15190], [15195, 15210], [15215, 15233], [15238, 15260], [15265, 15290], [15295, 15323], [15328, 15345], [15350, 15377], [15382, 15403], [18201, 18218], [18223, 18238], [18243, 18261], [18266, 18288], [18293, 18318], [18323, 18340], [18345, 18371], [18376, 18398], [18420, 18447], [18452, 18508], [18530, 18557], [18562, 18590], [18595, 18652], [20724, 20734], [20739, 20755], [20760, 20770], [20775, 20790], [20795, 20812], [20817, 20838]]}}
{"sample_i": "vicvicvarunis-tt_unis_nano_24", "topmodule": "tt_um_unisnano", "code": "\n\n\nmodule tt_um_unisnano\n\n(\n\tinput wire [7:0] ui_in, // Dedicated inputs\n\toutput wire [7:0] uo_out, // Dedicated outputs\n\tinput wire [7:0] uio_in, // IOs: Input path\n\toutput wire [7:0] uio_out, // IOs: Output path\n\toutput wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)\n\tinput wire ena, // always 1 when the design is powered, so you can ignore it\n\tinput wire clk, // clock\n\tinput wire rst_n // reset_n - low to reset\n\n);\n\n   \n\treg output1,output2;\n\twire rx,tx;\n\tassign rx=ui_in[3];\n\tassign uo_out[0]=1'b0;\n\tassign uo_out[1]=output1;\n\tassign uo_out[2]=output2;\n\tassign uo_out[3]=1'b0;\n\tassign uo_out[4]=tx;\n\tassign uo_out[5]=1'b0;\n\tassign uo_out[6]=1'b0;\n\tassign uo_out[7]=1'b0;\n\t\n\tassign uio_out = 8'b00000000;\n\tassign uio_oe = 8'b00000000;\n  \n  \n  \n//  wire rst_n;\n//  assign rst_n=!reset;\n  \n   reg tx_start=0;\n   \n   wire tick, rx_done_tick, tx_done_tick;\n   \n   wire [7:0] rx_data_out;\n   wire [7:0]  dout_rom;\n   reg [29:0] counter=0;\n  \n   \n   \n   reg [3:0] state=0;\n  \n  reg[7:0] din;\n  reg [9:0] addr,start_addr,stop_addr;\n  \n   mod_m_counter #(.M(27), .N(10)) baud_gen_unit\n      (.clk(clk), .reset(!rst_n), .q(), .max_tick(tick));\n      \n   uart_rx #(.DBIT(8), .SB_TICK(16)) uart_rx_unit\n      (.clk(clk), .reset(!rst_n), .rx(rx), .s_tick(tick),\n       .rx_done_tick(rx_done_tick), .dout(rx_data_out));\n\n   uart_tx #(.DBIT(8), .SB_TICK(16)) uart_tx_unit\n      (.clk(clk), .reset(!rst_n), .tx_start(tx_start),\n       .s_tick(tick), .din(din),\n       .tx_done_tick(tx_done_tick), .tx(tx) );\n\n\n\n    menu_rom menu_rom(\n    .clk(clk), .addr(addr) ,.dout(dout_rom) ) ;\n\n\n   \n \n\n     always @(posedge clk)\n        begin\n            if(!rst_n)//reset is needed\n                begin \n                    state<=0;    \n                    \n                end        \n            else\n                begin\n                    case(state)//parse every incoming word in real time\n                        4'd0://IDLE state, waiting here all the time\n                            begin\n                                counter<=0;\n                                addr<=0;\n                                state<=state+1;  \n                                start_addr<=0;\n                                stop_addr<=97;\n                            end\n                        4'd1:\n                            begin   \n                                state<=state+1;\n                            end\n                        4'd2:\n                            begin\n                                din<=dout_rom;\n                                state<=state+1;\n                                \n                            end\n                        4'd3:\n                            begin\n                                tx_start<=1;\n                                state<=state+1;\n                                                     \n                            end\n                        4'd4:\n                            begin   \n                                state<=state+1;\n                                counter<=0;\n                            end\n                            \n                        4'd5:\n                            begin\n                                tx_start<=0;        \n                                if(tx_done_tick)\n                                    state<=state+1;    \n                                else if(counter<100000000)\n                                    counter<=counter+1;\n                                else\n                                    state<=0;\n                                                   \n                            end\n                        4'd6:\n                            begin\n                                counter<=0;\n                                if(addr>=stop_addr) \n                                    begin\n                                        state<=state+1;   \n                                    end\n                                else\n                                    begin\n                                        state<=1;\n                                        addr<=addr+1;\n                                    end\n                            \n                            end\n                        4'd7:\n                            begin\n                                if(rx_done_tick)\n                                    begin\n                                        \n                                        if(rx_data_out==49)// 1\n                                            begin\n                                                start_addr<=98;\n                                                stop_addr<=105;\n                                                state<=state+1;\n                                            end\n                                        else if(rx_data_out==50)// 2\n                                            begin\n                                                start_addr<=106;\n                                                stop_addr<=162;\n                                                state<=state+1;\n                                            end\n                                        else if(rx_data_out==51)// 3\n                                            begin\n                                                start_addr<=163;\n                                                stop_addr<=192;\n                                                state<=state+1;\n                                            end\n\n                                        else if(rx_data_out==52)// 4\n                                            begin\n                                                output1<=!output1;\n                                                state<=0;\n                                            end\n                                        else if(rx_data_out==53)// 5\n                                            begin\n                                                output2<=!output2;\n                                                state<=0;\n                                            end \n                                        else\n                                            state<=0;\n                                    end  \n                                end  \n                        4'd8:\n                            begin\n                                addr<=start_addr;\n                                state<=state+1;\n                            end\n                        4'd9:\n                            begin   \n                                state<=state+1;\n                            end\n                        4'd10:\n                            begin\n                                din<=dout_rom;\n                                state<=state+1;\n                                \n                            end\n                        4'd11:\n                            begin\n                                tx_start<=1;\n                                state<=state+1;\n                                                     \n                            end\n                        4'd12:\n                            begin   \n                                state<=state+1;\n                                counter<=0;\n                            end\n                            \n                        4'd13:\n                            begin\n                                tx_start<=0;        \n                                if(tx_done_tick)\n                                    state<=state+1; \n                                else if(counter<100000000)\n                                    counter<=counter+1;\n                                else\n                                    state<=0;             \n                            end\n                            \n                        4'd14:\n                            begin\n                                if(addr>=stop_addr) \n                                    begin\n                                        state<=0;   \n                                    end\n                                else\n                                    begin\n                                        state<=9;\n                                        addr<=addr+1;\n                                    end\n                            \n                            end\n                        default:\n                            begin\n                                state<=0;\n                            end\n                    endcase\n                end\n        end\n        \n        \n  \n           \nendmodule\n\nmodule menu_rom(\ninput clk,\ninput [9:0] addr,\noutput reg [7:0] dout ) ; \n\n\n\nalways @ (posedge clk) begin\n   case(addr) \n         0 : begin\n             dout <= 83;   end \n         1 : begin\n             dout <= 111;   end \n         2 : begin\n             dout <= 121;   end \n         3 : begin\n             dout <= 32;   end \n         4 : begin\n             dout <= 110;   end \n         5 : begin\n             dout <= 97;   end \n         6 : begin\n             dout <= 110;   end \n         7 : begin\n             dout <= 111;   end \n         8 : begin\n             dout <= 32;   end \n         9 : begin\n             dout <= 101;   end \n         10 : begin\n             dout <= 108;   end \n         11 : begin\n             dout <= 32;   end \n         12 : begin\n             dout <= 112;   end \n         13 : begin\n             dout <= 114;   end \n         14 : begin\n             dout <= 105;   end \n         15 : begin\n             dout <= 109;   end \n         16 : begin\n             dout <= 101;   end \n         17 : begin\n             dout <= 114;   end \n         18 : begin\n             dout <= 32;   end \n         19 : begin\n             dout <= 65;   end \n         20 : begin\n             dout <= 83;   end \n         21 : begin\n             dout <= 73;   end \n         22 : begin\n             dout <= 67;   end \n         23 : begin\n             dout <= 32;   end \n         24 : begin\n             dout <= 100;   end \n         25 : begin\n             dout <= 105;   end \n         26 : begin\n             dout <= 115;   end \n         27 : begin\n             dout <= 101;   end \n         28 : begin\n             dout <= 110;   end \n         29 : begin\n             dout <= 97;   end \n         30 : begin\n             dout <= 100;   end \n         31 : begin\n             dout <= 111;   end \n         32 : begin\n             dout <= 32;   end \n         33 : begin\n             dout <= 101;   end \n         34 : begin\n             dout <= 110;   end \n         35 : begin\n             dout <= 32;   end \n         36 : begin\n             dout <= 71;   end \n         37 : begin\n             dout <= 117;   end \n         38 : begin\n             dout <= 97;   end \n         39 : begin\n             dout <= 116;   end \n         40 : begin\n             dout <= 101;   end \n         41 : begin\n             dout <= 109;   end \n         42 : begin\n             dout <= 97;   end \n         43 : begin\n             dout <= 108;   end \n         44 : begin\n             dout <= 97;   end \n         45 : begin\n             dout <= 13;   end \n         46 : begin\n             dout <= 10;   end \n         47 : begin\n             dout <= 49;   end \n         48 : begin\n             dout <= 32;   end \n         49 : begin\n             dout <= 67;   end \n         50 : begin\n             dout <= 114;   end \n         51 : begin\n             dout <= 101;   end \n         52 : begin\n             dout <= 97;   end \n         53 : begin\n             dout <= 100;   end \n         54 : begin\n             dout <= 111;   end \n         55 : begin\n             dout <= 114;   end \n         56 : begin\n             dout <= 101;   end \n         57 : begin\n             dout <= 115;   end \n         58 : begin\n             dout <= 13;   end \n         59 : begin\n             dout <= 10;   end \n         60 : begin\n             dout <= 50;   end \n         61 : begin\n             dout <= 32;   end \n         62 : begin\n             dout <= 80;   end \n         63 : begin\n             dout <= 111;   end \n         64 : begin\n             dout <= 114;   end \n         65 : begin\n             dout <= 32;   end \n         66 : begin\n             dout <= 113;   end \n         67 : begin\n             dout <= 117;   end \n         68 : begin\n             dout <= 101;   end \n         69 : begin\n             dout <= 13;   end \n         70 : begin\n             dout <= 10;   end \n         71 : begin\n             dout <= 51;   end \n         72 : begin\n             dout <= 32;   end \n         73 : begin\n             dout <= 70;   end \n         74 : begin\n             dout <= 114;   end \n         75 : begin\n             dout <= 97;   end \n         76 : begin\n             dout <= 115;   end \n         77 : begin\n             dout <= 101;   end \n         78 : begin\n             dout <= 13;   end \n         79 : begin\n             dout <= 10;   end \n         80 : begin\n             dout <= 52;   end \n         81 : begin\n             dout <= 32;   end \n         82 : begin\n             dout <= 65;   end \n         83 : begin\n             dout <= 49;   end \n         84 : begin\n             dout <= 13;   end \n         85 : begin\n             dout <= 10;   end \n         86 : begin\n             dout <= 53;   end \n         87 : begin\n             dout <= 32;   end \n         88 : begin\n             dout <= 65;   end \n         89 : begin\n             dout <= 50;   end \n         90 : begin\n             dout <= 13;   end \n         91 : begin\n             dout <= 10;   end \n         92 : begin\n             dout <= 13;   end \n         93 : begin\n             dout <= 10;   end \n         94 : begin\n             dout <= 13;   end \n         95 : begin\n             dout <= 10;   end \n         96 : begin\n             dout <= 13;   end \n         97 : begin\n             dout <= 10;   end \n         98 : begin\n             dout <= 85;   end \n         99 : begin\n             dout <= 78;   end \n         100 : begin\n             dout <= 73;   end \n         101 : begin\n             dout <= 83;   end \n         102 : begin\n             dout <= 50;   end \n         103 : begin\n             dout <= 52;   end \n         104 : begin\n             dout <= 13;   end \n         105 : begin\n             dout <= 10;   end \n         106 : begin\n             dout <= 83;   end \n         107 : begin\n             dout <= 111;   end \n         108 : begin\n             dout <= 121;   end \n         109 : begin\n             dout <= 32;   end \n         110 : begin\n             dout <= 117;   end \n         111 : begin\n             dout <= 110;   end \n         112 : begin\n             dout <= 32;   end \n         113 : begin\n             dout <= 104;   end \n         114 : begin\n             dout <= 105;   end \n         115 : begin\n             dout <= 116;   end \n         116 : begin\n             dout <= 111;   end \n         117 : begin\n             dout <= 32;   end \n         118 : begin\n             dout <= 105;   end \n         119 : begin\n             dout <= 109;   end \n         120 : begin\n             dout <= 112;   end \n         121 : begin\n             dout <= 111;   end \n         122 : begin\n             dout <= 114;   end \n         123 : begin\n             dout <= 116;   end \n         124 : begin\n             dout <= 97;   end \n         125 : begin\n             dout <= 110;   end \n         126 : begin\n             dout <= 116;   end \n         127 : begin\n             dout <= 101;   end \n         128 : begin\n             dout <= 32;   end \n         129 : begin\n             dout <= 101;   end \n         130 : begin\n             dout <= 110;   end \n         131 : begin\n             dout <= 32;   end \n         132 : begin\n             dout <= 108;   end \n         133 : begin\n             dout <= 97;   end \n         134 : begin\n             dout <= 32;   end \n         135 : begin\n             dout <= 99;   end \n         136 : begin\n             dout <= 105;   end \n         137 : begin\n             dout <= 101;   end \n         138 : begin\n             dout <= 110;   end \n         139 : begin\n             dout <= 99;   end \n         140 : begin\n             dout <= 105;   end \n         141 : begin\n             dout <= 97;   end \n         142 : begin\n             dout <= 32;   end \n         143 : begin\n             dout <= 121;   end \n         144 : begin\n             dout <= 32;   end \n         145 : begin\n             dout <= 116;   end \n         146 : begin\n             dout <= 101;   end \n         147 : begin\n             dout <= 99;   end \n         148 : begin\n             dout <= 110;   end \n         149 : begin\n             dout <= 111;   end \n         150 : begin\n             dout <= 108;   end \n         151 : begin\n             dout <= 111;   end \n         152 : begin\n             dout <= 103;   end \n         153 : begin\n             dout <= 105;   end \n         154 : begin\n             dout <= 97;   end \n         155 : begin\n             dout <= 32;   end \n         156 : begin\n             dout <= 100;   end \n         157 : begin\n             dout <= 101;   end \n         158 : begin\n             dout <= 32;   end \n         159 : begin\n             dout <= 71;   end \n         160 : begin\n             dout <= 84;   end \n         161 : begin\n             dout <= 13;   end \n         162 : begin\n             dout <= 10;   end \n         163 : begin\n             dout <= 71;   end \n         164 : begin\n             dout <= 117;   end \n         165 : begin\n             dout <= 97;   end \n         166 : begin\n             dout <= 116;   end \n         167 : begin\n             dout <= 101;   end \n         168 : begin\n             dout <= 109;   end \n         169 : begin\n             dout <= 97;   end \n         170 : begin\n             dout <= 108;   end \n         171 : begin\n             dout <= 97;   end \n         172 : begin\n             dout <= 32;   end \n         173 : begin\n             dout <= 116;   end \n         174 : begin\n             dout <= 117;   end \n         175 : begin\n             dout <= 32;   end \n         176 : begin\n             dout <= 110;   end \n         177 : begin\n             dout <= 111;   end \n         178 : begin\n             dout <= 109;   end \n         179 : begin\n             dout <= 98;   end \n         180 : begin\n             dout <= 114;   end \n         181 : begin\n             dout <= 101;   end \n         182 : begin\n             dout <= 32;   end \n         183 : begin\n             dout <= 105;   end \n         184 : begin\n             dout <= 110;   end \n         185 : begin\n             dout <= 109;   end \n         186 : begin\n             dout <= 111;   end \n         187 : begin\n             dout <= 114;   end \n         188 : begin\n             dout <= 116;   end \n         189 : begin\n             dout <= 97;   end \n         190 : begin\n             dout <= 108;   end \n         191 : begin\n             dout <= 13;   end \n         192 : begin\n             dout <= 10;   end \nendcase \n end \n endmodule\n\n\nmodule mod_m_counter\n   #(\n    parameter N=27, // number of bits in counter\n              M=100000000 // mod-M\n   )\n   (\n    input wire clk, reset,\n    output wire max_tick,\n    output wire [N-1:0] q\n   );\n\n   //signal declaration\n   reg [N-1:0] r_reg;\n   wire [N-1:0] r_next;\n\n   // body\n   // register\n   always @(posedge clk, posedge reset)\n      if (reset)\n         r_reg <= 0;\n      else\n         r_reg <= r_next;\n\n   // next-state logic\n   assign r_next = (r_reg==(M-1)) ? 0 : r_reg + 1;\n   // output logic\n   assign q = r_reg;\n   assign max_tick = (r_reg==(M-1)) ? 1'b1 : 1'b0;\n\nendmodule\n\nmodule uart_rx\n   #(\n     parameter DBIT = 8,     // # data bits\n               SB_TICK = 16  // # ticks for stop bits\n   )\n   (\n    input wire clk, reset,\n    input wire rx, s_tick,\n    output reg rx_done_tick,\n    output wire [7:0] dout\n   );\n\n   // symbolic state declaration\n   localparam [1:0]\n      idle  = 2'b00,\n      start = 2'b01,\n      data  = 2'b10,\n      stop  = 2'b11;\n\n   // signal declaration\n   reg [1:0] state_reg, state_next;\n   reg [3:0] s_reg, s_next;\n   reg [2:0] n_reg, n_next;\n   reg [7:0] b_reg, b_next;\n\n   // body\n   // FSMD state & data registers\n   always @(posedge clk, posedge reset)\n      if (reset)\n         begin\n            state_reg <= idle;\n            s_reg <= 0;\n            n_reg <= 0;\n            b_reg <= 0;\n         end\n      else\n         begin\n            state_reg <= state_next;\n            s_reg <= s_next;\n            n_reg <= n_next;\n            b_reg <= b_next;\n         end\n\n   // FSMD next-state logic\n   always @*\n   begin\n      state_next = state_reg;\n      rx_done_tick = 1'b0;\n      s_next = s_reg;\n      n_next = n_reg;\n      b_next = b_reg;\n      case (state_reg)\n         idle:\n            if (~rx)\n               begin\n                  state_next = start;\n                  s_next = 0;\n               end\n         start:\n            if (s_tick)\n               if (s_reg==7)\n                  begin\n                     state_next = data;\n                     s_next = 0;\n                     n_next = 0;\n                  end\n               else\n                  s_next = s_reg + 1;\n         data:\n            if (s_tick)\n               if (s_reg==15)\n                  begin\n                     s_next = 0;\n                     b_next = {rx, b_reg[7:1]};\n                     if (n_reg==(DBIT-1))\n                        state_next = stop ;\n                      else\n                        n_next = n_reg + 1;\n                   end\n               else\n                  s_next = s_reg + 1;\n         stop:\n            if (s_tick)\n               if (s_reg==(SB_TICK-1))\n                  begin\n                     state_next = idle;\n                     rx_done_tick =1'b1;\n                  end\n               else\n                  s_next = s_reg + 1;\n      endcase\n   end\n   // output\n   assign dout = b_reg;\n\nendmodule\n\nmodule uart_tx\n   #(\n     parameter DBIT = 8,     // # data bits\n               SB_TICK = 16  // # ticks for stop bits\n   )\n   (\n    input wire clk, reset,\n    input wire tx_start, s_tick,\n    input wire [7:0] din,\n    output reg tx_done_tick,\n    output wire tx\n   );\n\n   // symbolic state declaration\n   localparam [1:0]\n      idle  = 2'b00,\n      start = 2'b01,\n      data  = 2'b10,\n      stop  = 2'b11;\n\n   // signal declaration\n   reg [1:0] state_reg, state_next;\n   reg [3:0] s_reg, s_next;\n   reg [2:0] n_reg, n_next;\n   reg [7:0] b_reg, b_next;\n   reg tx_reg, tx_next;\n\n   // body\n   // FSMD state & data registers\n   always @(posedge clk, posedge reset)\n      if (reset)\n         begin\n            state_reg <= idle;\n            s_reg <= 0;\n            n_reg <= 0;\n            b_reg <= 0;\n            tx_reg <= 1'b1;\n         end\n      else\n         begin\n            state_reg <= state_next;\n            s_reg <= s_next;\n            n_reg <= n_next;\n            b_reg <= b_next;\n            tx_reg <= tx_next;\n         end\n\n   // FSMD next-state logic & functional units\n   always @*\n   begin\n      state_next = state_reg;\n      tx_done_tick = 1'b0;\n      s_next = s_reg;\n      n_next = n_reg;\n      b_next = b_reg;\n      tx_next = tx_reg ;\n      case (state_reg)\n         idle:\n            begin\n               tx_next = 1'b1;\n               if (tx_start)\n                  begin\n                     state_next = start;\n                     s_next = 0;\n                     b_next = din;\n                  end\n            end\n         start:\n            begin\n               tx_next = 1'b0;\n               if (s_tick)\n                  if (s_reg==15)\n                     begin\n                        state_next = data;\n                        s_next = 0;\n                        n_next = 0;\n                     end\n                  else\n                     s_next = s_reg + 1;\n            end\n         data:\n            begin\n               tx_next = b_reg[0];\n               if (s_tick)\n                  if (s_reg==15)\n                     begin\n                        s_next = 0;\n                        b_next = b_reg >> 1;\n                        if (n_reg==(DBIT-1))\n                           state_next = stop ;\n                        else\n                           n_next = n_reg + 1;\n                     end\n                  else\n                     s_next = s_reg + 1;\n            end\n         stop:\n            begin\n               tx_next = 1'b1;\n               if (s_tick)\n                  if (s_reg==(SB_TICK-1))\n                     begin\n                        state_next = idle;\n                        tx_done_tick = 1'b1;\n                     end\n                  else\n                     s_next = s_reg + 1;\n            end\n      endcase\n   end\n   // output\n   assign tx = tx_reg;\n\nendmodule", "mask_idx": {"conditional_statement": [[23402, 23677], [20643, 20759], [5148, 6147], [1660, 1793]], "blocking_assignment": [[21574, 21592], [23106, 23121], [22893, 22916], [21694, 21713], [22950, 22965], [24430, 24450]], "module_program_interface_instantiation": [[1531, 1597], [1342, 1523], [1062, 1165]], "always_construct": [[20071, 20418], [1612, 8488], [22868, 24576], [19203, 19314]], "case_statement": [[8641, 18876], [1853, 8456], [23041, 24569], [20599, 21727]], "ansi_port_declaration": [[19709, 19731], [19021, 19043], [19074, 19095]], "continuous_assign": [[706, 735], [508, 530], [19433, 19480]], "parameter_declaration": [[19519, 19611], [18927, 19006], [21810, 21902]], "nonblocking_assignment": [[16062, 16081], [5335, 5350], [7356, 7376], [15043, 15062]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1062, 1165], [1176, 1337], [1342, 1523], [1531, 1597]], "continuous_assign": [[487, 506], [508, 530], [532, 557], [559, 584], [586, 608], [610, 630], [632, 654], [656, 678], [680, 702], [706, 735], [737, 765], [19342, 19389], [19412, 19429], [19433, 19480], [21751, 21771], [24593, 24612]], "blocking_assignment": [[20476, 20499], [20506, 20526], [20533, 20548], [20555, 20570], [20577, 20592], [20691, 20710], [20729, 20740], [20874, 20892], [20914, 20925], [20947, 20958], [21019, 21038], [21153, 21164], [21186, 21212], [21279, 21298], [21350, 21369], [21431, 21450], [21574, 21592], [21614, 21633], [21694, 21713], [22893, 22916], [22923, 22943], [22950, 22965], [22972, 22987], [22994, 23009], [23016, 23034], [23106, 23121], [23196, 23215], [23237, 23248], [23270, 23283], [23371, 23386], [23498, 23516], [23541, 23552], [23577, 23588], [23658, 23677], [23742, 23761], [23873, 23884], [23909, 23929], [24002, 24021], [24078, 24097], [24167, 24186], [24251, 24266], [24387, 24405], [24430, 24450], [24520, 24539]], "nonblocking_assignment": [[1731, 1744], [2040, 2051], [2084, 2092], [2125, 2142], [2175, 2189], [2222, 2236], [2368, 2383], [2512, 2526], [2559, 2574], [2736, 2748], [2781, 2796], [2982, 2997], [3030, 3041], [3199, 3219], [3305, 3324], [3420, 3439], [3513, 3522], [3703, 3714], [3850, 3868], [4028, 4037], [4078, 4091], [4551, 4566], [4615, 4630], [4679, 4694], [4910, 4926], [4975, 4990], [5039, 5054], [5270, 5286], [5335, 5350], [5399, 5414], [5631, 5649], [5698, 5707], [5923, 5941], [5990, 5999], [6138, 6147], [6324, 6341], [6374, 6389], [6521, 6536], [6666, 6680], [6713, 6728], [6891, 6903], [6936, 6951], [7138, 7153], [7186, 7197], [7356, 7376], [7462, 7478], [7574, 7593], [7667, 7689], [7951, 7963], [8123, 8132], [8173, 8186], [8387, 8396], [8685, 8703], [8736, 8755], [8788, 8807], [8840, 8858], [8891, 8910], [8943, 8961], [8994, 9013], [9046, 9065], [9098, 9116], [9149, 9168], [9202, 9221], [9255, 9273], [9307, 9326], [9360, 9379], [9413, 9432], [9466, 9485], [9519, 9538], [9572, 9591], [9625, 9643], [9677, 9695], [9729, 9747], [9781, 9799], [9833, 9851], [9885, 9903], [9937, 9956], [9990, 10009], [10043, 10062], [10096, 10115], [10149, 10168], [10202, 10220], [10254, 10273], [10307, 10326], [10360, 10378], [10412, 10431], [10465, 10484], [10518, 10536], [10570, 10588], [10622, 10641], [10675, 10693], [10727, 10746], [10780, 10799], [10833, 10852], [10886, 10904], [10938, 10957], [10991, 11009], [11043, 11061], [11095, 11113], [11147, 11165], [11199, 11217], [11251, 11269], [11303, 11322], [11356, 11375], [11409, 11427], [11461, 11480], [11514, 11533], [11567, 11586], [11620, 11639], [11673, 11692], [11726, 11744], [11778, 11796], [11830, 11848], [11882, 11900], [11934, 11952], [11986, 12005], [12039, 12058], [12092, 12110], [12144, 12163], [12197, 12216], [12250, 12269], [12303, 12321], [12355, 12373], [12407, 12425], [12459, 12477], [12511, 12529], [12563, 12582], [12616, 12634], [12668, 12687], [12721, 12740], [12774, 12792], [12826, 12844], [12878, 12896], [12930, 12948], [12982, 13000], [13034, 13052], [13086, 13104], [13138, 13156], [13190, 13208], [13242, 13260], [13294, 13312], [13346, 13364], [13398, 13416], [13450, 13468], [13502, 13520], [13554, 13572], [13606, 13624], [13658, 13676], [13710, 13728], [13762, 13780], [13814, 13832], [13866, 13884], [13919, 13937], [13972, 13990], [14025, 14043], [14078, 14096], [14131, 14149], [14184, 14202], [14237, 14255], [14290, 14309], [14344, 14363], [14398, 14416], [14451, 14470], [14505, 14524], [14559, 14577], [14612, 14631], [14666, 14685], [14720, 14739], [14774, 14793], [14828, 14846], [14881, 14900], [14935, 14954], [14989, 15008], [15043, 15062], [15097, 15116], [15151, 15170], [15205, 15223], [15258, 15277], [15312, 15331], [15366, 15385], [15420, 15438], [15473, 15492], [15527, 15546], [15581, 15599], [15634, 15653], [15688, 15706], [15741, 15759], [15794, 15812], [15847, 15866], [15901, 15920], [15955, 15974], [16009, 16027], [16062, 16081], [16116, 16134], [16169, 16187], [16222, 16241], [16276, 16294], [16329, 16348], [16383, 16402], [16437, 16455], [16490, 16509], [16544, 16563], [16598, 16617], [16652, 16671], [16706, 16725], [16760, 16779], [16814, 16832], [16867, 16885], [16920, 16939], [16974, 16993], [17028, 17046], [17081, 17099], [17134, 17152], [17187, 17205], [17240, 17258], [17293, 17311], [17346, 17365], [17400, 17418], [17453, 17472], [17507, 17526], [17561, 17580], [17615, 17633], [17668, 17687], [17722, 17740], [17775, 17793], [17828, 17847], [17882, 17901], [17936, 17954], [17989, 18008], [18043, 18062], [18097, 18116], [18151, 18169], [18204, 18223], [18258, 18277], [18312, 18330], [18365, 18384], [18419, 18438], [18473, 18492], [18527, 18546], [18581, 18600], [18635, 18654], [18689, 18707], [18742, 18761], [18796, 18814], [18849, 18867], [19266, 19277], [19298, 19314], [20152, 20170], [20183, 20194], [20207, 20218], [20231, 20242], [20294, 20318], [20331, 20347], [20360, 20376], [20389, 20405], [22491, 22509], [22522, 22533], [22546, 22557], [22570, 22581], [22594, 22609], [22661, 22685], [22698, 22714], [22727, 22743], [22756, 22772], [22785, 22803]], "case_statement": [[1853, 8456], [8641, 18876], [20599, 21727], [23041, 24569]], "conditional_statement": [[1660, 1793], [3252, 3522], [3362, 3522], [3747, 4131], [4289, 6189], [4429, 6147], [4788, 6147], [5148, 6147], [5509, 6147], [5801, 6147], [7409, 7689], [7516, 7689], [7848, 8226], [19246, 19314], [20114, 20418], [20643, 20759], [20788, 21038], [20815, 21038], [21066, 21450], [21093, 21450], [21234, 21369], [21478, 21713], [21505, 21713], [22453, 22816], [23137, 23305], [23402, 23677], [23432, 23677], [23777, 24186], [23807, 24186], [23954, 24097], [24282, 24539], [24312, 24539]], "always_construct": [[1612, 8488], [8609, 18882], [19203, 19314], [20071, 20418], [20451, 21734], [22410, 22816], [22868, 24576]], "parameter_declaration": [[18927, 19006], [19519, 19611], [21810, 21902]], "ansi_port_declaration": [[29, 72], [74, 120], [122, 165], [167, 213], [215, 293], [295, 371], [373, 397], [399, 441], [8550, 8560], [8561, 8578], [8579, 8605], [19021, 19043], [19037, 19043], [19048, 19069], [19074, 19095], [19626, 19648], [19642, 19648], [19653, 19675], [19668, 19675], [19680, 19704], [19709, 19731], [21917, 21939], [21933, 21939], [21944, 21972], [21965, 21972], [21977, 21998], [22003, 22027], [22032, 22046]]}}
{"sample_i": "vrteee-tt07-mini-aie-cgra", "topmodule": "tt_um_mini_aie_2x2", "code": "`default_nettype none\n\nmodule tt_um_mini_aie_2x2 (\n    input  wire [7:0] ui_in,    // Dedicated inputs - connected to the input switches\n    output wire [7:0] uo_out,   // Dedicated outputs - connected to the 7 segment display\n    /* verilator lint_off UNUSEDSIGNAL */\n    input  wire [7:0] uio_in,   // IOs: Bidirectional Input path\n    /* verilator lint_on UNUSEDSIGNAL */\n    output wire [7:0] uio_out,  // IOs: Bidirectional Output path\n    output wire [7:0] uio_oe,   // IOs: Bidirectional Enable path (active high: 0=input, 1=output)\n    input  wire       ena,      // will go high when the design is enabled\n    input  wire       clk,      // clock\n    input  wire       rst_n     // reset_n - low to reset\n);\n\n  wire reset = !rst_n & ena;\n  assign uio_oe = 8'b11111111;\n\n  // intermediate regs between FIFOs and switches\n  reg [7:0] switch_fifo_in[4];\n  reg [7:0] switch_fifo_out[4];\n\n  // intermediate regs between switches and PEs\n  reg [7:0] switch_pe_out[4];\n  reg [7:0] switch_pe_in[4];\n\n  // intermediate regs between PEs\n  reg [7:0] prev_pe_in[4];\n  reg [7:0] next_pe_in[4];\n\n  // control signals\n  wire switch_fifo_rd_en[4];\n  wire switch_fifo_wr_en[4];\n  \n  // generate noc and pe array\n  generate\n    genvar i;\n    for (i = 0; i < 4; i = i + 1) begin : gen\n      if (i == 0) begin\n        synchronous_fifo #(\n            .DEPTH(2),\n            .DATA_WIDTH(8)\n        ) fifo (\n            .clk(clk),\n            .rst_n(rst_n),\n            .w_en(ena),\n            .r_en(switch_fifo_rd_en[i]),\n            .data_in(ui_in),\n            .data_out(switch_fifo_in[i]),\n            .full(),\n            .empty()\n        );\n      end else begin\n        synchronous_fifo #(\n            .DEPTH(2),\n            .DATA_WIDTH(8)\n        ) fifo (\n            .clk(clk),\n            .rst_n(rst_n),\n            .w_en(switch_fifo_wr_en[i-1]),\n            .r_en(switch_fifo_rd_en[i]),\n            .data_in(switch_fifo_out[i-1]),\n            .data_out(switch_fifo_in[i]),\n            .full(),\n            .empty()\n        );\n      end\n\n      switch #(\n          .rank(i)\n      ) switch (\n          .clk(clk),\n          .rst_n(rst_n),\n          .switch_fifo_in(switch_fifo_in[i]),\n          .switch_fifo_out(switch_fifo_out[i]),\n          .pe_fifo_in(switch_pe_out[i]),\n          .pe_fifo_out(switch_pe_in[i]),\n          .rd_en(switch_fifo_rd_en[i]),\n          .wr_en(switch_fifo_wr_en[i])\n      );\n\n      integer last = i == 3 ? 0 : i + 1;\n      compute_tile pe (\n          .clk(clk),\n          .rst_n(rst_n),\n          .switch_data_in(switch_pe_in[i]),\n          .switch_data_out(switch_pe_out[i]),\n          .prev_pe_data_in(next_pe_in[last]),\n          .next_pe_data_out(next_pe_in[i]),\n          .next_pe_data_in(prev_pe_in[last]),\n          .prev_pe_data_out(prev_pe_in[i])\n      );\n    end\n\n  endgenerate\n  assign uo_out = switch_fifo_out[2];\n  assign uio_out = 8'b00000000;\n\n  always @(posedge clk or negedge rst_n) begin\n    $display(\"------------\");\n    $display(\"uo_out: %d, uio_in[7]: %d\", uo_out, uio_in[7]);\n    $display(\"switch_fifo_out[0]: %b, switch_fifo_in[0]: %b\", switch_fifo_out[0], switch_fifo_in[0]);\n    $display(\"switch_fifo_out[1]: %b, switch_fifo_in[1]: %b\", switch_fifo_out[1], switch_fifo_in[1]);\n    $display(\"switch_fifo_out[2]: %b, switch_fifo_in[2]: %b\", switch_fifo_out[2], switch_fifo_in[2]);\n    $display(\"switch_fifo_out[3]: %b, switch_fifo_in[3]: %b\", switch_fifo_out[3], switch_fifo_in[3]);\n  end\n  \n\nendmodule\n\n\n\n\nmodule synchronous_fifo #(parameter DEPTH=2, DATA_WIDTH=8) (\n  input wire clk, \n  input wire rst_n,\n  input wire w_en, \n  input wire r_en,\n  input [DATA_WIDTH-1:0] data_in,\n  output reg [DATA_WIDTH-1:0] data_out,\n  output wire full, empty\n);\n  \n  reg [$clog2(DEPTH)-1:0] w_ptr, r_ptr;\n  reg [DATA_WIDTH-1:0] fifo[DEPTH];\n  \n  // Set Default values on reset.\n  always@(posedge clk or negedge rst_n) begin\n    if (!rst_n) begin\n      w_ptr <= 0; r_ptr <= 0;\n      data_out <= 0;\n      \n    end else begin\n      if (w_en & !full) begin\n        fifo[w_ptr] <= data_in;\n        w_ptr <= w_ptr + 1;\n      end\n      \n      if (r_en & !empty) begin\n        data_out <= fifo[r_ptr];\n        r_ptr <= r_ptr + 1;\n      end\n    end\n  end\n\n  assign full = ((w_ptr+1'b1) == r_ptr);\n  assign empty = (w_ptr == r_ptr);\n\n\nendmodule\n\n// data_in[7:6] -> state\n//   state = 00: CONFIG(WEIGHT)\n//   state = 01: CONFIG(NEXT_PE, OP)\n//   state = 10: START(OPERAND)\n//   state = 11: END(OUTPUT)\n\nmodule compute_tile\n(\n    input wire clk, \n    input wire rst_n,\n    input [7:0] switch_data_in,\n    output reg [7:0] switch_data_out,\n    output reg [7:0] next_pe_data_out,\n    input [7:0] next_pe_data_in,\n    input [7:0] prev_pe_data_in,\n    output reg [7:0] prev_pe_data_out\n);\n\n    reg op_type;\n    reg [3:0] weight;\n\n    reg has_next_core;\n    reg next_core_offset;\n\n    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n            op_type <= 1'b0;\n            weight <= 4'b0000;\n            next_pe_data_out <= 8'b00000000;\n            prev_pe_data_out <= 8'b00000000;\n\n            has_next_core <= 1'b0;\n            next_core_offset <= 1'b0;\n            switch_data_out <= 8'b00000000;\n        \n        end else if (switch_data_in[7:6] == 2'b00) begin\n            // $display(\"compute_tile config weight: %d\", switch_data_in);\n            weight <= switch_data_in[3:0];\n        \n        end else if (switch_data_in[7:6] == 2'b01) begin\n            has_next_core <= 1'b1;\n            next_core_offset <= switch_data_in[4];\n            op_type <= switch_data_in[0];\n        \n        end else begin\n            if (has_next_core) begin\n                next_pe_data_out <= switch_data_in;\n                // case (next_core_offset)\n                //     1'b0: next_pe_data_out <= switch_data_in;\n                //     1'b1: prev_pe_data_out <= switch_data_in;\n                // endcase\n            end else begin\n                switch_data_out <= weight + prev_pe_data_in + next_pe_data_in;\n                // case (op_type) \n                //     1'b0: switch_data_out <= weight + prev_pe_data_in + next_pe_data_in;\n                //     1'b1: switch_data_out <= weight & prev_pe_data_in & next_pe_data_in;\n                // endcase    \n            end\n        end\n    end\nendmodule\n\n\n\n\n\nmodule switch \n#(parameter rank = 0)\n(\n    input wire clk, rst_n,\n    input [7:0] switch_fifo_in, \n    output reg [7:0] switch_fifo_out,\n    input [7:0] pe_fifo_in,\n    output reg [7:0] pe_fifo_out,\n    output wire rd_en,\n    output wire wr_en\n);\n\nreg [7:0] prev_switch_fifo_in;\nreg [7:0] prev_pe_fifo_in;\n\nwire pe_rd, fifo_rd;\nassign pe_rd = pe_fifo_in != prev_pe_fifo_in;\nassign fifo_rd = switch_fifo_in != prev_switch_fifo_in;\n\nalways @(posedge clk or negedge rst_n) begin\n    if (!rst_n) begin\n        switch_fifo_out <= 8'b00000000;\n        pe_fifo_out <= 8'b00000000;\n        prev_pe_fifo_in <= 8'b00000000;\n        prev_switch_fifo_in <= 8'b00000001;\n\n    end else begin\n        if (pe_rd) begin\n            prev_pe_fifo_in <= pe_fifo_in;\n            switch_fifo_out <= {4'b1111, pe_fifo_in[3:0]};\n            \n        end else if (fifo_rd) begin\n            prev_switch_fifo_in <= switch_fifo_in;\n            if (switch_fifo_in[5:4] == rank) begin\n                pe_fifo_out <= switch_fifo_in;\n            end else begin\n                switch_fifo_out <= switch_fifo_in;\n            end\n        end \n    end\nend\n\nassign rd_en = 1'b1;\nassign wr_en = 1'b1;\n\nendmodule\n", "mask_idx": {"conditional_statement": [[5163, 6219], [5347, 6219], [6929, 7352], [4851, 6219]], "module_program_interface_instantiation": [[2039, 2394], [1307, 1632], [1662, 2021]], "always_construct": [[4798, 6227], [6674, 7364], [3810, 4175]], "ansi_port_declaration": [[6469, 6486], [4448, 4464], [3591, 3622]], "continuous_assign": [[749, 777], [7387, 7407], [4220, 4252]], "parameter_declaration": [[3476, 3510], [6260, 6279]], "nonblocking_assignment": [[7289, 7323], [5290, 5320], [3912, 3926], [4986, 5018]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1307, 1632], [1662, 2021], [2039, 2394], [2443, 2784]], "continuous_assign": [[749, 777], [2810, 2845], [2848, 2877], [4179, 4217], [4220, 4252], [6571, 6616], [6617, 6672], [7366, 7386], [7387, 7407]], "blocking_assignment": [], "nonblocking_assignment": [[3882, 3905], [3894, 3905], [3912, 3926], [3991, 4014], [4023, 4042], [4099, 4123], [4132, 4151], [4881, 4897], [4910, 4928], [4941, 4973], [4986, 5018], [5032, 5054], [5067, 5092], [5105, 5136], [5290, 5320], [5399, 5421], [5434, 5472], [5485, 5514], [5600, 5635], [5879, 5941], [6749, 6780], [6789, 6816], [6825, 6856], [6865, 6900], [6958, 6988], [7001, 7047], [7109, 7147], [7215, 7245], [7289, 7323]], "case_statement": [], "conditional_statement": [[3858, 4169], [3959, 4052], [4066, 4161], [4851, 6219], [5163, 6219], [5347, 6219], [5559, 6207], [6723, 7360], [6929, 7352], [7078, 7352], [7160, 7339]], "always_construct": [[2881, 3431], [3810, 4175], [4798, 6227], [6674, 7364]], "parameter_declaration": [[3476, 3510], [6260, 6279]], "ansi_port_declaration": [[55, 136], [141, 226], [273, 333], [379, 440], [445, 539], [544, 614], [619, 655], [660, 713], [3513, 3529], [3532, 3549], [3552, 3569], [3572, 3588], [3591, 3622], [3625, 3662], [3665, 3688], [3683, 3688], [4448, 4464], [4469, 4486], [4491, 4518], [4523, 4556], [4561, 4595], [4600, 4628], [4633, 4661], [4666, 4699], [6286, 6308], [6302, 6308], [6313, 6341], [6346, 6379], [6384, 6407], [6412, 6441], [6446, 6464], [6469, 6486]]}}
{"sample_i": "vzayakov-tt07-pong-vga", "topmodule": "tt_um_vzayakov_top", "code": "`default_nettype none\nmodule tt_um_vzayakov_top (\n\tui_in,\n\tuo_out,\n\tuio_in,\n\tuio_out,\n\tuio_oe,\n\tena,\n\tclk,\n\trst_n\n);\n\tinput wire [7:0] ui_in;\n\toutput wire [7:0] uo_out;\n\tinput wire [7:0] uio_in;\n\toutput wire [7:0] uio_out;\n    output wire [7:0] uio_oe;\n\tinput wire ena;\n\tinput wire clk;\n\tinput wire rst_n;\n\twire R_move_switch;\n\twire R_up_switch;\n\twire L_move_switch;\n\twire L_up_switch;\n\twire serve_L_button;\n\twire VGA_BLANK_N;\n\twire VGA_CLK;\n\twire VGA_SYNC_N;\n\twire VGA_VS;\n\twire VGA_HS;\n\twire VGA_R;\n\twire VGA_G;\n\twire VGA_B;\n\twire [6:0] HEX0;\n\twire [6:0] HEX1;\n\twire [6:0] HEX2;\n\twire [6:0] HEX3;\n\twire [6:0] HEX4;\n\twire [6:0] HEX5;\n\twire [6:0] HEX6;\n\twire [6:0] HEX7;\n\twire blank;\n\twire [8:0] row;\n\twire [9:0] col;\n\twire [3:0] L1;\n\twire [3:0] L2;\n\twire [3:0] L3;\n\twire [3:0] L4;\n\twire [3:0] R1;\n\twire [3:0] R2;\n\twire [3:0] R3;\n\twire [3:0] R4;\n\tassign R_move_switch = ui_in[0];\n\tassign R_up_switch = ui_in[1];\n\tassign L_move_switch = ui_in[2];\n\tassign L_up_switch = ui_in[3];\n\tassign serve_L_button = ui_in[4];\n\tassign uo_out[0] = VGA_CLK;\n\tassign uo_out[1] = VGA_BLANK_N;\n\tassign uo_out[2] = VGA_SYNC_N;\n\tassign uo_out[3] = VGA_VS;\n\tassign uo_out[4] = VGA_HS;\n\tassign uo_out[5] = VGA_R;\n\tassign uo_out[6] = VGA_G;\n\tassign uo_out[7] = VGA_B;\n\tassign VGA_SYNC_N = 1'b0;\n\tassign VGA_BLANK_N = ~blank;\n\tassign VGA_CLK = ~clk;\n\tassign uio_out = 8'b0;\n\tassign uio_oe = 8'b0;\n\tpong DUT(\n\t\t.serve_L_async(serve_L_button),\n\t\t.reset_L(rst_n),\n\t\t.CLOCK_50(clk),\n\t\t.R_move_async(R_move_switch),\n\t\t.R_up_async(R_up_switch),\n\t\t.L_move_async(L_move_switch),\n\t\t.L_up_async(L_up_switch),\n\t\t.VGA_R(VGA_R),\n\t\t.VGA_G(VGA_G),\n\t\t.VGA_B(VGA_B),\n\t\t.HS(VGA_HS),\n\t\t.VS(VGA_VS),\n\t\t.blank(blank),\n\t\t.HEX0(HEX0),\n\t\t.HEX1(HEX1),\n\t\t.HEX2(HEX2),\n\t\t.HEX3(HEX3),\n\t\t.HEX4(HEX4),\n\t\t.HEX5(HEX5),\n\t\t.HEX6(HEX6),\n\t\t.HEX7(HEX7),\n\t\t.L1(L1),\n\t\t.L2(L2),\n\t\t.L3(L3),\n\t\t.L4(L4),\n\t\t.R1(R1),\n\t\t.R2(R2),\n\t\t.R3(R3),\n\t\t.R4(R4)\n\t);\n\tSevenSegment SSL1(\n\t\t.BCDnumber(L1),\n\t\t.hexOutput_L(HEX4)\n\t);\n\tSevenSegment SSL2(\n\t\t.BCDnumber(L2),\n\t\t.hexOutput_L(HEX5)\n\t);\n\tSevenSegment SSL3(\n\t\t.BCDnumber(L3),\n\t\t.hexOutput_L(HEX6)\n\t);\n\tSevenSegment SSL4(\n\t\t.BCDnumber(L4),\n\t\t.hexOutput_L(HEX7)\n\t);\n\tSevenSegment SSR1(\n\t\t.BCDnumber(R1),\n\t\t.hexOutput_L(HEX0)\n\t);\n\tSevenSegment SSR2(\n\t\t.BCDnumber(R2),\n\t\t.hexOutput_L(HEX1)\n\t);\n\tSevenSegment SSR3(\n\t\t.BCDnumber(R3),\n\t\t.hexOutput_L(HEX2)\n\t);\n\tSevenSegment SSR4(\n\t\t.BCDnumber(R4),\n\t\t.hexOutput_L(HEX3)\n\t);\nendmodule\nmodule SevenSegment (\n\tBCDnumber,\n\thexOutput_L\n);\n\tinput wire [3:0] BCDnumber;\n\toutput reg [6:0] hexOutput_L;\n\talways @(*)\n\t\tcase (BCDnumber)\n\t\t\t4'd0: hexOutput_L = 7'b1000000;\n\t\t\t4'd1: hexOutput_L = 7'b1111001;\n\t\t\t4'd2: hexOutput_L = 7'b0100100;\n\t\t\t4'd3: hexOutput_L = 7'b0110000;\n\t\t\t4'd4: hexOutput_L = 7'b0011001;\n\t\t\t4'd5: hexOutput_L = 7'b0010010;\n\t\t\t4'd6: hexOutput_L = 7'b0000011;\n\t\t\t4'd7: hexOutput_L = 7'b1111000;\n\t\t\t4'd8: hexOutput_L = 7'b0000000;\n\t\t\t4'd9: hexOutput_L = 7'b0011000;\n\t\t\tdefault: hexOutput_L = 7'b1111111;\n\t\tendcase\nendmodule\nmodule pong (\n\tserve_L_async,\n\treset_L,\n\tCLOCK_50,\n\tR_move_async,\n\tR_up_async,\n\tL_move_async,\n\tL_up_async,\n\tHEX0,\n\tHEX1,\n\tHEX2,\n\tHEX3,\n\tHEX4,\n\tHEX5,\n\tHEX6,\n\tHEX7,\n\tVGA_R,\n\tVGA_G,\n\tVGA_B,\n\tHS,\n\tVS,\n\tblank,\n\tL1,\n\tL2,\n\tL3,\n\tL4,\n\tR1,\n\tR2,\n\tR3,\n\tR4\n);\n\tinput wire serve_L_async;\n\tinput wire reset_L;\n\tinput wire CLOCK_50;\n\tinput wire R_move_async;\n\tinput wire R_up_async;\n\tinput wire L_move_async;\n\tinput wire L_up_async;\n\tinput wire [6:0] HEX0;\n\tinput wire [6:0] HEX1;\n\tinput wire [6:0] HEX2;\n\tinput wire [6:0] HEX3;\n\tinput wire [6:0] HEX4;\n\tinput wire [6:0] HEX5;\n\tinput wire [6:0] HEX6;\n\tinput wire [6:0] HEX7;\n\toutput wire VGA_R;\n\toutput wire VGA_G;\n\toutput wire VGA_B;\n\toutput wire HS;\n\toutput wire VS;\n\toutput wire blank;\n\toutput wire [3:0] L1;\n\toutput wire [3:0] L2;\n\toutput wire [3:0] L3;\n\toutput wire [3:0] L4;\n\toutput wire [3:0] R1;\n\toutput wire [3:0] R2;\n\toutput wire [3:0] R3;\n\toutput wire [3:0] R4;\n\twire [8:0] row;\n\twire [8:0] sum_left;\n\twire [8:0] sum_right;\n\twire [8:0] Q_BR;\n\twire [8:0] LPad_row;\n\twire [8:0] RPad_row;\n\twire [9:0] col;\n\twire [9:0] Q_BC;\n\twire is_btwn_LPad;\n\twire is_btwn_RPad;\n\twire reset_paddle;\n\twire reset_ballcol;\n\twire reset_ballrow;\n\twire preset_left;\n\twire reset_left;\n\twire preset_up;\n\twire reset_up;\n\twire clr_score;\n\twire en_BR;\n\twire en_BC;\n\twire en_LPadR;\n\twire en_RPadR;\n\twire en_Lscore;\n\twire en_Rscore;\n\twire showScoreRight;\n\twire showScoreLeft;\n\twire LWin;\n\twire RWin;\n\treg D_left;\n\twire VS_display_done;\n\twire rightHit;\n\twire leftHit;\n\twire up;\n\twire left;\n\treg in_done;\n\twire out_done;\n\twire R_move;\n\twire R_up;\n\twire L_move;\n\twire L_up;\n\twire serve_L;\n\twire isB_L1;\n\twire isB_R1;\n\twire isB_L2;\n\twire isB_R2;\n\twire isB_L3;\n\twire isB_R3;\n\twire isB_L4;\n\twire isB_R4;\n\tvga vg(\n\t\t.reset(~reset_L),\n\t\t.CLOCK_50(CLOCK_50),\n\t\t.HS(HS),\n\t\t.VS(VS),\n\t\t.blank(blank),\n\t\t.row(row),\n\t\t.col(col)\n\t);\n\tSynchronizer sync1(\n\t\t.async(serve_L_async),\n\t\t.clock(CLOCK_50),\n\t\t.sync(serve_L)\n\t);\n\tSynchronizer sync2(\n\t\t.async(R_move_async),\n\t\t.clock(CLOCK_50),\n\t\t.sync(R_move)\n\t);\n\tSynchronizer sync3(\n\t\t.async(R_up_async),\n\t\t.clock(CLOCK_50),\n\t\t.sync(R_up)\n\t);\n\tSynchronizer sync4(\n\t\t.async(L_move_async),\n\t\t.clock(CLOCK_50),\n\t\t.sync(L_move)\n\t);\n\tSynchronizer sync5(\n\t\t.async(L_up_async),\n\t\t.clock(CLOCK_50),\n\t\t.sync(L_up)\n\t);\n\tpong_fsm pfsm(\n\t\t.serve_L(serve_L),\n\t\t.reset_L(reset_L),\n\t\t.LWin(LWin),\n\t\t.RWin(RWin),\n\t\t.CLOCK_50(CLOCK_50),\n\t\t.VS_display_done(VS_display_done),\n\t\t.reset_paddle(reset_paddle),\n\t\t.reset_ballcol(reset_ballcol),\n\t\t.reset_ballrow(reset_ballrow),\n\t\t.preset_left(preset_left),\n\t\t.preset_up(preset_up),\n\t\t.reset_left(reset_left),\n\t\t.reset_up(reset_up),\n\t\t.clr_score(clr_score),\n\t\t.en_BR(en_BR),\n\t\t.en_BC(en_BC),\n\t\t.en_LPadR(en_LPadR),\n\t\t.en_RPadR(en_RPadR),\n\t\t.en_Lscore(en_Lscore),\n\t\t.en_Rscore(en_Rscore),\n\t\t.showScoreRight(showScoreRight),\n\t\t.showScoreLeft(showScoreLeft)\n\t);\n\tBall b(\n\t\t.clock(CLOCK_50),\n\t\t.reset_ballrow(reset_ballrow),\n\t\t.reset_ballcol(reset_ballcol),\n\t\t.reset_left(reset_left),\n\t\t.preset_left(preset_left),\n\t\t.reset_up(reset_up),\n\t\t.en_BR(en_BR),\n\t\t.en_BC(en_BC),\n\t\t.D_left(D_left),\n\t\t.leftHit(leftHit),\n\t\t.rightHit(rightHit),\n\t\t.RWin(RWin),\n\t\t.LWin(LWin),\n\t\t.Q_BC(Q_BC),\n\t\t.Q_BR(Q_BR),\n\t\t.up(up),\n\t\t.left(left)\n\t);\n\tPaddle leftPaddle(\n\t\t.en_P(en_LPadR),\n\t\t.move(L_move),\n\t\t.clock(CLOCK_50),\n\t\t.reset_paddle(reset_paddle),\n\t\t.up(L_up),\n\t\t.Q_P(LPad_row)\n\t);\n\tPaddle rightPaddle(\n\t\t.en_P(en_RPadR),\n\t\t.move(R_move),\n\t\t.clock(CLOCK_50),\n\t\t.reset_paddle(reset_paddle),\n\t\t.up(R_up),\n\t\t.Q_P(RPad_row)\n\t);\n\tColor c(\n\t\t.VGA_row(row),\n\t\t.VGA_col(col),\n\t\t.Q_BR(Q_BR),\n\t\t.Q_BC(Q_BC),\n\t\t.Q_LP(LPad_row),\n\t\t.Q_RP(RPad_row),\n\t\t.VGA_R(VGA_R),\n\t\t.VGA_G(VGA_G),\n\t\t.VGA_B(VGA_B),\n\t\t.showScoreRight(showScoreRight),\n\t\t.showScoreLeft(showScoreLeft),\n\t\t.isB_L1(isB_L1),\n\t\t.isB_R1(isB_R1),\n\t\t.isB_L2(isB_L2),\n\t\t.isB_R2(isB_R2),\n\t\t.isB_L3(isB_L3),\n\t\t.isB_R3(isB_R3),\n\t\t.isB_L4(isB_L4),\n\t\t.isB_R4(isB_R4)\n\t);\n\tScoring s(\n\t\t.en_Rscore(en_Rscore),\n\t\t.en_Lscore(en_Lscore),\n\t\t.clr_score(clr_score),\n\t\t.CLOCK_50(CLOCK_50),\n\t\t.L1(L1),\n\t\t.L2(L2),\n\t\t.L3(L3),\n\t\t.L4(L4),\n\t\t.R1(R1),\n\t\t.R2(R2),\n\t\t.R3(R3),\n\t\t.R4(R4)\n\t);\n\tScoreOnDisplay scoreL1(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd200),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX4),\n\t\t.is_between(isB_L1)\n\t);\n\tScoreOnDisplay scoreR1(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd540),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX0),\n\t\t.is_between(isB_R1)\n\t);\n\tScoreOnDisplay scoreL2(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd160),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX5),\n\t\t.is_between(isB_L2)\n\t);\n\tScoreOnDisplay scoreR2(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd500),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX1),\n\t\t.is_between(isB_R2)\n\t);\n\tScoreOnDisplay scoreL3(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd120),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX6),\n\t\t.is_between(isB_L3)\n\t);\n\tScoreOnDisplay scoreR3(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd460),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX2),\n\t\t.is_between(isB_R3)\n\t);\n\tScoreOnDisplay scoreL4(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd80),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX7),\n\t\t.is_between(isB_L4)\n\t);\n\tScoreOnDisplay scoreR4(\n\t\t.rowChoice(9'd64),\n\t\t.colChoice(10'd420),\n\t\t.curr_row(row),\n\t\t.curr_col(col),\n\t\t.hexOutput_L(HEX3),\n\t\t.is_between(isB_R4)\n\t);\n\tDFlipFlop doneff(\n\t\t.D(in_done),\n\t\t.Q(out_done),\n\t\t.clock(CLOCK_50),\n\t\t.preset_L(),\n\t\t.reset_L()\n\t);\n\talways @(*)\n\t\tif (VS_display_done)\n\t\t\tin_done = 1'b1;\n\t\telse\n\t\t\tin_done = 1'b0;\n\tassign VS_display_done = (((row == 9'd479) && (col == 10'd639)) && ~out_done ? 1'b1 : 1'b0);\n\tAdder #(.WIDTH(9)) addL(\n\t\t.A(Q_BR),\n\t\t.B(9'd3),\n\t\t.Cin(1'b0),\n\t\t.Sum(sum_left),\n\t\t.Cout()\n\t);\n\tAdder #(.WIDTH(9)) addR(\n\t\t.A(Q_BR),\n\t\t.B(9'd3),\n\t\t.Cin(1'b0),\n\t\t.Sum(sum_right),\n\t\t.Cout()\n\t);\n\tOffsetCheck #(.WIDTH(9)) oc_left(\n\t\t.low(LPad_row),\n\t\t.delta(9'd51),\n\t\t.val(sum_left),\n\t\t.is_between(is_btwn_LPad)\n\t);\n\tOffsetCheck #(.WIDTH(9)) oc_right(\n\t\t.low(RPad_row),\n\t\t.delta(9'd51),\n\t\t.val(sum_right),\n\t\t.is_between(is_btwn_RPad)\n\t);\n\talways @(*)\n\t\tif ((is_btwn_RPad && rightHit) && VS_display_done)\n\t\t\tD_left = 1'b1;\n\t\telse if ((is_btwn_LPad && leftHit) && VS_display_done)\n\t\t\tD_left = 1'b0;\n\t\telse\n\t\t\tD_left = left;\nendmodule\nmodule pong_fsm (\n\tserve_L,\n\treset_L,\n\tLWin,\n\tRWin,\n\tCLOCK_50,\n\tVS_display_done,\n\treset_paddle,\n\treset_ballcol,\n\treset_ballrow,\n\tpreset_left,\n\tpreset_up,\n\treset_left,\n\treset_up,\n\tclr_score,\n\ten_BR,\n\ten_BC,\n\ten_LPadR,\n\ten_RPadR,\n\ten_Lscore,\n\ten_Rscore,\n\tshowScoreRight,\n\tshowScoreLeft\n);\n\tinput wire serve_L;\n\tinput wire reset_L;\n\tinput wire LWin;\n\tinput wire RWin;\n\tinput wire CLOCK_50;\n\tinput wire VS_display_done;\n\toutput reg reset_paddle;\n\toutput reg reset_ballcol;\n\toutput reg reset_ballrow;\n\toutput reg preset_left;\n\toutput reg preset_up;\n\toutput reg reset_left;\n\toutput reg reset_up;\n\toutput reg clr_score;\n\toutput reg en_BR;\n\toutput reg en_BC;\n\toutput reg en_LPadR;\n\toutput reg en_RPadR;\n\toutput reg en_Lscore;\n\toutput reg en_Rscore;\n\toutput reg showScoreRight;\n\toutput reg showScoreLeft;\n\twire [3:0] currState;\n\treg [3:0] nextState;\n\tDFlipFlop dff0(\n\t\t.D(nextState[0]),\n\t\t.Q(currState[0]),\n\t\t.clock(CLOCK_50),\n\t\t.reset_L(reset_L),\n\t\t.preset_L(1'b1)\n\t);\n\tDFlipFlop dff1(\n\t\t.D(nextState[1]),\n\t\t.Q(currState[1]),\n\t\t.clock(CLOCK_50),\n\t\t.reset_L(reset_L),\n\t\t.preset_L(1'b1)\n\t);\n\tDFlipFlop dff2(\n\t\t.D(nextState[2]),\n\t\t.Q(currState[2]),\n\t\t.clock(CLOCK_50),\n\t\t.reset_L(reset_L),\n\t\t.preset_L(1'b1)\n\t);\n\tDFlipFlop dff3(\n\t\t.D(nextState[3]),\n\t\t.Q(currState[3]),\n\t\t.clock(CLOCK_50),\n\t\t.reset_L(reset_L),\n\t\t.preset_L(1'b1)\n\t);\n\talways @(*) begin\n\t\treset_paddle = 1'b0;\n\t\treset_ballcol = 1'b0;\n\t\treset_ballrow = 1'b0;\n\t\tpreset_left = 1'b0;\n\t\tpreset_up = 1'b0;\n\t\treset_left = 1'b0;\n\t\treset_up = 1'b0;\n\t\tclr_score = 1'b0;\n\t\ten_BR = 1'b0;\n\t\ten_BC = 1'b0;\n\t\ten_LPadR = 1'b0;\n\t\ten_RPadR = 1'b0;\n\t\ten_Lscore = 1'b0;\n\t\ten_Rscore = 1'b0;\n\t\tshowScoreLeft = 1'b0;\n\t\tshowScoreRight = 1'b0;\n\t\tcase (currState)\n\t\t\t4'b0000: begin\n\t\t\t\tnextState = 4'b0001;\n\t\t\t\treset_up = 1'b1;\n\t\t\t\treset_left = 1'b1;\n\t\t\t\treset_paddle = 1'b1;\n\t\t\t\treset_ballcol = 1'b1;\n\t\t\t\treset_ballrow = 1'b1;\n\t\t\t\tclr_score = 1'b1;\n\t\t\t\ten_BR = 1'b1;\n\t\t\t\ten_BC = 1'b1;\n\t\t\t\ten_LPadR = 1'b1;\n\t\t\t\ten_RPadR = 1'b1;\n\t\t\tend\n\t\t\t4'b0001:\n\t\t\t\tif (~serve_L && VS_display_done)\n\t\t\t\t\tnextState = 4'b0011;\n\t\t\t\telse\n\t\t\t\t\tnextState = 4'b0001;\n\t\t\t4'b0010: begin\n\t\t\t\tnextState = 4'b0100;\n\t\t\t\tpreset_left = 1'b1;\n\t\t\t\treset_up = 1'b1;\n\t\t\t\ten_BR = 1'b1;\n\t\t\t\ten_BC = 1'b1;\n\t\t\t\ten_LPadR = 1'b1;\n\t\t\t\ten_RPadR = 1'b1;\n\t\t\tend\n\t\t\t4'b0011: begin\n\t\t\t\tnextState = 4'b0100;\n\t\t\t\treset_left = 1'b1;\n\t\t\t\treset_up = 1'b1;\n\t\t\t\ten_BR = 1'b1;\n\t\t\t\ten_BC = 1'b1;\n\t\t\t\ten_LPadR = 1'b1;\n\t\t\t\ten_RPadR = 1'b1;\n\t\t\tend\n\t\t\t4'b0100:\n\t\t\t\tif (LWin && VS_display_done)\n\t\t\t\t\tnextState = 4'b0101;\n\t\t\t\telse if (RWin && VS_display_done)\n\t\t\t\t\tnextState = 4'b0110;\n\t\t\t\telse if (VS_display_done)\n\t\t\t\t\tnextState = 4'b1001;\n\t\t\t\telse\n\t\t\t\t\tnextState = 4'b0100;\n\t\t\t4'b1001: begin\n\t\t\t\tnextState = 4'b0100;\n\t\t\t\ten_BR = 1'b1;\n\t\t\t\ten_BC = 1'b1;\n\t\t\t\ten_LPadR = 1'b1;\n\t\t\t\ten_RPadR = 1'b1;\n\t\t\tend\n\t\t\t4'b0101: begin\n\t\t\t\tnextState = 4'b0111;\n\t\t\t\treset_up = 1'b1;\n\t\t\t\treset_paddle = 1'b1;\n\t\t\t\treset_ballcol = 1'b1;\n\t\t\t\treset_ballrow = 1'b1;\n\t\t\t\ten_BR = 1'b1;\n\t\t\t\ten_BC = 1'b1;\n\t\t\t\ten_Lscore = 1'b1;\n\t\t\t\ten_LPadR = 1'b1;\n\t\t\t\ten_RPadR = 1'b1;\n\t\t\tend\n\t\t\t4'b0110: begin\n\t\t\t\tnextState = 4'b1000;\n\t\t\t\treset_up = 1'b1;\n\t\t\t\treset_paddle = 1'b1;\n\t\t\t\treset_ballcol = 1'b1;\n\t\t\t\treset_ballrow = 1'b1;\n\t\t\t\ten_BR = 1'b1;\n\t\t\t\ten_BC = 1'b1;\n\t\t\t\ten_Rscore = 1'b1;\n\t\t\t\ten_LPadR = 1'b1;\n\t\t\t\ten_RPadR = 1'b1;\n\t\t\tend\n\t\t\t4'b0111: begin\n\t\t\t\tif (~serve_L && VS_display_done)\n\t\t\t\t\tnextState = 4'b0011;\n\t\t\t\telse\n\t\t\t\t\tnextState = 4'b0111;\n\t\t\t\tshowScoreLeft = 1'b1;\n\t\t\tend\n\t\t\t4'b1000: begin\n\t\t\t\tif (~serve_L && VS_display_done)\n\t\t\t\t\tnextState = 4'b0010;\n\t\t\t\telse\n\t\t\t\t\tnextState = 4'b1000;\n\t\t\t\tshowScoreRight = 1'b1;\n\t\t\tend\n\t\t\tdefault:\n\t\t\t\tnextState = 4'b0000;\n\t\tendcase\n\tend\nendmodule\nmodule Ball (\n\tclock,\n\treset_ballrow,\n\treset_ballcol,\n\treset_left,\n\tpreset_left,\n\treset_up,\n\ten_BR,\n\ten_BC,\n\tD_left,\n\tleftHit,\n\trightHit,\n\tRWin,\n\tLWin,\n\tQ_BC,\n\tQ_BR,\n\tup,\n\tleft\n);\n\tinput wire clock;\n\tinput wire reset_ballrow;\n\tinput wire reset_ballcol;\n\tinput wire reset_left;\n\tinput wire preset_left;\n\tinput wire reset_up;\n\tinput wire en_BR;\n\tinput wire en_BC;\n\tinput wire D_left;\n\toutput wire leftHit;\n\toutput wire rightHit;\n\toutput wire RWin;\n\toutput wire LWin;\n\toutput wire [9:0] Q_BC;\n\toutput wire [8:0] Q_BR;\n\toutput wire up;\n\toutput wire left;\n\twire cout1;\n\twire cout2;\n\twire ballTop;\n\twire ballBottom;\n\twire [9:0] addLeftIn;\n\twire [9:0] D_BC;\n\twire [8:0] D_BR;\n\twire [8:0] addUpIn;\n\twire Q_up;\n\twire Q_left;\n\treg D_up;\n\twire [8:0] resetBallRow;\n\twire [9:0] resetBallCol;\n\tRegister #(.WIDTH(9)) BallRow(\n\t\t.en(en_BR),\n\t\t.clear(1'b0),\n\t\t.D(D_BR),\n\t\t.Q(Q_BR),\n\t\t.clock(clock)\n\t);\n\tRegister #(.WIDTH(10)) BallCol(\n\t\t.en(en_BC),\n\t\t.clear(1'b0),\n\t\t.D(D_BC),\n\t\t.Q(Q_BC),\n\t\t.clock(clock)\n\t);\n\tMux2to1 #(.WIDTH(9)) MuxUp(\n\t\t.I0(9'd1),\n\t\t.I1(9'b111111111),\n\t\t.S(Q_up),\n\t\t.Y(addUpIn)\n\t);\n\tMux2to1 #(.WIDTH(10)) MuxLeft(\n\t\t.I0(10'd2),\n\t\t.I1(10'b1111111110),\n\t\t.S(Q_left),\n\t\t.Y(addLeftIn)\n\t);\n\tAdder #(.WIDTH(9)) RowAdd(\n\t\t.Cin(1'b0),\n\t\t.Cout(cout1),\n\t\t.A(addUpIn),\n\t\t.B(Q_BR),\n\t\t.Sum(resetBallRow)\n\t);\n\tAdder #(.WIDTH(10)) ColAdd(\n\t\t.Cin(1'b0),\n\t\t.Cout(cout2),\n\t\t.A(addLeftIn),\n\t\t.B(Q_BC),\n\t\t.Sum(resetBallCol)\n\t);\n\tMux2to1 #(.WIDTH(9)) ResetRow(\n\t\t.I0(resetBallRow),\n\t\t.I1(9'd238),\n\t\t.S(reset_ballrow),\n\t\t.Y(D_BR)\n\t);\n\tMux2to1 #(.WIDTH(10)) ResetCol(\n\t\t.I0(resetBallCol),\n\t\t.I1(10'd318),\n\t\t.S(reset_ballcol),\n\t\t.Y(D_BC)\n\t);\n\tMagComp #(.WIDTH(9)) mc1(\n\t\t.A(Q_BR),\n\t\t.B(9'd0),\n\t\t.AltB(),\n\t\t.AgtB(),\n\t\t.AeqB(ballTop)\n\t);\n\tMagComp #(.WIDTH(9)) mc2(\n\t\t.A(Q_BR),\n\t\t.B(9'd476),\n\t\t.AltB(),\n\t\t.AgtB(),\n\t\t.AeqB(ballBottom)\n\t);\n\tMagComp #(.WIDTH(10)) mc3(\n\t\t.A(Q_BC),\n\t\t.B(10'd64),\n\t\t.AltB(),\n\t\t.AgtB(),\n\t\t.AeqB(leftHit)\n\t);\n\tMagComp #(.WIDTH(10)) mc4(\n\t\t.A(Q_BC),\n\t\t.B(10'd572),\n\t\t.AltB(),\n\t\t.AgtB(),\n\t\t.AeqB(rightHit)\n\t);\n\tMagComp #(.WIDTH(10)) mc5(\n\t\t.A(Q_BC),\n\t\t.B(10'd0),\n\t\t.AltB(),\n\t\t.AgtB(),\n\t\t.AeqB(RWin)\n\t);\n\tMagComp #(.WIDTH(10)) mc6(\n\t\t.A(Q_BC),\n\t\t.B(10'd636),\n\t\t.AltB(),\n\t\t.AgtB(),\n\t\t.AeqB(LWin)\n\t);\n\tDFlipFlop leftff(\n\t\t.D(D_left),\n\t\t.preset_L(~preset_left),\n\t\t.reset_L(~reset_left),\n\t\t.clock(clock),\n\t\t.Q(Q_left)\n\t);\n\tDFlipFlop upff(\n\t\t.D(D_up),\n\t\t.preset_L(1'b1),\n\t\t.reset_L(~reset_up),\n\t\t.clock(clock),\n\t\t.Q(Q_up)\n\t);\n\tassign up = Q_up;\n\tassign left = Q_left;\n\talways @(*)\n\t\tif (ballTop)\n\t\t\tD_up = 1'b0;\n\t\telse if (ballBottom)\n\t\t\tD_up = 1'b1;\n\t\telse\n\t\t\tD_up = Q_up;\nendmodule\nmodule Paddle (\n\ten_P,\n\tmove,\n\tclock,\n\treset_paddle,\n\tup,\n\tQ_P\n);\n\tinput wire en_P;\n\tinput wire move;\n\tinput wire clock;\n\tinput wire reset_paddle;\n\tinput wire up;\n\toutput wire [8:0] Q_P;\n\twire cout;\n\twire bounds0lt;\n\twire bounds1gt;\n\treg [8:0] AddIn;\n\twire [8:0] D_P;\n\twire [8:0] M_P;\n\tRegister #(.WIDTH(9)) PaddleRow(\n\t\t.en(en_P),\n\t\t.clear(1'b0),\n\t\t.D(D_P),\n\t\t.Q(Q_P),\n\t\t.clock(clock)\n\t);\n\tAdder #(.WIDTH(9)) PaddleRowAdd(\n\t\t.A(AddIn),\n\t\t.B(Q_P),\n\t\t.Cin(1'b0),\n\t\t.Sum(M_P),\n\t\t.Cout(cout)\n\t);\n\tMux2to1 #(.WIDTH(9)) resetPaddle(\n\t\t.I0(M_P),\n\t\t.I1(9'd215),\n\t\t.S(reset_paddle),\n\t\t.Y(D_P)\n\t);\n\tMagComp #(.WIDTH(9)) bounds0(\n\t\t.A(Q_P),\n\t\t.B(9'd5),\n\t\t.AltB(bounds0lt),\n\t\t.AgtB(),\n\t\t.AeqB()\n\t);\n\tMagComp #(.WIDTH(9)) bounds1(\n\t\t.A(Q_P),\n\t\t.B(9'd426),\n\t\t.AltB(),\n\t\t.AgtB(bounds1gt),\n\t\t.AeqB()\n\t);\n\talways @(*)\n\t\tif (bounds0lt & up)\n\t\t\tcase (Q_P)\n\t\t\t\t9'd4: AddIn = 9'b111111100;\n\t\t\t\t9'd3: AddIn = 9'b111111101;\n\t\t\t\t9'd2: AddIn = 9'b111111110;\n\t\t\t\t9'd1: AddIn = 9'b111111111;\n\t\t\t\tdefault: AddIn = 9'd0;\n\t\t\tendcase\n\t\telse if (bounds1gt & ~up)\n\t\t\tcase (Q_P)\n\t\t\t\t9'd427: AddIn = 9'd4;\n\t\t\t\t9'd428: AddIn = 9'd3;\n\t\t\t\t9'd429: AddIn = 9'd2;\n\t\t\t\t9'd430: AddIn = 9'd1;\n\t\t\t\tdefault: AddIn = 9'd0;\n\t\t\tendcase\n\t\telse if (move & ~up)\n\t\t\tAddIn = 9'd5;\n\t\telse if (move & up)\n\t\t\tAddIn = 9'b111111011;\n\t\telse\n\t\t\tAddIn = 9'd0;\nendmodule\nmodule Color (\n\tVGA_row,\n\tVGA_col,\n\tQ_BC,\n\tQ_BR,\n\tQ_LP,\n\tQ_RP,\n\tshowScoreLeft,\n\tshowScoreRight,\n\tisB_L1,\n\tisB_R1,\n\tisB_L2,\n\tisB_R2,\n\tisB_L3,\n\tisB_R3,\n\tisB_L4,\n\tisB_R4,\n\tVGA_R,\n\tVGA_G,\n\tVGA_B\n);\n\tinput wire [8:0] VGA_row;\n\tinput wire [9:0] VGA_col;\n\tinput wire [9:0] Q_BC;\n\tinput wire [8:0] Q_BR;\n\tinput wire [8:0] Q_LP;\n\tinput wire [8:0] Q_RP;\n\tinput wire showScoreLeft;\n\tinput wire showScoreRight;\n\tinput wire isB_L1;\n\tinput wire isB_R1;\n\tinput wire isB_L2;\n\tinput wire isB_R2;\n\tinput wire isB_L3;\n\tinput wire isB_R3;\n\tinput wire isB_L4;\n\tinput wire isB_R4;\n\toutput reg VGA_R;\n\toutput reg VGA_G;\n\toutput reg VGA_B;\n\twire BR_isB;\n\twire BC_isB;\n\twire LPR_isB;\n\twire LPC_isB;\n\twire RPR_isB;\n\twire RPC_isB;\n\twire rowBound;\n\twire rowBound1;\n\twire colBound;\n\twire colBound1;\n\twire RSC_isB;\n\twire LSC_isB;\n\twire SR_isB;\n\twire showScore;\n\tassign showScore = showScoreLeft | showScoreRight;\n\tOffsetCheck #(.WIDTH(9)) BallRow(\n\t\t.low(Q_BR),\n\t\t.delta(9'd3),\n\t\t.val(VGA_row),\n\t\t.is_between(BR_isB)\n\t);\n\tOffsetCheck #(.WIDTH(10)) BallCol(\n\t\t.low(Q_BC),\n\t\t.delta(10'd3),\n\t\t.val(VGA_col),\n\t\t.is_between(BC_isB)\n\t);\n\tOffsetCheck #(.WIDTH(9)) LPaddleRow(\n\t\t.low(Q_LP),\n\t\t.delta(9'd47),\n\t\t.val(VGA_row),\n\t\t.is_between(LPR_isB)\n\t);\n\tOffsetCheck #(.WIDTH(10)) LPaddleCol(\n\t\t.low(10'd60),\n\t\t.delta(10'd3),\n\t\t.val(VGA_col),\n\t\t.is_between(LPC_isB)\n\t);\n\tOffsetCheck #(.WIDTH(9)) RPaddleRow(\n\t\t.low(Q_RP),\n\t\t.delta(9'd47),\n\t\t.val(VGA_row),\n\t\t.is_between(RPR_isB)\n\t);\n\tOffsetCheck #(.WIDTH(10)) RPaddleCol(\n\t\t.low(10'd577),\n\t\t.delta(10'd3),\n\t\t.val(VGA_col),\n\t\t.is_between(RPC_isB)\n\t);\n\tRangeCheck #(.WIDTH(10)) rightScoreCol(\n\t\t.low(10'd470),\n\t\t.high(10'd490),\n\t\t.val(VGA_col),\n\t\t.is_between(RSC_isB)\n\t);\n\tRangeCheck #(.WIDTH(10)) leftScoreCol(\n\t\t.low(10'd150),\n\t\t.high(10'd170),\n\t\t.val(VGA_col),\n\t\t.is_between(LSC_isB)\n\t);\n\tRangeCheck #(.WIDTH(9)) ScoreRow(\n\t\t.low(9'd230),\n\t\t.high(9'd250),\n\t\t.val(VGA_row),\n\t\t.is_between(SR_isB)\n\t);\n\tMagComp #(.WIDTH(9)) RowBoundary(\n\t\t.A(9'd0),\n\t\t.B(VGA_row),\n\t\t.AeqB(rowBound),\n\t\t.AltB(),\n\t\t.AgtB()\n\t);\n\tMagComp #(.WIDTH(9)) RowBoundary1(\n\t\t.A(9'd479),\n\t\t.B(VGA_row),\n\t\t.AeqB(rowBound1),\n\t\t.AltB(),\n\t\t.AgtB()\n\t);\n\tMagComp #(.WIDTH(10)) ColBoundary(\n\t\t.A(10'd0),\n\t\t.B(VGA_col),\n\t\t.AeqB(colBound),\n\t\t.AltB(),\n\t\t.AgtB()\n\t);\n\tMagComp #(.WIDTH(10)) ColBoundary1(\n\t\t.A(10'd639),\n\t\t.B(VGA_col),\n\t\t.AeqB(colBound1),\n\t\t.AltB(),\n\t\t.AgtB()\n\t);\n\talways @(*)\n\t\tif (BR_isB & BC_isB) begin\n\t\t\tVGA_R = 1'b1;\n\t\t\tVGA_G = 1'b1;\n\t\t\tVGA_B = 1'b1;\n\t\tend\n\t\telse if (LPR_isB & LPC_isB) begin\n\t\t\tVGA_R = 1'b1;\n\t\t\tVGA_G = 1'b1;\n\t\t\tVGA_B = 1'b0;\n\t\tend\n\t\telse if (RPR_isB & RPC_isB) begin\n\t\t\tVGA_R = 1'b0;\n\t\t\tVGA_G = 1'b1;\n\t\t\tVGA_B = 1'b1;\n\t\tend\n\t\telse if (((rowBound | rowBound1) | colBound) | colBound1) begin\n\t\t\tVGA_R = 1'b1;\n\t\t\tVGA_G = 1'b0;\n\t\t\tVGA_B = 1'b0;\n\t\tend\n\t\telse if ((RSC_isB & SR_isB) & showScoreRight) begin\n\t\t\tVGA_R = 1'b0;\n\t\t\tVGA_G = 1'b1;\n\t\t\tVGA_B = 1'b0;\n\t\tend\n\t\telse if ((LSC_isB & SR_isB) & showScoreLeft) begin\n\t\t\tVGA_R = 1'b0;\n\t\t\tVGA_G = 1'b1;\n\t\t\tVGA_B = 1'b0;\n\t\tend\n\t\telse if ((isB_L1 | isB_R1) & showScore) begin\n\t\t\tVGA_R = 1'b1;\n\t\t\tVGA_G = 1'b0;\n\t\t\tVGA_B = 1'b1;\n\t\tend\n\t\telse if ((isB_L2 | isB_R2) & showScore) begin\n\t\t\tVGA_R = 1'b0;\n\t\t\tVGA_G = 1'b0;\n\t\t\tVGA_B = 1'b1;\n\t\tend\n\t\telse if ((isB_L3 | isB_R3) & showScore) begin\n\t\t\tVGA_R = 1'b0;\n\t\t\tVGA_G = 1'b1;\n\t\t\tVGA_B = 1'b0;\n\t\tend\n\t\telse if ((isB_L4 | isB_R4) & showScore) begin\n\t\t\tVGA_R = 1'b1;\n\t\t\tVGA_G = 1'b1;\n\t\t\tVGA_B = 1'b0;\n\t\tend\n\t\telse begin\n\t\t\tVGA_R = 1'b0;\n\t\t\tVGA_G = 1'b0;\n\t\t\tVGA_B = 1'b0;\n\t\tend\nendmodule\nmodule Scoring (\n\ten_Rscore,\n\ten_Lscore,\n\tclr_score,\n\tCLOCK_50,\n\tL1,\n\tL2,\n\tL3,\n\tL4,\n\tR1,\n\tR2,\n\tR3,\n\tR4\n);\n\tinput wire en_Rscore;\n\tinput wire en_Lscore;\n\tinput wire clr_score;\n\tinput wire CLOCK_50;\n\toutput wire [3:0] L1;\n\toutput wire [3:0] L2;\n\toutput wire [3:0] L3;\n\toutput wire [3:0] L4;\n\toutput wire [3:0] R1;\n\toutput wire [3:0] R2;\n\toutput wire [3:0] R3;\n\toutput wire [3:0] R4;\n\twire L1_gt9;\n\twire L2_gt9;\n\twire L3_gt9;\n\twire L4_gt9;\n\twire R1_gt9;\n\twire R2_gt9;\n\twire R3_gt9;\n\twire R4_gt9;\n\twire clr_L1;\n\twire clr_L2;\n\twire clr_L3;\n\twire clr_L4;\n\twire clr_R1;\n\twire clr_R2;\n\twire clr_R3;\n\twire clr_R4;\n\tMagComp #(.WIDTH(4)) L1gt9(\n\t\t.A(L1),\n\t\t.B(4'd9),\n\t\t.AgtB(L1_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(4)) L2gt9(\n\t\t.A(L2),\n\t\t.B(4'd9),\n\t\t.AgtB(L2_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(4)) L3gt9(\n\t\t.A(L3),\n\t\t.B(4'd9),\n\t\t.AgtB(L3_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(4)) L4gt9(\n\t\t.A(L4),\n\t\t.B(4'd9),\n\t\t.AgtB(L4_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(4)) R1gt9(\n\t\t.A(R1),\n\t\t.B(4'd9),\n\t\t.AgtB(R1_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(4)) R2gt9(\n\t\t.A(R2),\n\t\t.B(4'd9),\n\t\t.AgtB(R2_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(4)) R3gt9(\n\t\t.A(R3),\n\t\t.B(4'd9),\n\t\t.AgtB(R3_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(4)) R4gt9(\n\t\t.A(R4),\n\t\t.B(4'd9),\n\t\t.AgtB(R4_gt9),\n\t\t.AeqB(),\n\t\t.AltB()\n\t);\n\tassign clr_L1 = L1_gt9 | clr_score;\n\tassign clr_L2 = L2_gt9 | clr_score;\n\tassign clr_L3 = L3_gt9 | clr_score;\n\tassign clr_L4 = L4_gt9 | clr_score;\n\tassign clr_R1 = R1_gt9 | clr_score;\n\tassign clr_R2 = R2_gt9 | clr_score;\n\tassign clr_R3 = R3_gt9 | clr_score;\n\tassign clr_R4 = R4_gt9 | clr_score;\n\tCounter #(.WIDTH(4)) LScore1(\n\t\t.en(en_Lscore),\n\t\t.clear(clr_L1),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(L1)\n\t);\n\tCounter #(.WIDTH(4)) LScore2(\n\t\t.en(L1_gt9),\n\t\t.clear(clr_L2),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(L2)\n\t);\n\tCounter #(.WIDTH(4)) LScore3(\n\t\t.en(L2_gt9),\n\t\t.clear(clr_L3),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(L3)\n\t);\n\tCounter #(.WIDTH(4)) LScore4(\n\t\t.en(L3_gt9),\n\t\t.clear(clr_L4),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(L4)\n\t);\n\tCounter #(.WIDTH(4)) RScore1(\n\t\t.en(en_Rscore),\n\t\t.clear(clr_R1),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(R1)\n\t);\n\tCounter #(.WIDTH(4)) RScore2(\n\t\t.en(R1_gt9),\n\t\t.clear(clr_R2),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(R2)\n\t);\n\tCounter #(.WIDTH(4)) RScore3(\n\t\t.en(R2_gt9),\n\t\t.clear(clr_R3),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(R3)\n\t);\n\tCounter #(.WIDTH(4)) RScore4(\n\t\t.en(R3_gt9),\n\t\t.clear(clr_R4),\n\t\t.load(1'b0),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(4'b0000),\n\t\t.Q(R4)\n\t);\nendmodule\nmodule ScoreOnDisplay (\n\trowChoice,\n\tcurr_row,\n\tcolChoice,\n\tcurr_col,\n\thexOutput_L,\n\tis_between\n);\n\tinput wire [8:0] rowChoice;\n\tinput wire [8:0] curr_row;\n\tinput wire [9:0] colChoice;\n\tinput wire [9:0] curr_col;\n\tinput wire [6:0] hexOutput_L;\n\toutput wire is_between;\n\twire [9:0] a1_out;\n\twire [8:0] a2_out;\n\twire [8:0] a3_out;\n\twire isB_Arow;\n\twire isB_Acol;\n\twire isB_Brow;\n\twire isB_Bcol;\n\twire isB_Crow;\n\twire isB_Ccol;\n\twire isB_Drow;\n\twire isB_Dcol;\n\twire isB_Erow;\n\twire isB_Ecol;\n\twire isB_Frow;\n\twire isB_Fcol;\n\twire isB_Grow;\n\twire isB_Gcol;\n\twire isA;\n\twire isB;\n\twire isC;\n\twire isD;\n\twire isE;\n\twire isF;\n\twire isG;\n\tassign isA = (isB_Arow & isB_Acol) & ~hexOutput_L[0];\n\tassign isB = (isB_Brow & isB_Bcol) & ~hexOutput_L[1];\n\tassign isC = (isB_Crow & isB_Ccol) & ~hexOutput_L[2];\n\tassign isD = (isB_Drow & isB_Dcol) & ~hexOutput_L[3];\n\tassign isE = (isB_Erow & isB_Ecol) & ~hexOutput_L[4];\n\tassign isF = (isB_Frow & isB_Fcol) & ~hexOutput_L[5];\n\tassign isG = (isB_Grow & isB_Gcol) & ~hexOutput_L[6];\n\tassign is_between = (((((isA | isB) | isC) | isD) | isE) | isF) | isG;\n\tAdder #(.WIDTH(10)) a1(\n\t\t.A(colChoice),\n\t\t.B(10'd20),\n\t\t.Sum(a1_out),\n\t\t.Cout(),\n\t\t.Cin(1'b0)\n\t);\n\tAdder #(.WIDTH(9)) a2(\n\t\t.A(rowChoice),\n\t\t.B(9'd20),\n\t\t.Sum(a2_out),\n\t\t.Cout(),\n\t\t.Cin(1'b0)\n\t);\n\tAdder #(.WIDTH(9)) a3(\n\t\t.A(rowChoice),\n\t\t.B(9'd40),\n\t\t.Sum(a3_out),\n\t\t.Cout(),\n\t\t.Cin(1'b0)\n\t);\n\tOffsetCheck #(.WIDTH(9)) A_row(\n\t\t.low(rowChoice),\n\t\t.delta(9'd2),\n\t\t.val(curr_row),\n\t\t.is_between(isB_Arow)\n\t);\n\tOffsetCheck #(.WIDTH(10)) A_col(\n\t\t.low(colChoice),\n\t\t.delta(10'd20),\n\t\t.val(curr_col),\n\t\t.is_between(isB_Acol)\n\t);\n\tOffsetCheck #(.WIDTH(9)) B_row(\n\t\t.low(rowChoice),\n\t\t.delta(9'd20),\n\t\t.val(curr_row),\n\t\t.is_between(isB_Brow)\n\t);\n\tOffsetCheck #(.WIDTH(10)) B_col(\n\t\t.low(a1_out),\n\t\t.delta(10'd2),\n\t\t.val(curr_col),\n\t\t.is_between(isB_Bcol)\n\t);\n\tOffsetCheck #(.WIDTH(9)) C_row(\n\t\t.low(rowChoice + 9'd20),\n\t\t.delta(9'd20),\n\t\t.val(curr_row),\n\t\t.is_between(isB_Crow)\n\t);\n\tOffsetCheck #(.WIDTH(10)) C_col(\n\t\t.low(a1_out),\n\t\t.delta(10'd2),\n\t\t.val(curr_col),\n\t\t.is_between(isB_Ccol)\n\t);\n\tOffsetCheck #(.WIDTH(9)) D_row(\n\t\t.low(a3_out),\n\t\t.delta(9'd2),\n\t\t.val(curr_row),\n\t\t.is_between(isB_Drow)\n\t);\n\tOffsetCheck #(.WIDTH(10)) D_col(\n\t\t.low(colChoice),\n\t\t.delta(10'd20),\n\t\t.val(curr_col),\n\t\t.is_between(isB_Dcol)\n\t);\n\tOffsetCheck #(.WIDTH(9)) E_row(\n\t\t.low(a2_out),\n\t\t.delta(9'd20),\n\t\t.val(curr_row),\n\t\t.is_between(isB_Erow)\n\t);\n\tOffsetCheck #(.WIDTH(10)) E_col(\n\t\t.low(colChoice),\n\t\t.delta(10'd2),\n\t\t.val(curr_col),\n\t\t.is_between(isB_Ecol)\n\t);\n\tOffsetCheck #(.WIDTH(9)) F_row(\n\t\t.low(rowChoice),\n\t\t.delta(9'd20),\n\t\t.val(curr_row),\n\t\t.is_between(isB_Frow)\n\t);\n\tOffsetCheck #(.WIDTH(10)) F_col(\n\t\t.low(colChoice),\n\t\t.delta(10'd2),\n\t\t.val(curr_col),\n\t\t.is_between(isB_Fcol)\n\t);\n\tOffsetCheck #(.WIDTH(9)) G_row(\n\t\t.low(a2_out),\n\t\t.delta(9'd2),\n\t\t.val(curr_row),\n\t\t.is_between(isB_Grow)\n\t);\n\tOffsetCheck #(.WIDTH(10)) G_col(\n\t\t.low(colChoice),\n\t\t.delta(10'd20),\n\t\t.val(curr_col),\n\t\t.is_between(isB_Gcol)\n\t);\nendmodule\nmodule vga (\n\tCLOCK_50,\n\treset,\n\tHS,\n\tVS,\n\tblank,\n\trow,\n\tcol\n);\n\tinput wire CLOCK_50;\n\tinput wire reset;\n\toutput wire HS;\n\toutput wire VS;\n\toutput wire blank;\n\toutput wire [8:0] row;\n\toutput wire [9:0] col;\n\treg en_vs;\n\twire en_hs;\n\twire en_row;\n\twire en_col;\n\treg clear_vs;\n\twire clear_hs;\n\treg clear_row;\n\twire clear_col;\n\twire [19:0] Q_VS;\n\treg [19:0] D_VS;\n\twire [10:0] Q_HS;\n\treg [10:0] D_HS;\n\twire [8:0] Q_row;\n\twire [9:0] Q_col;\n\treg load_vs;\n\treg load_hs;\n\twire VS_done;\n\twire HS_done;\n\twire isB_vp;\n\twire isB_vd;\n\twire isB_hp;\n\twire isB_hd;\n\tMagComp #(.WIDTH(20)) vs_done(\n\t\t.A(Q_VS),\n\t\t.B(20'd833599),\n\t\t.AeqB(VS_done),\n\t\t.AgtB(),\n\t\t.AltB()\n\t);\n\tMagComp #(.WIDTH(11)) hs_done(\n\t\t.A(Q_HS),\n\t\t.B(11'd1599),\n\t\t.AeqB(HS_done),\n\t\t.AgtB(),\n\t\t.AltB()\n\t);\n\tCounter #(.WIDTH(20)) VSCounter(\n\t\t.en(en_vs),\n\t\t.clear(clear_vs),\n\t\t.load(load_vs),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(D_VS),\n\t\t.Q(Q_VS)\n\t);\n\tCounter #(.WIDTH(11)) HSCounter(\n\t\t.en(en_hs),\n\t\t.clear(clear_hs),\n\t\t.load(load_hs),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(D_HS),\n\t\t.Q(Q_HS)\n\t);\n\tCounter #(.WIDTH(9)) RowCounter(\n\t\t.en(en_row),\n\t\t.clear(clear_row),\n\t\t.load(),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(),\n\t\t.Q(Q_row)\n\t);\n\tCounter #(.WIDTH(10)) ColCounter(\n\t\t.en(en_col),\n\t\t.clear(clear_col),\n\t\t.load(),\n\t\t.up(1'b1),\n\t\t.clock(CLOCK_50),\n\t\t.D(),\n\t\t.Q(Q_col)\n\t);\n\tRangeCheck #(.WIDTH(20)) VS_pulse(\n\t\t.val(Q_VS),\n\t\t.high(20'd3199),\n\t\t.low(20'd0),\n\t\t.is_between(isB_vp)\n\t);\n\tRangeCheck #(.WIDTH(20)) VS_display(\n\t\t.val(Q_VS),\n\t\t.high(20'd817599),\n\t\t.low(20'd49600),\n\t\t.is_between(isB_vd)\n\t);\n\tRangeCheck #(.WIDTH(11)) HS_pulse(\n\t\t.val(Q_HS),\n\t\t.high(11'd191),\n\t\t.low(11'd0),\n\t\t.is_between(isB_hp)\n\t);\n\tRangeCheck #(.WIDTH(11)) HS_display(\n\t\t.val(Q_HS),\n\t\t.high(11'd1567),\n\t\t.low(11'd288),\n\t\t.is_between(isB_hd)\n\t);\n\twire [1:0] currState;\n\treg [1:0] nextState;\n\tDFlipFlop dff0(\n\t\t.D(nextState[0]),\n\t\t.Q(currState[0]),\n\t\t.clock(CLOCK_50),\n\t\t.reset_L(~reset),\n\t\t.preset_L(1'b1)\n\t);\n\tDFlipFlop dff1(\n\t\t.D(nextState[1]),\n\t\t.Q(currState[1]),\n\t\t.clock(CLOCK_50),\n\t\t.reset_L(~reset),\n\t\t.preset_L(1'b1)\n\t);\n\tassign en_col = ~Q_HS[0] & isB_hd;\n\tassign en_row = HS_done & isB_vd;\n\tassign en_hs = ~HS_done;\n\tassign clear_hs = HS_done;\n\tassign clear_col = HS_done | (currState == 2'b00);\n\talways @(*) begin\n\t\ten_vs = 1'b0;\n\t\tload_vs = 1'b0;\n\t\tload_hs = 1'b0;\n\t\tclear_vs = 1'b0;\n\t\tD_HS = 11'd0;\n\t\tD_VS = 20'd0;\n\t\tclear_row = 1'b0;\n\t\tcase (currState)\n\t\t\t2'b00: begin\n\t\t\t\tnextState = 2'b01;\n\t\t\t\tclear_row = 1'b1;\n\t\t\t\tload_vs = 1'b1;\n\t\t\t\tload_hs = 1'b1;\n\t\t\t\tD_HS = 11'd1;\n\t\t\t\tD_VS = 20'd1;\n\t\t\t\ten_vs = 1'b0;\n\t\t\tend\n\t\t\t2'b01:\n\t\t\t\tif (VS_done) begin\n\t\t\t\t\tnextState = 2'b10;\n\t\t\t\t\tclear_vs = 1'b1;\n\t\t\t\t\tclear_row = 1'b1;\n\t\t\t\t\ten_vs = 1'b0;\n\t\t\t\tend\n\t\t\t\telse begin\n\t\t\t\t\tnextState = 2'b01;\n\t\t\t\t\ten_vs = 1'b1;\n\t\t\t\t\tclear_row = 1'b0;\n\t\t\t\t\tload_vs = 1'b0;\n\t\t\t\t\tload_hs = 1'b0;\n\t\t\t\tend\n\t\t\t2'b10: begin\n\t\t\t\tnextState = 2'b01;\n\t\t\t\ten_vs = 1'b1;\n\t\t\t\tclear_vs = 1'b0;\n\t\t\t\tclear_row = 1'b0;\n\t\t\tend\n\t\t\tdefault:\n\t\t\t\tnextState = 2'b00;\n\t\tendcase\n\tend\n\tassign HS = ~isB_hp;\n\tassign VS = ~isB_vp;\n\tassign blank = ~(isB_vd & isB_hd);\n\tassign row = Q_row;\n\tassign col = Q_col;\nendmodule\nmodule Adder (\n\tA,\n\tB,\n\tCin,\n\tSum,\n\tCout\n);\n\tparameter WIDTH = 8;\n\tinput wire [WIDTH - 1:0] A;\n\tinput wire [WIDTH - 1:0] B;\n\tinput wire Cin;\n\toutput wire [WIDTH - 1:0] Sum;\n\toutput wire Cout;\n\tassign {Cout, Sum} = (A + B) + Cin;\nendmodule\nmodule Mux2to1 (\n\tI0,\n\tI1,\n\tS,\n\tY\n);\n\tparameter WIDTH = 8;\n\tinput wire [WIDTH - 1:0] I0;\n\tinput wire [WIDTH - 1:0] I1;\n\tinput wire S;\n\toutput wire [WIDTH - 1:0] Y;\n\tassign Y = (S ? I1 : I0);\nendmodule\nmodule DFlipFlop (\n\tQ,\n\tD,\n\tclock,\n\treset_L,\n\tpreset_L\n);\n\toutput reg Q;\n\tinput wire D;\n\tinput wire clock;\n\tinput wire reset_L;\n\tinput wire preset_L;\n\talways @(posedge clock)\n\t\tif (~reset_L)\n\t\t\tQ <= 0;\n\t\telse if (~preset_L)\n\t\t\tQ <= 1;\n\t\telse\n\t\t\tQ <= D;\nendmodule\nmodule Register (\n\ten,\n\tclear,\n\tclock,\n\tD,\n\tQ\n);\n\tparameter WIDTH = 8;\n\tinput wire en;\n\tinput wire clear;\n\tinput wire clock;\n\tinput wire [WIDTH - 1:0] D;\n\toutput reg [WIDTH - 1:0] Q;\n\talways @(posedge clock)\n\t\tif (en)\n\t\t\tQ <= D;\n\t\telse if (clear)\n\t\t\tQ <= 1'sb0;\nendmodule\nmodule Counter (\n\ten,\n\tclear,\n\tload,\n\tup,\n\tclock,\n\tD,\n\tQ\n);\n\tparameter WIDTH = 8;\n\tinput wire en;\n\tinput wire clear;\n\tinput wire load;\n\tinput wire up;\n\tinput wire clock;\n\tinput wire [WIDTH - 1:0] D;\n\toutput reg [WIDTH - 1:0] Q;\n\talways @(posedge clock)\n\t\tif (clear)\n\t\t\tQ <= 1'sb0;\n\t\telse if (load)\n\t\t\tQ <= D;\n\t\telse if (en & up)\n\t\t\tQ <= Q + 1;\n\t\telse if (en & ~up)\n\t\t\tQ <= Q - 1;\nendmodule\nmodule Synchronizer (\n\tasync,\n\tclock,\n\tsync\n);\n\tinput wire async;\n\tinput wire clock;\n\toutput reg sync;\n\treg async_1;\n\talways @(posedge clock) begin\n\t\tasync_1 <= async;\n\t\tsync <= async_1;\n\tend\nendmodule\nmodule MagComp (\n\tA,\n\tB,\n\tAltB,\n\tAeqB,\n\tAgtB\n);\n\tparameter WIDTH = 8;\n\tinput wire [WIDTH - 1:0] A;\n\tinput wire [WIDTH - 1:0] B;\n\toutput wire AltB;\n\toutput wire AeqB;\n\toutput wire AgtB;\n\tassign AeqB = A == B;\n\tassign AltB = A < B;\n\tassign AgtB = A > B;\nendmodule\nmodule RangeCheck (\n\tval,\n\thigh,\n\tlow,\n\tis_between\n);\n\tparameter WIDTH = 8;\n\tinput wire [WIDTH - 1:0] val;\n\tinput wire [WIDTH - 1:0] high;\n\tinput wire [WIDTH - 1:0] low;\n\toutput reg is_between;\n\twire valLtHigh;\n\twire valGtHigh;\n\twire valEqHigh;\n\twire valLtLow;\n\twire valGtLow;\n\twire valEqLow;\n\tMagComp #(.WIDTH(WIDTH)) comp1(\n\t\t.A(val),\n\t\t.B(high),\n\t\t.AeqB(valEqHigh),\n\t\t.AgtB(valGtHigh),\n\t\t.AltB(valLtHigh)\n\t);\n\tMagComp #(.WIDTH(WIDTH)) comp2(\n\t\t.A(val),\n\t\t.B(low),\n\t\t.AeqB(valEqLow),\n\t\t.AgtB(valGtLow),\n\t\t.AltB(valLtLow)\n\t);\n\talways @(*)\n\t\tif (valGtHigh | valLtLow)\n\t\t\tis_between = 1'b0;\n\t\telse\n\t\t\tis_between = 1'b1;\nendmodule\nmodule OffsetCheck (\n\tdelta,\n\tlow,\n\tval,\n\tis_between\n);\n\tparameter WIDTH = 8;\n\tinput wire [WIDTH - 1:0] delta;\n\tinput wire [WIDTH - 1:0] low;\n\tinput wire [WIDTH - 1:0] val;\n\toutput wire is_between;\n\twire [WIDTH - 1:0] sum;\n\twire cout;\n\twire [WIDTH:0] full_sum;\n\twire [WIDTH:0] full_val;\n\twire [WIDTH:0] full_low;\n\tAdder #(.WIDTH(WIDTH)) add(\n\t\t.A(low),\n\t\t.B(delta),\n\t\t.Cin(1'b0),\n\t\t.Sum(sum),\n\t\t.Cout(cout)\n\t);\n\tassign full_sum = {cout, sum};\n\tassign full_val = {1'b0, val};\n\tassign full_low = {1'b0, low};\n\tRangeCheck #(.WIDTH(WIDTH + 1)) rc(\n\t\t.val(full_val),\n\t\t.high(full_sum),\n\t\t.low(full_low),\n\t\t.is_between(is_between)\n\t);\nendmodule\n", "mask_idx": {"conditional_statement": [[19099, 20111], [30342, 30370], [19285, 20111], [29955, 29980], [15237, 15327], [19629, 20111]], "blocking_assignment": [[12459, 12479], [12048, 12061], [19347, 19360], [19038, 19051], [28325, 28343], [15253, 15265], [9107, 9121], [2863, 2888]], "module_program_interface_instantiation": [[24869, 24980], [18208, 18326], [6134, 6273], [22331, 22472], [21286, 21377], [15078, 15179], [25780, 25895], [18558, 18662], [8817, 8937], [6275, 6415], [10214, 10332], [22754, 22892], [7616, 7767], [7004, 7155], [17978, 18089]], "always_construct": [[18994, 20111], [31373, 31463], [30499, 30572], [8939, 9121], [16128, 16636], [29903, 29980]], "case_statement": [[16165, 16341], [2522, 2936], [28288, 28878], [10806, 12744], [16373, 16525]], "ansi_port_declaration": [[12920, 12925], [3145, 3151], [20212, 20215], [15397, 15400]], "continuous_assign": [[28039, 28063], [17479, 17529], [23644, 23697], [1218, 1243], [1191, 1216]], "parameter_declaration": [[29061, 29081], [29293, 29313], [31531, 31551], [30052, 30072], [29769, 29789], [30632, 30652]], "nonblocking_assignment": [[29969, 29980], [30531, 30548], [29683, 29690]]}, "all_mask_idx": {"module_program_interface_instantiation": [[1373, 1882], [1884, 1945], [1947, 2008], [2010, 2071], [2073, 2134], [2136, 2197], [2199, 2260], [2262, 2323], [2325, 2386], [4660, 4778], [4780, 4865], [4867, 4950], [4952, 5031], [5033, 5116], [5118, 5197], [5199, 5772], [5774, 6132], [6134, 6273], [6275, 6415], [6417, 6801], [6803, 7002], [7004, 7155], [7157, 7308], [7310, 7461], [7463, 7614], [7616, 7767], [7769, 7920], [7922, 8072], [8074, 8225], [8227, 8327], [8504, 8598], [8600, 8695], [8697, 8815], [8817, 8937], [9974, 10092], [10094, 10212], [10214, 10332], [10334, 10452], [13540, 13644], [13646, 13751], [13753, 13844], [13846, 13947], [13949, 14057], [14059, 14170], [14172, 14274], [14276, 14380], [14382, 14474], [14476, 14573], [14575, 14670], [14672, 14769], [14771, 14862], [14864, 14957], [14959, 15076], [15078, 15179], [15624, 15727], [15729, 15830], [15832, 15926], [15928, 16025], [16027, 16126], [17531, 17637], [17639, 17747], [17749, 17860], [17862, 17976], [17978, 18089], [18091, 18206], [18208, 18326], [18328, 18445], [18447, 18556], [18558, 18662], [18664, 18772], [18774, 18880], [18882, 18992], [20728, 20819], [20821, 20912], [20914, 21005], [21007, 21098], [21100, 21191], [21193, 21284], [21286, 21377], [21379, 21470], [21768, 21909], [21911, 22049], [22051, 22189], [22191, 22329], [22331, 22472], [22474, 22612], [22614, 22752], [22754, 22892], [23991, 24089], [24091, 24187], [24189, 24285], [24287, 24399], [24401, 24516], [24518, 24631], [24633, 24744], [24746, 24867], [24869, 24980], [24982, 25091], [25093, 25208], [25210, 25320], [25322, 25436], [25438, 25551], [25553, 25667], [25669, 25778], [25780, 25895], [26457, 26560], [26562, 26663], [26665, 26809], [26811, 26955], [26957, 27093], [27095, 27232], [27234, 27342], [27344, 27460], [27462, 27569], [27571, 27683], [27730, 27847], [27849, 27966], [31139, 31256], [31258, 31371], [31788, 31884], [31982, 32102]], "continuous_assign": [[847, 879], [881, 911], [913, 945], [947, 977], [979, 1012], [1014, 1041], [1043, 1074], [1076, 1106], [1108, 1134], [1136, 1162], [1164, 1189], [1191, 1216], [1218, 1243], [1245, 1270], [1272, 1300], [1302, 1324], [1326, 1348], [1350, 1371], [8410, 8502], [15181, 15198], [15200, 15221], [17479, 17529], [21472, 21507], [21509, 21544], [21546, 21581], [21583, 21618], [21620, 21655], [21657, 21692], [21694, 21729], [21731, 21766], [23534, 23587], [23589, 23642], [23644, 23697], [23699, 23752], [23754, 23807], [23809, 23862], [23864, 23917], [23919, 23989], [27968, 28002], [28004, 28037], [28039, 28063], [28065, 28091], [28093, 28143], [28885, 28905], [28907, 28927], [28929, 28963], [28965, 28984], [28986, 29005], [29209, 29244], [29420, 29445], [30769, 30790], [30792, 30812], [30814, 30834], [31886, 31916], [31918, 31948], [31950, 31980]], "blocking_assignment": [[2548, 2573], [2583, 2608], [2618, 2643], [2653, 2678], [2688, 2713], [2723, 2748], [2758, 2783], [2793, 2818], [2828, 2853], [2863, 2888], [2901, 2926], [8367, 8382], [8393, 8408], [9007, 9021], [9082, 9096], [9107, 9121], [10474, 10494], [10497, 10518], [10521, 10542], [10545, 10564], [10567, 10584], [10587, 10605], [10608, 10624], [10627, 10644], [10647, 10660], [10663, 10676], [10679, 10695], [10698, 10714], [10717, 10734], [10737, 10754], [10757, 10778], [10781, 10803], [10845, 10865], [10870, 10886], [10891, 10909], [10914, 10934], [10939, 10960], [10965, 10986], [10991, 11008], [11013, 11026], [11031, 11044], [11049, 11065], [11070, 11086], [11148, 11168], [11183, 11203], [11226, 11246], [11251, 11270], [11275, 11291], [11296, 11309], [11314, 11327], [11332, 11348], [11353, 11369], [11399, 11419], [11424, 11442], [11447, 11463], [11468, 11481], [11486, 11499], [11504, 11520], [11525, 11541], [11599, 11619], [11663, 11683], [11719, 11739], [11754, 11774], [11797, 11817], [11822, 11835], [11840, 11853], [11858, 11874], [11879, 11895], [11925, 11945], [11950, 11966], [11971, 11991], [11996, 12017], [12022, 12043], [12048, 12061], [12066, 12079], [12084, 12101], [12106, 12122], [12127, 12143], [12173, 12193], [12198, 12214], [12219, 12239], [12244, 12265], [12270, 12291], [12296, 12309], [12314, 12327], [12332, 12349], [12354, 12370], [12375, 12391], [12459, 12479], [12494, 12514], [12519, 12540], [12608, 12628], [12643, 12663], [12668, 12690], [12714, 12734], [15253, 15265], [15292, 15304], [15315, 15327], [16186, 16207], [16218, 16239], [16250, 16271], [16282, 16303], [16317, 16330], [16396, 16409], [16422, 16435], [16448, 16461], [16474, 16487], [16501, 16514], [16552, 16565], [16591, 16612], [16623, 16636], [19038, 19051], [19055, 19068], [19072, 19085], [19131, 19144], [19148, 19161], [19165, 19178], [19224, 19237], [19241, 19254], [19258, 19271], [19347, 19360], [19364, 19377], [19381, 19394], [19458, 19471], [19475, 19488], [19492, 19505], [19568, 19581], [19585, 19598], [19602, 19615], [19673, 19686], [19690, 19703], [19707, 19720], [19778, 19791], [19795, 19808], [19812, 19825], [19883, 19896], [19900, 19913], [19917, 19930], [19988, 20001], [20005, 20018], [20022, 20035], [20058, 20071], [20075, 20088], [20092, 20105], [28165, 28178], [28181, 28196], [28199, 28214], [28217, 28233], [28236, 28249], [28252, 28265], [28268, 28285], [28325, 28343], [28348, 28365], [28370, 28385], [28390, 28405], [28410, 28423], [28428, 28441], [28446, 28459], [28505, 28523], [28529, 28545], [28551, 28568], [28574, 28587], [28616, 28634], [28640, 28653], [28659, 28676], [28682, 28697], [28703, 28718], [28747, 28765], [28770, 28783], [28788, 28804], [28809, 28826], [28850, 28868], [31416, 31434], [31445, 31463]], "nonblocking_assignment": [[29650, 29657], [29683, 29690], [29701, 29708], [29940, 29947], [29969, 29980], [30260, 30271], [30292, 30299], [30323, 30334], [30359, 30370], [30531, 30548], [30551, 30567]], "case_statement": [[2522, 2936], [10806, 12744], [16165, 16341], [16373, 16525], [28288, 28878]], "conditional_statement": [[8343, 8408], [8953, 9121], [9029, 9121], [11110, 11203], [11565, 11774], [11629, 11774], [11693, 11774], [12421, 12514], [12570, 12663], [15237, 15327], [15273, 15327], [16142, 16636], [16349, 16636], [16533, 16636], [16573, 16636], [19008, 20111], [19099, 20111], [19192, 20111], [19285, 20111], [19408, 20111], [19519, 20111], [19629, 20111], [19734, 20111], [19839, 20111], [19944, 20111], [28481, 28726], [29633, 29708], [29665, 29708], [29929, 29980], [29955, 29980], [30246, 30370], [30279, 30370], [30307, 30370], [30342, 30370], [31387, 31463]], "always_construct": [[2508, 2936], [8329, 8408], [8939, 9121], [10454, 12749], [15223, 15327], [16128, 16636], [18994, 20111], [28145, 28883], [29607, 29708], [29903, 29980], [30220, 30370], [30499, 30572], [31373, 31463]], "parameter_declaration": [[29061, 29081], [29293, 29313], [29769, 29789], [30052, 30072], [30632, 30652], [30900, 30920], [31531, 31551]], "ansi_port_declaration": [[51, 57], [59, 66], [68, 75], [77, 85], [87, 94], [96, 100], [102, 106], [108, 113], [2420, 2430], [2432, 2443], [2962, 2976], [2978, 2986], [2988, 2997], [2999, 3012], [3014, 3025], [3027, 3040], [3042, 3053], [3055, 3060], [3062, 3067], [3069, 3074], [3076, 3081], [3083, 3088], [3090, 3095], [3097, 3102], [3104, 3109], [3111, 3117], [3119, 3125], [3127, 3133], [3135, 3138], [3140, 3143], [3145, 3151], [3153, 3156], [3158, 3161], [3163, 3166], [3168, 3171], [3173, 3176], [3178, 3181], [3183, 3186], [3188, 3190], [9151, 9159], [9161, 9169], [9171, 9176], [9178, 9183], [9185, 9194], [9196, 9212], [9214, 9227], [9229, 9243], [9245, 9259], [9261, 9273], [9275, 9285], [9287, 9298], [9300, 9309], [9311, 9321], [9323, 9329], [9331, 9337], [9339, 9348], [9350, 9359], [9361, 9371], [9373, 9383], [9385, 9400], [9402, 9415], [12775, 12781], [12783, 12797], [12799, 12813], [12815, 12826], [12828, 12840], [12842, 12851], [12853, 12859], [12861, 12867], [12869, 12876], [12878, 12886], [12888, 12897], [12899, 12904], [12906, 12911], [12913, 12918], [12920, 12925], [12927, 12930], [12932, 12936], [15355, 15360], [15362, 15367], [15369, 15375], [15377, 15390], [15392, 15395], [15397, 15400], [16663, 16671], [16673, 16681], [16683, 16688], [16690, 16695], [16697, 16702], [16704, 16709], [16711, 16725], [16727, 16742], [16744, 16751], [16753, 16760], [16762, 16769], [16771, 16778], [16780, 16787], [16789, 16796], [16798, 16805], [16807, 16814], [16816, 16822], [16824, 16830], [16832, 16837], [20140, 20150], [20152, 20162], [20164, 20174], [20176, 20185], [20187, 20190], [20192, 20195], [20197, 20200], [20202, 20205], [20207, 20210], [20212, 20215], [20217, 20220], [20222, 20224], [22928, 22938], [22940, 22949], [22951, 22961], [22963, 22972], [22974, 22986], [22988, 22998], [25920, 25929], [25931, 25937], [25939, 25942], [25944, 25947], [25949, 25955], [25957, 25961], [25963, 25966], [29032, 29034], [29036, 29038], [29040, 29044], [29046, 29050], [29052, 29056], [29273, 29276], [29278, 29281], [29283, 29285], [29287, 29288], [29476, 29478], [29480, 29482], [29484, 29490], [29492, 29500], [29502, 29510], [29738, 29741], [29743, 29749], [29751, 29757], [29759, 29761], [29763, 29764], [30009, 30012], [30014, 30020], [30022, 30027], [30029, 30032], [30034, 30040], [30042, 30044], [30046, 30047], [30404, 30410], [30412, 30418], [30420, 30424], [30601, 30603], [30605, 30607], [30609, 30614], [30616, 30621], [30623, 30627], [30866, 30870], [30872, 30877], [30879, 30883], [30885, 30895], [31496, 31502], [31504, 31508], [31510, 31514], [31516, 31526]]}}
{"sample_i": "wilfredkisku-tt07_wilfred_fp_mac", "topmodule": "tt_um_fp_mac", "code": "`default_nettype none\n\nmodule FP8_MUL(\n  input  [7:0] io_inputA,\n  input  [7:0] io_inputB,\n  output [7:0] io_output\n);\n  wire  signA = io_inputA[7]; // @[FP8_MUL.scala 13:20]\n  wire [4:0] expA = io_inputA[6:2]; // @[FP8_MUL.scala 14:24]\n  wire [1:0] sigA = io_inputA[1:0]; // @[FP8_MUL.scala 15:27]\n  wire  signB = io_inputB[7]; // @[FP8_MUL.scala 13:20]\n  wire [4:0] expB = io_inputB[6:2]; // @[FP8_MUL.scala 14:24]\n  wire [1:0] sigB = io_inputB[1:0]; // @[FP8_MUL.scala 15:27]\n  wire  _infFlagA_T = expA == 5'h1f; // @[FP8_MUL.scala 24:25]\n  wire  _infFlagA_T_1 = sigA == 2'h0; // @[FP8_MUL.scala 24:48]\n  wire  infFlagA = expA == 5'h1f & sigA == 2'h0; // @[FP8_MUL.scala 24:40]\n  wire  _infFlagB_T = expB == 5'h1f; // @[FP8_MUL.scala 25:25]\n  wire  _infFlagB_T_1 = sigB == 2'h0; // @[FP8_MUL.scala 25:48]\n  wire  infFlagB = expB == 5'h1f & sigB == 2'h0; // @[FP8_MUL.scala 25:40]\n  wire  _zeroFlagA_T = expA == 5'h0; // @[FP8_MUL.scala 28:26]\n  wire  zeroFlagA = expA == 5'h0 & _infFlagA_T_1; // @[FP8_MUL.scala 28:41]\n  wire  _zeroFlagB_T = expB == 5'h0; // @[FP8_MUL.scala 29:26]\n  wire  zeroFlagB = expB == 5'h0 & _infFlagB_T_1; // @[FP8_MUL.scala 29:41]\n  wire  _nanFlagA_T_1 = sigA != 2'h0; // @[FP8_MUL.scala 32:48]\n  wire  nanFlagA = _infFlagA_T & sigA != 2'h0; // @[FP8_MUL.scala 32:40]\n  wire  _nanFlagB_T_1 = sigB != 2'h0; // @[FP8_MUL.scala 33:48]\n  wire  nanFlagB = _infFlagB_T & sigB != 2'h0; // @[FP8_MUL.scala 33:40]\n  wire  subFlagA = _zeroFlagA_T & _nanFlagA_T_1; // @[FP8_MUL.scala 36:40]\n  wire  subFlagB = _zeroFlagB_T & _nanFlagB_T_1; // @[FP8_MUL.scala 37:40]\n  wire [7:0] _io_output_T = infFlagA ? io_inputA : io_inputB; // @[FP8_MUL.scala 55:23]\n  wire [7:0] _GEN_0 = infFlagA & infFlagB & signA != signB ? 8'h7f : _io_output_T; // @[FP8_MUL.scala 52:53 53:17 55:17]\n  wire [5:0] _ovrChk_6_T = expA + expB; // @[FP8_MUL.scala 61:22]\n  wire  _sigMul_6_T = ~subFlagA; // @[FP8_MUL.scala 62:21]\n  wire [2:0] _sigMul_6_T_1 = {_sigMul_6_T,sigA}; // @[Cat.scala 33:92]\n  wire  _sigMul_6_T_2 = ~subFlagB; // @[FP8_MUL.scala 62:43]\n  wire [2:0] _sigMul_6_T_3 = {_sigMul_6_T_2,sigB}; // @[Cat.scala 33:92]\n  wire [5:0] _sigMul_6_T_4 = _sigMul_6_T_1 * _sigMul_6_T_3; // @[FP8_MUL.scala 62:37]\n  wire [5:0] _GEN_4 = nanFlagA | nanFlagB ? 6'h0 : _ovrChk_6_T; // @[FP8_MUL.scala 42:14 57:35 61:14]\n  wire [5:0] _GEN_7 = infFlagA | infFlagB ? 6'h0 : _GEN_4; // @[FP8_MUL.scala 42:14 50:35]\n  wire [5:0] _GEN_10 = zeroFlagA | zeroFlagB ? 6'h0 : _GEN_7; // @[FP8_MUL.scala 42:14 48:37]\n  wire [5:0] ovrChk_6 = zeroFlagA & zeroFlagB ? 6'h0 : _GEN_10; // @[FP8_MUL.scala 42:14 45:32]\n  wire  _io_output_T_1 = signA ^ signB; // @[FP8_MUL.scala 64:30]\n  wire [7:0] _io_output_T_2 = {_io_output_T_1,7'h7c}; // @[Cat.scala 33:92]\n  wire [5:0] _io_output_T_5 = ovrChk_6 - 6'hf; // @[FP8_MUL.scala 69:50]\n  wire [5:0] _GEN_5 = nanFlagA | nanFlagB ? 6'h0 : _sigMul_6_T_4; // @[FP8_MUL.scala 43:14 57:35 62:14]\n  wire [5:0] _GEN_8 = infFlagA | infFlagB ? 6'h0 : _GEN_5; // @[FP8_MUL.scala 43:14 50:35]\n  wire [5:0] _GEN_11 = zeroFlagA | zeroFlagB ? 6'h0 : _GEN_8; // @[FP8_MUL.scala 43:14 48:37]\n  wire [5:0] sigMul_6 = zeroFlagA & zeroFlagB ? 6'h0 : _GEN_11; // @[FP8_MUL.scala 43:14 45:32]\n  wire [4:0] _GEN_15 = {{4'd0}, sigMul_6[5]}; // @[FP8_MUL.scala 69:63]\n  wire [4:0] _io_output_T_9 = _io_output_T_5[4:0] + _GEN_15; // @[FP8_MUL.scala 69:63]\n  wire [5:0] _io_output_T_11 = sigMul_6 >> sigMul_6[5]; // @[FP8_MUL.scala 69:89]\n  wire [7:0] _io_output_T_13 = {_io_output_T_1,_io_output_T_9,_io_output_T_11[3:2]}; // @[Cat.scala 33:92]\n  wire [7:0] _GEN_1 = ovrChk_6 < 6'hf ? 8'h0 : _io_output_T_13; // @[FP8_MUL.scala 65:32 66:17 69:17]\n  wire [7:0] _GEN_2 = ovrChk_6 > 6'h2d ? _io_output_T_2 : _GEN_1; // @[FP8_MUL.scala 63:26 64:17]\n  wire [7:0] _GEN_3 = nanFlagA | nanFlagB ? 8'h7f : _GEN_2; // @[FP8_MUL.scala 57:35 58:15]\n  wire [7:0] _GEN_6 = infFlagA | infFlagB ? _GEN_0 : _GEN_3; // @[FP8_MUL.scala 50:35]\n  wire [7:0] _GEN_9 = zeroFlagA | zeroFlagB ? 8'h0 : _GEN_6; // @[FP8_MUL.scala 48:37 49:15]\n  assign io_output = zeroFlagA & zeroFlagB ? 8'h0 : _GEN_9; // @[FP8_MUL.scala 45:32 47:15]\nendmodule\n\nmodule FP8_ADD(\n  input  [7:0] io_inputA,\n  input  [7:0] io_inputB,\n  output [7:0] io_output\n);\n  wire  signA = io_inputA[7]; // @[FP8_ADD.scala 13:18]\n  wire [4:0] expA = io_inputA[6:2]; // @[FP8_ADD.scala 14:22]\n  wire [1:0] sigA = io_inputA[1:0]; // @[FP8_ADD.scala 15:25]\n  wire  signB = io_inputB[7]; // @[FP8_ADD.scala 13:18]\n  wire [4:0] expB = io_inputB[6:2]; // @[FP8_ADD.scala 14:22]\n  wire [1:0] sigB = io_inputB[1:0]; // @[FP8_ADD.scala 15:25]\n  wire  _infFlagA_T = expA == 5'h1f; // @[FP8_ADD.scala 24:23]\n  wire  _infFlagA_T_1 = sigA == 2'h0; // @[FP8_ADD.scala 24:46]\n  wire  infFlagA = expA == 5'h1f & sigA == 2'h0; // @[FP8_ADD.scala 24:38]\n  wire  _infFlagB_T = expB == 5'h1f; // @[FP8_ADD.scala 25:23]\n  wire  _infFlagB_T_1 = sigB == 2'h0; // @[FP8_ADD.scala 25:46]\n  wire  infFlagB = expB == 5'h1f & sigB == 2'h0; // @[FP8_ADD.scala 25:38]\n  wire  _zeroFlagA_T = expA == 5'h0; // @[FP8_ADD.scala 28:24]\n  wire  zeroFlagA = expA == 5'h0 & _infFlagA_T_1; // @[FP8_ADD.scala 28:39]\n  wire  _zeroFlagB_T = expB == 5'h0; // @[FP8_ADD.scala 29:24]\n  wire  zeroFlagB = expB == 5'h0 & _infFlagB_T_1; // @[FP8_ADD.scala 29:39]\n  wire  _nanFlagA_T_1 = sigA != 2'h0; // @[FP8_ADD.scala 32:46]\n  wire  nanFlagA = _infFlagA_T & sigA != 2'h0; // @[FP8_ADD.scala 32:38]\n  wire  _nanFlagB_T_1 = sigB != 2'h0; // @[FP8_ADD.scala 33:46]\n  wire  nanFlagB = _infFlagB_T & sigB != 2'h0; // @[FP8_ADD.scala 33:38]\n  wire  subFlagA = _zeroFlagA_T & _nanFlagA_T_1; // @[FP8_ADD.scala 36:38]\n  wire  subFlagB = _zeroFlagB_T & _nanFlagB_T_1; // @[FP8_ADD.scala 37:38]\n  wire [7:0] _io_output_T = zeroFlagA ? io_inputB : io_inputA; // @[FP8_ADD.scala 56:21]\n  wire  _T_4 = signA != signB; // @[FP8_ADD.scala 59:42]\n  wire [7:0] _io_output_T_1 = infFlagA ? io_inputA : io_inputB; // @[FP8_ADD.scala 62:23]\n  wire [7:0] _GEN_0 = infFlagA & infFlagB & signA != signB ? 8'h7f : _io_output_T_1; // @[FP8_ADD.scala 59:53 60:17 62:17]\n  wire  _T_8 = sigA > sigB; // @[FP8_ADD.scala 71:17]\n  wire [2:0] _ovrChk_a_n_T = {1'h0,sigA}; // @[Cat.scala 33:92]\n  wire [2:0] _ovrChk_a_n_T_1 = {1'h0,sigB}; // @[Cat.scala 33:92]\n  wire [3:0] _ovrChk_a_n_T_2 = _ovrChk_a_n_T + _ovrChk_a_n_T_1; // @[FP8_ADD.scala 72:38]\n  wire [2:0] _ovrChk_s_n_T_3 = _ovrChk_a_n_T - _ovrChk_a_n_T_1; // @[FP8_ADD.scala 73:38]\n  wire  _io_output_T_2 = ~signA; // @[FP8_ADD.scala 74:32]\n  wire  _io_output_T_3 = ~signB; // @[FP8_ADD.scala 74:62]\n  wire  _T_9 = sigB > sigA; // @[FP8_ADD.scala 75:23]\n  wire [3:0] _ovrChk_a_n_T_5 = _ovrChk_a_n_T_1 + _ovrChk_a_n_T; // @[FP8_ADD.scala 76:38]\n  wire [3:0] _GEN_1 = sigB > sigA ? _ovrChk_a_n_T_5 : _ovrChk_a_n_T_5; // @[FP8_ADD.scala 75:30 76:20 80:20]\n  wire [3:0] _GEN_4 = sigA > sigB ? _ovrChk_a_n_T_2 : _GEN_1; // @[FP8_ADD.scala 71:24 72:20]\n  wire [3:0] _GEN_21 = subFlagA & subFlagB ? _GEN_4 : 4'h0; // @[FP8_ADD.scala 49:14 68:31]\n  wire [3:0] _GEN_27 = nanFlagA | nanFlagB ? 4'h0 : _GEN_21; // @[FP8_ADD.scala 49:14 64:35]\n  wire [3:0] _GEN_32 = infFlagA | infFlagB ? 4'h0 : _GEN_27; // @[FP8_ADD.scala 49:14 57:35]\n  wire [3:0] _GEN_37 = zeroFlagA | zeroFlagB ? 4'h0 : _GEN_32; // @[FP8_ADD.scala 49:14 55:37]\n  wire [3:0] _GEN_42 = zeroFlagA & zeroFlagB ? 4'h0 : _GEN_37; // @[FP8_ADD.scala 49:14 52:32]\n  wire [2:0] ovrChk_a_n = _GEN_42[2:0]; // @[FP8_ADD.scala 47:24]\n  wire [4:0] _GEN_46 = {{4'd0}, ovrChk_a_n[2]}; // @[FP8_ADD.scala 74:80]\n  wire [4:0] _io_output_T_6 = expA + _GEN_46; // @[FP8_ADD.scala 74:80]\n  wire [6:0] _io_output_T_8 = {_io_output_T_6,ovrChk_a_n[1:0]}; // @[Cat.scala 33:92]\n  wire [2:0] _ovrChk_s_n_T_7 = _ovrChk_a_n_T_1 - _ovrChk_a_n_T; // @[FP8_ADD.scala 77:38]\n  wire [2:0] _GEN_2 = sigB > sigA ? _ovrChk_s_n_T_7 : 3'h0; // @[FP8_ADD.scala 50:14 75:30 77:20]\n  wire [2:0] _GEN_5 = sigA > sigB ? _ovrChk_s_n_T_3 : _GEN_2; // @[FP8_ADD.scala 71:24 73:20]\n  wire [2:0] _GEN_22 = subFlagA & subFlagB ? _GEN_5 : 3'h0; // @[FP8_ADD.scala 50:14 68:31]\n  wire [2:0] _GEN_28 = nanFlagA | nanFlagB ? 3'h0 : _GEN_22; // @[FP8_ADD.scala 50:14 64:35]\n  wire [2:0] _GEN_33 = infFlagA | infFlagB ? 3'h0 : _GEN_28; // @[FP8_ADD.scala 50:14 57:35]\n  wire [2:0] _GEN_38 = zeroFlagA | zeroFlagB ? 3'h0 : _GEN_33; // @[FP8_ADD.scala 50:14 55:37]\n  wire [2:0] ovrChk_s_n = zeroFlagA & zeroFlagB ? 3'h0 : _GEN_38; // @[FP8_ADD.scala 50:14 52:32]\n  wire [4:0] _GEN_47 = {{4'd0}, ovrChk_s_n[2]}; // @[FP8_ADD.scala 74:124]\n  wire [4:0] _io_output_T_11 = expA + _GEN_47; // @[FP8_ADD.scala 74:124]\n  wire [6:0] _io_output_T_13 = {_io_output_T_11,ovrChk_s_n[1:0]}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_14 = ~signB ? _io_output_T_8 : _io_output_T_13; // @[FP8_ADD.scala 74:55]\n  wire [7:0] _io_output_T_15 = {signA,_io_output_T_14}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_27 = ~signB ? _io_output_T_13 : _io_output_T_8; // @[FP8_ADD.scala 74:175]\n  wire [7:0] _io_output_T_28 = {signA,_io_output_T_27}; // @[Cat.scala 33:92]\n  wire [7:0] _io_output_T_29 = ~signA ? _io_output_T_15 : _io_output_T_28; // @[FP8_ADD.scala 74:25]\n  wire [4:0] _io_output_T_34 = expB + _GEN_46; // @[FP8_ADD.scala 78:80]\n  wire [6:0] _io_output_T_36 = {_io_output_T_34,ovrChk_a_n[1:0]}; // @[Cat.scala 33:92]\n  wire [4:0] _io_output_T_39 = expB + _GEN_47; // @[FP8_ADD.scala 78:124]\n  wire [6:0] _io_output_T_41 = {_io_output_T_39,ovrChk_s_n[1:0]}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_42 = _io_output_T_2 ? _io_output_T_36 : _io_output_T_41; // @[FP8_ADD.scala 78:55]\n  wire [7:0] _io_output_T_43 = {signB,_io_output_T_42}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_55 = _io_output_T_2 ? _io_output_T_41 : _io_output_T_36; // @[FP8_ADD.scala 78:175]\n  wire [7:0] _io_output_T_56 = {signB,_io_output_T_55}; // @[Cat.scala 33:92]\n  wire [7:0] _io_output_T_57 = _io_output_T_3 ? _io_output_T_43 : _io_output_T_56; // @[FP8_ADD.scala 78:25]\n  wire [7:0] _io_output_T_63 = {signA,_io_output_T_6,ovrChk_a_n[1:0]}; // @[Cat.scala 33:92]\n  wire [7:0] _io_output_T_64 = signB != signA ? 8'h0 : _io_output_T_63; // @[FP8_ADD.scala 82:25]\n  wire [7:0] _GEN_3 = sigB > sigA ? _io_output_T_57 : _io_output_T_64; // @[FP8_ADD.scala 75:30 78:19 82:19]\n  wire [7:0] _GEN_6 = sigA > sigB ? _io_output_T_29 : _GEN_3; // @[FP8_ADD.scala 71:24 74:19]\n  wire [2:0] _ovrChk_a_T = {1'h1,sigA}; // @[Cat.scala 33:92]\n  wire [2:0] _ovrChk_a_T_1 = {1'h1,sigB}; // @[Cat.scala 33:92]\n  wire [4:0] _ovrChk_a_T_3 = expA - expB; // @[FP8_ADD.scala 96:64]\n  wire [2:0] _ovrChk_a_T_4 = _ovrChk_a_T_1 >> _ovrChk_a_T_3; // @[FP8_ADD.scala 96:55]\n  wire [3:0] _ovrChk_a_T_5 = _ovrChk_a_T + _ovrChk_a_T_4; // @[FP8_ADD.scala 96:36]\n  wire [2:0] _ovrChk_s_T_6 = _ovrChk_a_T - _ovrChk_a_T_4; // @[FP8_ADD.scala 97:36]\n  wire [4:0] _ovrChk_a_T_9 = expB - expA; // @[FP8_ADD.scala 102:64]\n  wire [2:0] _ovrChk_a_T_10 = _ovrChk_a_T >> _ovrChk_a_T_9; // @[FP8_ADD.scala 102:55]\n  wire [3:0] _ovrChk_a_T_11 = _ovrChk_a_T_1 + _ovrChk_a_T_10; // @[FP8_ADD.scala 102:36]\n  wire [3:0] _GEN_9 = expB > expA ? _ovrChk_a_T_11 : _ovrChk_a_T_11; // @[FP8_ADD.scala 100:30 102:18 107:18]\n  wire [3:0] _GEN_12 = expA > expB ? _ovrChk_a_T_5 : _GEN_9; // @[FP8_ADD.scala 94:24 96:18]\n  wire [2:0] _ovrChk_a_T_22 = _ovrChk_a_n_T_1 >> _ovrChk_a_T_3; // @[FP8_ADD.scala 127:55]\n  wire [3:0] _ovrChk_a_T_23 = _ovrChk_a_T + _ovrChk_a_T_22; // @[FP8_ADD.scala 127:36]\n  wire [2:0] _ovrChk_a_T_28 = _ovrChk_a_n_T >> _ovrChk_a_T_9; // @[FP8_ADD.scala 131:55]\n  wire [3:0] _ovrChk_a_T_29 = _ovrChk_a_T_1 + _ovrChk_a_T_28; // @[FP8_ADD.scala 131:36]\n  wire [3:0] _GEN_15 = subFlagB ? _ovrChk_a_T_23 : _ovrChk_a_T_29; // @[FP8_ADD.scala 126:21 127:18 131:18]\n  wire [3:0] _GEN_18 = ~subFlagA & ~subFlagB ? _GEN_12 : _GEN_15; // @[FP8_ADD.scala 86:39]\n  wire [3:0] _GEN_24 = subFlagA & subFlagB ? 4'h0 : _GEN_18; // @[FP8_ADD.scala 43:12 68:31]\n  wire [3:0] _GEN_29 = nanFlagA | nanFlagB ? 4'h0 : _GEN_24; // @[FP8_ADD.scala 43:12 64:35]\n  wire [3:0] _GEN_34 = infFlagA | infFlagB ? 4'h0 : _GEN_29; // @[FP8_ADD.scala 43:12 57:35]\n  wire [3:0] _GEN_39 = zeroFlagA | zeroFlagB ? 4'h0 : _GEN_34; // @[FP8_ADD.scala 43:12 55:37]\n  wire [3:0] ovrChk_a = zeroFlagA & zeroFlagB ? 4'h0 : _GEN_39; // @[FP8_ADD.scala 43:12 52:32]\n  wire [4:0] _GEN_55 = {{4'd0}, ovrChk_a[3]}; // @[FP8_ADD.scala 98:80]\n  wire [4:0] _io_output_T_69 = expA + _GEN_55; // @[FP8_ADD.scala 98:80]\n  wire [3:0] _io_output_T_71 = ovrChk_a >> ovrChk_a[3]; // @[FP8_ADD.scala 98:105]\n  wire [6:0] _io_output_T_73 = {_io_output_T_69,_io_output_T_71[1:0]}; // @[Cat.scala 33:92]\n  wire [2:0] _ovrChk_s_T_13 = _ovrChk_a_T_1 - _ovrChk_a_T_10; // @[FP8_ADD.scala 103:36]\n  wire [2:0] _GEN_10 = expB > expA ? _ovrChk_s_T_13 : _ovrChk_s_T_13; // @[FP8_ADD.scala 100:30 103:18 108:18]\n  wire [2:0] _GEN_13 = expA > expB ? _ovrChk_s_T_6 : _GEN_10; // @[FP8_ADD.scala 94:24 97:18]\n  wire [2:0] _ovrChk_s_T_27 = _ovrChk_a_T - _ovrChk_a_T_22; // @[FP8_ADD.scala 128:36]\n  wire [2:0] _ovrChk_s_T_34 = _ovrChk_a_T_1 - _ovrChk_a_T_28; // @[FP8_ADD.scala 132:36]\n  wire [2:0] _GEN_16 = subFlagB ? _ovrChk_s_T_27 : _ovrChk_s_T_34; // @[FP8_ADD.scala 126:21 128:18 132:18]\n  wire [2:0] _GEN_19 = ~subFlagA & ~subFlagB ? _GEN_13 : _GEN_16; // @[FP8_ADD.scala 86:39]\n  wire [2:0] _GEN_25 = subFlagA & subFlagB ? 3'h0 : _GEN_19; // @[FP8_ADD.scala 44:12 68:31]\n  wire [2:0] _GEN_30 = nanFlagA | nanFlagB ? 3'h0 : _GEN_25; // @[FP8_ADD.scala 44:12 64:35]\n  wire [2:0] _GEN_35 = infFlagA | infFlagB ? 3'h0 : _GEN_30; // @[FP8_ADD.scala 44:12 57:35]\n  wire [2:0] _GEN_40 = zeroFlagA | zeroFlagB ? 3'h0 : _GEN_35; // @[FP8_ADD.scala 44:12 55:37]\n  wire [2:0] _GEN_45 = zeroFlagA & zeroFlagB ? 3'h0 : _GEN_40; // @[FP8_ADD.scala 44:12 52:32]\n  wire [3:0] ovrChk_s = {{1'd0}, _GEN_45}; // @[FP8_ADD.scala 41:22]\n  wire [4:0] _GEN_56 = {{4'd0}, ovrChk_s[3]}; // @[FP8_ADD.scala 98:137]\n  wire [4:0] _io_output_T_76 = expA + _GEN_56; // @[FP8_ADD.scala 98:137]\n  wire [3:0] _io_output_T_78 = ovrChk_s >> ovrChk_s[3]; // @[FP8_ADD.scala 98:162]\n  wire [6:0] _io_output_T_80 = {_io_output_T_76,_io_output_T_78[1:0]}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_81 = _io_output_T_3 ? _io_output_T_73 : _io_output_T_80; // @[FP8_ADD.scala 98:55]\n  wire [7:0] _io_output_T_82 = {signA,_io_output_T_81}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_98 = _io_output_T_3 ? _io_output_T_80 : _io_output_T_73; // @[FP8_ADD.scala 98:201]\n  wire [7:0] _io_output_T_99 = {signA,_io_output_T_98}; // @[Cat.scala 33:92]\n  wire [7:0] _io_output_T_100 = _io_output_T_2 ? _io_output_T_82 : _io_output_T_99; // @[FP8_ADD.scala 98:25]\n  wire [4:0] _io_output_T_105 = expB + _GEN_55; // @[FP8_ADD.scala 104:80]\n  wire [6:0] _io_output_T_109 = {_io_output_T_105,_io_output_T_71[1:0]}; // @[Cat.scala 33:92]\n  wire [4:0] _io_output_T_112 = expB + _GEN_56; // @[FP8_ADD.scala 104:137]\n  wire [6:0] _io_output_T_116 = {_io_output_T_112,_io_output_T_78[1:0]}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_117 = _io_output_T_2 ? _io_output_T_109 : _io_output_T_116; // @[FP8_ADD.scala 104:55]\n  wire [7:0] _io_output_T_118 = {signB,_io_output_T_117}; // @[Cat.scala 33:92]\n  wire [6:0] _io_output_T_134 = _io_output_T_2 ? _io_output_T_116 : _io_output_T_109; // @[FP8_ADD.scala 104:201]\n  wire [7:0] _io_output_T_135 = {signB,_io_output_T_134}; // @[Cat.scala 33:92]\n  wire [7:0] _io_output_T_136 = _io_output_T_3 ? _io_output_T_118 : _io_output_T_135; // @[FP8_ADD.scala 104:25]\n  wire [7:0] _io_output_T_216 = {signA,_io_output_T_69,_io_output_T_71[1:0]}; // @[Cat.scala 33:92]\n  wire [7:0] _io_output_T_217 = _T_4 ? 8'h0 : _io_output_T_216; // @[FP8_ADD.scala 117:27]\n  wire [7:0] _GEN_7 = _T_9 ? _io_output_T_136 : _io_output_T_217; // @[FP8_ADD.scala 113:32 114:21 117:21]\n  wire [7:0] _GEN_8 = _T_8 ? _io_output_T_100 : _GEN_7; // @[FP8_ADD.scala 110:26 111:21]\n  wire [7:0] _GEN_11 = expB > expA ? _io_output_T_136 : _GEN_8; // @[FP8_ADD.scala 100:30 104:19]\n  wire [7:0] _GEN_14 = expA > expB ? _io_output_T_100 : _GEN_11; // @[FP8_ADD.scala 94:24 98:19]\n  wire [7:0] _GEN_17 = subFlagB ? _io_output_T_100 : _io_output_T_136; // @[FP8_ADD.scala 126:21 129:19 133:19]\n  wire [7:0] _GEN_20 = ~subFlagA & ~subFlagB ? _GEN_14 : _GEN_17; // @[FP8_ADD.scala 86:39]\n  wire [7:0] _GEN_23 = subFlagA & subFlagB ? _GEN_6 : _GEN_20; // @[FP8_ADD.scala 68:31]\n  wire [7:0] _GEN_26 = nanFlagA | nanFlagB ? 8'h7f : _GEN_23; // @[FP8_ADD.scala 64:35 65:15]\n  wire [7:0] _GEN_31 = infFlagA | infFlagB ? _GEN_0 : _GEN_26; // @[FP8_ADD.scala 57:35]\n  wire [7:0] _GEN_36 = zeroFlagA | zeroFlagB ? _io_output_T : _GEN_31; // @[FP8_ADD.scala 55:37 56:15]\n  assign io_output = zeroFlagA & zeroFlagB ? 8'h0 : _GEN_36; // @[FP8_ADD.scala 52:32 54:15]\nendmodule\n\n\nmodule tt_um_fp_mac(\n  input        clk,   \t// clock\n  input        rst_n, \t// reset_n - low to reset\n  input  [7:0] ui_in, \t// io_wgt\n  input  [7:0] uio_in, \t// io_ifm\n  output [7:0] uo_out,\n  output [7:0] uio_out,\n  output [7:0] uio_oe, \t// IOs: Enable path (active high: 0=input, 1=output)\n  input        ena     // always 1 when the design is powered, so you can ignore it\n  //output       io_valid\n);\n`ifdef RANDOMIZE_REG_INIT\n  reg [31:0] _RAND_0;\n  reg [31:0] _RAND_1;\n`endif // RANDOMIZE_REG_INIT\n  wire [7:0] multiplier_io_inputA; // @[MAC_TOP.scala 13:26]\n  wire [7:0] multiplier_io_inputB; // @[MAC_TOP.scala 13:26]\n  wire [7:0] multiplier_io_output; // @[MAC_TOP.scala 13:26]\n  wire [7:0] adder_io_inputA; // @[MAC_TOP.scala 14:21]\n  wire [7:0] adder_io_inputB; // @[MAC_TOP.scala 14:21]\n  wire [7:0] adder_io_output; // @[MAC_TOP.scala 14:21]\n  reg [7:0] resBuff; // @[MAC_TOP.scala 56:24]\n  reg [1:0] count; // @[MAC_TOP.scala 57:22]\n  wire  _nextval_T = count < 2'h3; // @[MAC_TOP.scala 58:27]\n  wire [1:0] _count_T_2 = count + 2'h1; // @[MAC_TOP.scala 64:42]\n  FP8_MUL multiplier ( // @[MAC_TOP.scala 13:26]\n    .io_inputA(multiplier_io_inputA),\n    .io_inputB(multiplier_io_inputB),\n    .io_output(multiplier_io_output)\n  );\n  FP8_ADD adder ( // @[MAC_TOP.scala 14:21]\n    .io_inputA(adder_io_inputA),\n    .io_inputB(adder_io_inputB),\n    .io_output(adder_io_output)\n  );\n\n  assign uio_out = 0;\n  assign uio_oe  = 0;\n\n  assign uo_out = resBuff; // @[MAC_TOP.scala 66:13]\n  //assign io_valid = count == 2'h3; // @[MAC_TOP.scala 65:21]\n  assign multiplier_io_inputA = ui_in; // @[MAC_TOP.scala 51:26]\n  assign multiplier_io_inputB = uio_in; // @[MAC_TOP.scala 52:26]\n  assign adder_io_inputA = multiplier_io_output; // @[MAC_TOP.scala 61:19]\n  assign adder_io_inputB = resBuff; // @[MAC_TOP.scala 62:19]\n  always @(posedge clk) begin\n    if (!rst_n) begin // @[MAC_TOP.scala 56:24]\n      resBuff <= 8'h0; // @[MAC_TOP.scala 56:24]\n    end else if (_nextval_T) begin // @[MAC_TOP.scala 59:17]\n      if (count < 2'h3) begin // @[MAC_TOP.scala 58:20]\n        resBuff <= adder_io_output;\n      end else begin\n        resBuff <= 8'h0;\n      end\n    end else begin\n      resBuff <= 8'h0;\n    end\n    if (!rst_n) begin // @[MAC_TOP.scala 57:22]\n      count <= 2'h0; // @[MAC_TOP.scala 57:22]\n    end else if (count == 2'h3) begin // @[MAC_TOP.scala 64:15]\n      count <= 2'h0;\n    end else if (count < 2'h3) begin\n      count <= _count_T_2;\n    end else begin\n      count <= 2'h0;\n    end\n  end\n// Register and memory initialization\n`ifdef RANDOMIZE_GARBAGE_ASSIGN\n`define RANDOMIZE\n`endif\n`ifdef RANDOMIZE_INVALID_ASSIGN\n`define RANDOMIZE\n`endif\n`ifdef RANDOMIZE_REG_INIT\n`define RANDOMIZE\n`endif\n`ifdef RANDOMIZE_MEM_INIT\n`define RANDOMIZE\n`endif\n`ifndef RANDOM\n`define RANDOM $random\n`endif\n`ifdef RANDOMIZE_MEM_INIT\n  integer initvar;\n`endif\n`ifndef SYNTHESIS\n`ifdef FIRRTL_BEFORE_INITIAL\n`FIRRTL_BEFORE_INITIAL\n`endif\ninitial begin\n  `ifdef RANDOMIZE\n    `ifdef INIT_RANDOM\n      `INIT_RANDOM\n    `endif\n    `ifndef VERILATOR\n      `ifdef RANDOMIZE_DELAY\n        #`RANDOMIZE_DELAY begin end\n      `else\n        #0.002 begin end\n      `endif\n    `endif\n`ifdef RANDOMIZE_REG_INIT\n  _RAND_0 = {1{`RANDOM}};\n  resBuff = _RAND_0[7:0];\n  _RAND_1 = {1{`RANDOM}};\n  count = _RAND_1[1:0];\n  // _RAND_0 = 8'h0;\n  // resBuff = _RAND_0[7:0];\n  // _RAND_1 = 8'h0;\n  // count = _RAND_1[1:0];\n`endif // RANDOMIZE_REG_INIT\n  `endif // RANDOMIZE\nend // initial\n`ifdef FIRRTL_AFTER_INITIAL\n`FIRRTL_AFTER_INITIAL\n`endif\n`endif // SYNTHESIS\nendmodule\n", "mask_idx": {"conditional_statement": [[18962, 19145], [18502, 18853], [18662, 18803]], "module_program_interface_instantiation": [[17726, 17890], [17893, 18037]], "always_construct": [[18470, 19151]], "ansi_port_declaration": [[4160, 4183], [16867, 16941], [16704, 16750]], "continuous_assign": [[18333, 18405], [16546, 16636], [4015, 4104]], "nonblocking_assignment": [[18908, 18948], [18720, 18747], [19077, 19097]]}, "all_mask_idx": {"module_program_interface_instantiation": [[17726, 17890], [17893, 18037]], "continuous_assign": [[4015, 4104], [16546, 16636], [18041, 18060], [18063, 18082], [18086, 18136], [18202, 18264], [18267, 18330], [18333, 18405], [18408, 18467]], "blocking_assignment": [], "nonblocking_assignment": [[18552, 18594], [18720, 18747], [18777, 18793], [18829, 18845], [18908, 18948], [19019, 19033], [19077, 19097], [19123, 19137]], "case_statement": [], "conditional_statement": [[18502, 18853], [18608, 18853], [18662, 18803], [18858, 19145], [18962, 19145], [19047, 19145]], "always_construct": [[18470, 19151]], "parameter_declaration": [], "ansi_port_declaration": [[41, 64], [67, 90], [93, 115], [4134, 4157], [4160, 4183], [4186, 4208], [16672, 16701], [16704, 16750], [16753, 16783], [16786, 16817], [16820, 16840], [16843, 16864], [16867, 16941], [16944, 17025]]}}