{"sample_i": "p1", "topmodule": "cve2_alu", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Arithmetic logic unit\n */\nmodule cve2_alu #(\n  parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone\n) (\n  input  cve2_pkg::alu_op_e operator_i,\n  input  logic [31:0]       operand_a_i,\n  input  logic [31:0]       operand_b_i,\n  input  logic              instr_first_cycle_i,\n  input  logic [32:0]       multdiv_operand_a_i,\n  input  logic [32:0]       multdiv_operand_b_i,\n  input  logic              multdiv_sel_i,\n  input  logic [31:0]       imd_val_q_i[2],\n  output logic [31:0]       imd_val_d_o[2],\n  output logic [1:0]        imd_val_we_o,\n  output logic [31:0]       adder_result_o,\n  output logic [33:0]       adder_result_ext_o,\n  output logic [31:0]       result_o,\n  output logic              comparison_result_o,\n  output logic              is_equal_result_o\n);\n  import cve2_pkg::*;\n  logic [31:0] operand_a_rev;\n  logic [32:0] operand_b_neg;\n  // bit reverse operand_a for left shifts and bit counting\n  for (genvar k = 0; k < 32; k++) begin : gen_rev_operand_a\n    assign operand_a_rev[k] = operand_a_i[31-k];\n  end\n  ///////////\n  // Adder //\n  ///////////\n  logic        adder_op_a_shift1;\n  logic        adder_op_a_shift2;\n  logic        adder_op_a_shift3;\n  logic        adder_op_b_negate;\n  logic [32:0] adder_in_a, adder_in_b;\n  logic [31:0] adder_result;\n  always_comb begin\n    adder_op_a_shift1 = 1'b0;\n    adder_op_a_shift2 = 1'b0;\n    adder_op_a_shift3 = 1'b0;\n    adder_op_b_negate = 1'b0;\n    unique case (operator_i)\n      // Adder OPs\n      ALU_SUB,\n      // Comparator OPs\n      ALU_EQ,   ALU_NE,\n      ALU_GE,   ALU_GEU,\n      ALU_LT,   ALU_LTU,\n      ALU_SLT,  ALU_SLTU,\n      // MinMax OPs (RV32B Ops)\n      ALU_MIN,  ALU_MINU,\n      ALU_MAX,  ALU_MAXU: adder_op_b_negate = 1'b1;\n      // Address Calculation OPs (RV32B Ops)\n      ALU_SH1ADD: if (RV32B != RV32BNone) adder_op_a_shift1 = 1'b1;\n      ALU_SH2ADD: if (RV32B != RV32BNone) adder_op_a_shift2 = 1'b1;\n      ALU_SH3ADD: if (RV32B != RV32BNone) adder_op_a_shift3 = 1'b1;\n      default:;\n    endcase\n  end\n  // prepare operand a\n  always_comb begin\n    unique case(1'b1)\n      multdiv_sel_i:     adder_in_a = multdiv_operand_a_i;\n      adder_op_a_shift1: adder_in_a = {operand_a_i[30:0],2'b01};\n      adder_op_a_shift2: adder_in_a = {operand_a_i[29:0],3'b001};\n      adder_op_a_shift3: adder_in_a = {operand_a_i[28:0],4'b0001};\n      default:           adder_in_a = {operand_a_i,1'b1};\n    endcase\n  end\n  // prepare operand b\n  assign operand_b_neg = {operand_b_i,1'b0} ^ {33{1'b1}};\n  always_comb begin\n    unique case (1'b1)\n      multdiv_sel_i:     adder_in_b = multdiv_operand_b_i;\n      adder_op_b_negate: adder_in_b = operand_b_neg;\n      default:           adder_in_b = {operand_b_i, 1'b0};\n    endcase\n  end\n  // actual adder\n  assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);\n  assign adder_result       = adder_result_ext_o[32:1];\n  assign adder_result_o     = adder_result;\n  ////////////////\n  // Comparison //\n  ////////////////\n  logic is_equal;\n  logic is_greater_equal;  // handles both signed and unsigned forms\n  logic cmp_signed;\n  always_comb begin\n    unique case (operator_i)\n      ALU_GE,\n      ALU_LT,\n      ALU_SLT,\n      // RV32B only\n      ALU_MIN,\n      ALU_MAX: cmp_signed = 1'b1;\n      default: cmp_signed = 1'b0;\n    endcase\n  end\n  assign is_equal = (adder_result == 32'b0);\n  assign is_equal_result_o = is_equal;\n  // Is greater equal\n  always_comb begin\n    if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0) begin\n      is_greater_equal = (adder_result[31] == 1'b0);\n    end else begin\n      is_greater_equal = operand_a_i[31] ^ (cmp_signed);\n    end\n  end\n  // GTE unsigned:\n  // (a[31] == 1 && b[31] == 1) => adder_result[31] == 0\n  // (a[31] == 0 && b[31] == 0) => adder_result[31] == 0\n  // (a[31] == 1 && b[31] == 0) => 1\n  // (a[31] == 0 && b[31] == 1) => 0\n  // GTE signed:\n  // (a[31] == 1 && b[31] == 1) => adder_result[31] == 0\n  // (a[31] == 0 && b[31] == 0) => adder_result[31] == 0\n  // (a[31] == 1 && b[31] == 0) => 0\n  // (a[31] == 0 && b[31] == 1) => 1\n  // generate comparison result\n  logic cmp_result;\n  always_comb begin\n    unique case (operator_i)\n      ALU_EQ:             cmp_result =  is_equal;\n      ALU_NE:             cmp_result = ~is_equal;\n      ALU_GE,   ALU_GEU,\n      ALU_MAX,  ALU_MAXU: cmp_result = is_greater_equal; // RV32B only\n      ALU_LT,   ALU_LTU,\n      ALU_MIN,  ALU_MINU, //RV32B only\n      ALU_SLT,  ALU_SLTU: cmp_result = ~is_greater_equal;\n      default: cmp_result = is_equal;\n    endcase\n  end\n  assign comparison_result_o = cmp_result;\n  ///////////\n  // Shift //\n  ///////////\n  // The shifter structure consists of a 33-bit shifter: 32-bit operand + 1 bit extension for\n  // arithmetic shifts and one-shift support.\n  // Rotations and funnel shifts are implemented as multi-cycle instructions.\n  // The shifter is also used for single-bit instructions and bit-field place as detailed below.\n  //\n  // Standard Shifts\n  // ===============\n  // For standard shift instructions, the direction of the shift is to the right by default. For\n  // left shifts, the signal shift_left signal is set. If so, the operand is initially reversed,\n  // shifted to the right by the specified amount and shifted back again. For arithmetic- and\n  // one-shifts the 33rd bit of the shifter operand can is set accordingly.\n  //\n  // Multicycle Shifts\n  // =================\n  //\n  // Rotation\n  // --------\n  // For rotations, the operand signals operand_a_i and operand_b_i are kept constant to rs1 and\n  // rs2 respectively.\n  //\n  // Rotation pseudocode:\n  //   shift_amt = rs2 & 31;\n  //   multicycle_result = (rs1 >> shift_amt) | (rs1 << (32 - shift_amt));\n  //                       ^-- cycle 0 -----^ ^-- cycle 1 --------------^\n  //\n  // Funnel Shifts\n  // -------------\n  // For funnel shifs, operand_a_i is tied to rs1 in the first cycle and rs3 in the\n  // second cycle. operand_b_i is always tied to rs2. The order of applying the shift amount or\n  // its complement is determined by bit [5] of shift_amt.\n  //\n  // Funnel shift Pseudocode: (fsl)\n  //  shift_amt = rs2 & 63;\n  //  shift_amt_compl = 32 - shift_amt[4:0]\n  //  if (shift_amt >=33):\n  //     multicycle_result = (rs1 >> shift_amt_compl[4:0]) | (rs3 << shift_amt[4:0]);\n  //                         ^-- cycle 0 ----------------^ ^-- cycle 1 ------------^\n  //  else if (shift_amt <= 31 && shift_amt > 0):\n  //     multicycle_result = (rs1 << shift_amt[4:0]) | (rs3 >> shift_amt_compl[4:0]);\n  //                         ^-- cycle 0 ----------^ ^-- cycle 1 -------------------^\n  //  For shift_amt == 0, 32, both shift_amt[4:0] and shift_amt_compl[4:0] == '0.\n  //  these cases need to be handled separately outside the shifting structure:\n  //  else if (shift_amt == 32):\n  //     multicycle_result = rs3\n  //  else if (shift_amt == 0):\n  //     multicycle_result = rs1.\n  //\n  // Single-Bit Instructions\n  // =======================\n  // Single bit instructions operate on bit operand_b_i[4:0] of operand_a_i.\n  // The operations bset, bclr and binv are implemented by generation of a bit-mask using the\n  // shifter structure. This is done by left-shifting the operand 32'h1 by the required amount.\n  // The signal shift_sbmode multiplexes the shifter input and sets the signal shift_left.\n  // Further processing is taken care of by a separate structure.\n  //\n  // For bext, the bit defined by operand_b_i[4:0] is to be returned. This is done by simply\n  // shifting operand_a_i to the right by the required amount and returning bit [0] of the result.\n  //\n  // Bit-Field Place\n  // ===============\n  // The shifter structure is shared to compute bfp_mask << bfp_off.\n  logic       shift_left;\n  logic       shift_ones;\n  logic       shift_arith;\n  logic       shift_funnel;\n  logic       shift_sbmode;\n  logic [5:0] shift_amt;\n  logic [5:0] shift_amt_compl; // complementary shift amount (32 - shift_amt)\n  logic        [31:0] shift_operand;\n  logic signed [32:0] shift_result_ext_signed;\n  logic        [32:0] shift_result_ext;\n  logic               unused_shift_result_ext;\n  logic        [31:0] shift_result;\n  logic        [31:0] shift_result_rev;\n  // zbf\n  logic bfp_op;\n  logic [4:0]  bfp_len;\n  logic [4:0]  bfp_off;\n  logic [31:0] bfp_mask;\n  logic [31:0] bfp_mask_rev;\n  logic [31:0] bfp_result;\n  // bfp: shares the shifter structure to compute bfp_mask << bfp_off\n  assign bfp_op = (RV32B != RV32BNone) ? (operator_i == ALU_BFP) : 1'b0;\n  assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]}; // len = 0 encodes for len = 16\n  assign bfp_off = operand_b_i[20:16];\n  assign bfp_mask = (RV32B != RV32BNone) ? ~(32'hffff_ffff << bfp_len) : '0;\n  for (genvar i = 0; i < 32; i++) begin : gen_rev_bfp_mask\n    assign bfp_mask_rev[i] = bfp_mask[31-i];\n  end\n  assign bfp_result =(RV32B != RV32BNone) ?\n      (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : '0;\n  // bit shift_amt[5]: word swap bit: only considered for FSL/FSR.\n  // if set, reverse operations in first and second cycle.\n  assign shift_amt[5] = operand_b_i[5] & shift_funnel;\n  assign shift_amt_compl = 32 - operand_b_i[4:0];\n  always_comb begin\n    if (bfp_op) begin\n      shift_amt[4:0] = bfp_off;  // length field of bfp control word\n    end else begin\n      shift_amt[4:0] = instr_first_cycle_i ?\n          (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) :\n          (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0]);\n    end\n  end\n  // single-bit mode: shift\n  assign shift_sbmode = (RV32B != RV32BNone) ?\n      (operator_i == ALU_BSET) | (operator_i == ALU_BCLR) | (operator_i == ALU_BINV) : 1'b0;\n  // left shift if this is:\n  // * a standard left shift (slo, sll)\n  // * a rol in the first cycle\n  // * a ror in the second cycle\n  // * fsl: without word-swap bit: first cycle, else: second cycle\n  // * fsr: without word-swap bit: second cycle, else: first cycle\n  // * a single-bit instruction: bclr, bset, binv (excluding bext)\n  // * bfp: bfp_mask << bfp_off\n  always_comb begin\n    unique case (operator_i)\n      ALU_SLL: shift_left = 1'b1;\n      ALU_SLO: shift_left = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b1 : 1'b0;\n      ALU_BFP: shift_left = (RV32B != RV32BNone) ? 1'b1 : 1'b0;\n      ALU_ROL: shift_left = (RV32B != RV32BNone) ? instr_first_cycle_i : 0;\n      ALU_ROR: shift_left = (RV32B != RV32BNone) ? ~instr_first_cycle_i : 0;\n      ALU_FSL: shift_left = (RV32B != RV32BNone) ?\n        (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0;\n      ALU_FSR: shift_left = (RV32B != RV32BNone) ?\n          (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0;\n      default: shift_left = 1'b0;\n    endcase\n    if (shift_sbmode) begin\n      shift_left = 1'b1;\n    end\n  end\n  assign shift_arith  = (operator_i == ALU_SRA);\n  assign shift_ones   = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ?\n      (operator_i == ALU_SLO) | (operator_i == ALU_SRO) : 1'b0;\n  assign shift_funnel = (RV32B != RV32BNone) ?\n      (operator_i == ALU_FSL) | (operator_i == ALU_FSR) : 1'b0;\n  // shifter structure.\n  always_comb begin\n    // select shifter input\n    // for bfp, sbmode and shift_left the corresponding bit-reversed input is chosen.\n    if (RV32B == RV32BNone) begin\n      shift_operand = shift_left ? operand_a_rev : operand_a_i;\n    end else begin\n      unique case (1'b1)\n        bfp_op:       shift_operand = bfp_mask_rev;\n        shift_sbmode: shift_operand = 32'h8000_0000;\n        default:      shift_operand = shift_left ? operand_a_rev : operand_a_i;\n      endcase\n    end\n    shift_result_ext_signed =\n        $signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> shift_amt[4:0];\n    shift_result_ext = $unsigned(shift_result_ext_signed);\n    shift_result            = shift_result_ext[31:0];\n    unused_shift_result_ext = shift_result_ext[32];\n    for (int unsigned i = 0; i < 32; i++) begin\n      shift_result_rev[i] = shift_result[31-i];\n    end\n    shift_result = shift_left ? shift_result_rev : shift_result;\n  end\n  ///////////////////\n  // Bitwise Logic //\n  ///////////////////\n  logic bwlogic_or;\n  logic bwlogic_and;\n  logic [31:0] bwlogic_operand_b;\n  logic [31:0] bwlogic_or_result;\n  logic [31:0] bwlogic_and_result;\n  logic [31:0] bwlogic_xor_result;\n  logic [31:0] bwlogic_result;\n  logic bwlogic_op_b_negate;\n  always_comb begin\n    unique case (operator_i)\n      // Logic-with-negate OPs (RV32B Ops)\n      ALU_XNOR,\n      ALU_ORN,\n      ALU_ANDN: bwlogic_op_b_negate = (RV32B != RV32BNone) ? 1'b1 : 1'b0;\n      ALU_CMIX: bwlogic_op_b_negate = (RV32B != RV32BNone) ? ~instr_first_cycle_i : 1'b0;\n      default:  bwlogic_op_b_negate = 1'b0;\n    endcase\n  end\n  assign bwlogic_operand_b = bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i;\n  assign bwlogic_or_result  = operand_a_i | bwlogic_operand_b;\n  assign bwlogic_and_result = operand_a_i & bwlogic_operand_b;\n  assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b;\n  assign bwlogic_or  = (operator_i == ALU_OR)  | (operator_i == ALU_ORN);\n  assign bwlogic_and = (operator_i == ALU_AND) | (operator_i == ALU_ANDN);\n  always_comb begin\n    unique case (1'b1)\n      bwlogic_or:  bwlogic_result = bwlogic_or_result;\n      bwlogic_and: bwlogic_result = bwlogic_and_result;\n      default:     bwlogic_result = bwlogic_xor_result;\n    endcase\n  end\n  logic [5:0]  bitcnt_result;\n  logic [31:0] minmax_result;\n  logic [31:0] pack_result;\n  logic [31:0] sext_result;\n  logic [31:0] singlebit_result;\n  logic [31:0] rev_result;\n  logic [31:0] shuffle_result;\n  logic [31:0] xperm_result;\n  logic [31:0] butterfly_result;\n  logic [31:0] invbutterfly_result;\n  logic [31:0] clmul_result;\n  logic [31:0] multicycle_result;\n  if (RV32B != RV32BNone) begin : g_alu_rvb\n    /////////////////\n    // Bitcounting //\n    /////////////////\n    // The bit-counter structure computes the number of set bits in its operand. Partial results\n    // (from left to right) are needed to compute the control masks for computation of\n    // bcompress/bdecompress by the butterfly network, if implemented.\n    // For cpop, clz and ctz, only the end result is used.\n    logic        zbe_op;\n    logic        bitcnt_ctz;\n    logic        bitcnt_clz;\n    logic        bitcnt_cz;\n    logic [31:0] bitcnt_bits;\n    logic [31:0] bitcnt_mask_op;\n    logic [31:0] bitcnt_bit_mask;\n    logic [ 5:0] bitcnt_partial [32];\n    logic [31:0] bitcnt_partial_lsb_d;\n    logic [31:0] bitcnt_partial_msb_d;\n    assign bitcnt_ctz    = operator_i == ALU_CTZ;\n    assign bitcnt_clz    = operator_i == ALU_CLZ;\n    assign bitcnt_cz     = bitcnt_ctz | bitcnt_clz;\n    assign bitcnt_result = bitcnt_partial[31];\n    // Bit-mask generation for clz and ctz:\n    // The bit mask is generated by spreading the lowest-order set bit in the operand to all\n    // higher order bits. The resulting mask is inverted to cover the lowest order zeros. In order\n    // to create the bit mask for leading zeros, the input operand needs to be reversed.\n    assign bitcnt_mask_op = bitcnt_clz ? operand_a_rev : operand_a_i;\n    always_comb begin\n      bitcnt_bit_mask = bitcnt_mask_op;\n      bitcnt_bit_mask |= bitcnt_bit_mask << 1;\n      bitcnt_bit_mask |= bitcnt_bit_mask << 2;\n      bitcnt_bit_mask |= bitcnt_bit_mask << 4;\n      bitcnt_bit_mask |= bitcnt_bit_mask << 8;\n      bitcnt_bit_mask |= bitcnt_bit_mask << 16;\n      bitcnt_bit_mask = ~bitcnt_bit_mask;\n    end\n    assign zbe_op = (operator_i == ALU_BCOMPRESS) | (operator_i == ALU_BDECOMPRESS);\n    always_comb begin\n      case (1'b1)\n        zbe_op:      bitcnt_bits = operand_b_i;\n        bitcnt_cz:   bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; // clz / ctz\n        default:     bitcnt_bits = operand_a_i; // cpop\n      endcase\n    end\n    // The parallel prefix counter is of the structure of a Brent-Kung Adder. In the first\n    // log2(width) stages, the sum of the n preceding bit lines is computed for the bit lines at\n    // positions 2**n-1 (power-of-two positions) where n denotes the current stage.\n    // In stage n=log2(width), the count for position width-1 (the MSB) is finished.\n    // For the intermediate values, an inverse adder tree then computes the bit counts for the bit\n    // lines at positions\n    // m = 2**(n-1) + i*2**(n-2), where i = [1 ... width / 2**(n-1)-1] and n = [log2(width) ... 2].\n    // Thus, at every subsequent stage the result of two previously unconnected sub-trees is\n    // summed, starting at the node summing bits [width/2-1 : 0] and [3*width/4-1: width/2]\n    // and moving to iteratively sum up all the sub-trees.\n    // The inverse adder tree thus features log2(width) - 1 stages the first of these stages is a\n    // single addition at position 3*width/4 - 1. It does not interfere with the last\n    // stage of the primary adder tree. These stages can thus be folded together, resulting in a\n    // total of 2*log2(width)-2 stages.\n    // For more details refer to R. Brent, H. T. Kung, \"A Regular Layout for Parallel Adders\",\n    // (1982).\n    // For a bitline at position p, only bits\n    // bitcnt_partial[max(i, such that p % log2(i) == 0)-1 : 0] are needed for generation of the\n    // butterfly network control signals. The adders in the intermediate value adder tree thus need\n    // not be full 5-bit adders. We leave the optimization to the synthesis tools.\n    //\n    // Consider the following 8-bit example for illustraton.\n    //\n    // let bitcnt_bits = 8'babcdefgh.\n    //\n    //                   a  b  c  d  e  f  g  h\n    //                   | /:  | /:  | /:  | /:\n    //                   |/ :  |/ :  |/ :  |/ :\n    // stage 1:          +  :  +  :  +  :  +  :\n    //                   |  : /:  :  |  : /:  :\n    //                   |,--+ :  :  |,--+ :  :\n    // stage 2:          +  :  :  :  +  :  :  :\n    //                   |  :  |  : /:  :  :  :\n    //                   |,-----,--+ :  :  :  : ^-primary adder tree\n    // stage 3:          +  :  +  :  :  :  :  : -------------------------\n    //                   :  | /| /| /| /| /|  : ,-intermediate adder tree\n    //                   :  |/ |/ |/ |/ |/ :  :\n    // stage 4           :  +  +  +  +  +  :  :\n    //                   :  :  :  :  :  :  :  :\n    // bitcnt_partial[i] 7  6  5  4  3  2  1  0\n    always_comb begin\n      bitcnt_partial = '{default: '0};\n      // stage 1\n      for (int unsigned i = 1; i < 32; i += 2) begin\n        bitcnt_partial[i] = {5'h0, bitcnt_bits[i]} + {5'h0, bitcnt_bits[i-1]};\n      end\n      // stage 2\n      for (int unsigned i = 3; i < 32; i += 4) begin\n        bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i];\n      end\n      // stage 3\n      for (int unsigned i = 7; i < 32; i += 8) begin\n        bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i];\n      end\n      // stage 4\n      for (int unsigned i = 15; i < 32; i += 16) begin\n        bitcnt_partial[i] = bitcnt_partial[i-8] + bitcnt_partial[i];\n      end\n      // stage 5\n      bitcnt_partial[31] = bitcnt_partial[15] + bitcnt_partial[31];\n      // ^- primary adder tree\n      // -------------------------------\n      // ,-intermediate value adder tree\n      bitcnt_partial[23] = bitcnt_partial[15] + bitcnt_partial[23];\n      // stage 6\n      for (int unsigned i = 11; i < 32; i += 8) begin\n        bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i];\n      end\n      // stage 7\n      for (int unsigned i = 5; i < 32; i += 4) begin\n        bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i];\n      end\n      // stage 8\n      bitcnt_partial[0] = {5'h0, bitcnt_bits[0]};\n      for (int unsigned i = 2; i < 32; i += 2) begin\n        bitcnt_partial[i] = bitcnt_partial[i-1] + {5'h0, bitcnt_bits[i]};\n      end\n    end\n    ///////////////\n    // Min / Max //\n    ///////////////\n    assign minmax_result = cmp_result ? operand_a_i : operand_b_i;\n    //////////\n    // Pack //\n    //////////\n    logic packu;\n    logic packh;\n    assign packu = operator_i == ALU_PACKU;\n    assign packh = operator_i == ALU_PACKH;\n    always_comb begin\n      unique case (1'b1)\n        packu:   pack_result = {operand_b_i[31:16], operand_a_i[31:16]};\n        packh:   pack_result = {16'h0, operand_b_i[7:0], operand_a_i[7:0]};\n        default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]};\n      endcase\n    end\n    //////////\n    // Sext //\n    //////////\n    assign sext_result = (operator_i == ALU_SEXTB) ?\n        { {24{operand_a_i[7]}}, operand_a_i[7:0]} : { {16{operand_a_i[15]}}, operand_a_i[15:0]};\n    /////////////////////////////\n    // Single-bit Instructions //\n    /////////////////////////////\n    always_comb begin\n      unique case (operator_i)\n        ALU_BSET: singlebit_result = operand_a_i | shift_result;\n        ALU_BCLR: singlebit_result = operand_a_i & ~shift_result;\n        ALU_BINV: singlebit_result = operand_a_i ^ shift_result;\n        default:  singlebit_result = {31'h0, shift_result[0]}; // ALU_BEXT\n      endcase\n    end\n    ////////////////////////////////////\n    // General Reverse and Or-combine //\n    ////////////////////////////////////\n    // Only a subset of the general reverse and or-combine instructions are implemented in the\n    // balanced version of the B extension. Currently rev8 (shift_amt = 5'b11000) and orc.b\n    // (shift_amt = 5'b00111) are supported in the base extension.\n    logic [4:0] zbp_shift_amt;\n    logic gorc_op;\n    assign gorc_op = (operator_i == ALU_GORC);\n    assign zbp_shift_amt[2:0] =\n        (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? shift_amt[2:0] : {3{shift_amt[0]}};\n    assign zbp_shift_amt[4:3] =\n        (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? shift_amt[4:3] : {2{shift_amt[3]}};\n    always_comb begin\n      rev_result = operand_a_i;\n      if (zbp_shift_amt[0]) begin\n        rev_result = (gorc_op ? rev_result : 32'h0)       |\n                     ((rev_result & 32'h5555_5555) <<  1) |\n                     ((rev_result & 32'haaaa_aaaa) >>  1);\n      end\n      if (zbp_shift_amt[1]) begin\n        rev_result = (gorc_op ? rev_result : 32'h0)       |\n                     ((rev_result & 32'h3333_3333) <<  2) |\n                     ((rev_result & 32'hcccc_cccc) >>  2);\n      end\n      if (zbp_shift_amt[2]) begin\n        rev_result = (gorc_op ? rev_result : 32'h0)       |\n                     ((rev_result & 32'h0f0f_0f0f) <<  4) |\n                     ((rev_result & 32'hf0f0_f0f0) >>  4);\n      end\n      if (zbp_shift_amt[3]) begin\n        rev_result = ((RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) &&\n                      gorc_op ? rev_result : 32'h0) |\n                     ((rev_result & 32'h00ff_00ff) <<  8) |\n                     ((rev_result & 32'hff00_ff00) >>  8);\n      end\n      if (zbp_shift_amt[4]) begin\n        rev_result = ((RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) &&\n                      gorc_op ? rev_result : 32'h0) |\n                     ((rev_result & 32'h0000_ffff) << 16) |\n                     ((rev_result & 32'hffff_0000) >> 16);\n      end\n    end\n    logic crc_hmode;\n    logic crc_bmode;\n    logic [31:0] clmul_result_rev;\n    if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin : gen_alu_rvb_otearlgrey_full\n      /////////////////////////\n      // Shuffle / Unshuffle //\n      /////////////////////////\n      localparam logic [31:0] SHUFFLE_MASK_L [4] =\n          '{32'h00ff_0000, 32'h0f00_0f00, 32'h3030_3030, 32'h4444_4444};\n      localparam logic [31:0] SHUFFLE_MASK_R [4] =\n          '{32'h0000_ff00, 32'h00f0_00f0, 32'h0c0c_0c0c, 32'h2222_2222};\n      localparam logic [31:0] FLIP_MASK_L [4] =\n          '{32'h2200_1100, 32'h0044_0000, 32'h4411_0000, 32'h1100_0000};\n      localparam logic [31:0] FLIP_MASK_R [4] =\n          '{32'h0088_0044, 32'h0000_2200, 32'h0000_8822, 32'h0000_0088};\n      logic [31:0] SHUFFLE_MASK_NOT [4];\n      for(genvar i = 0; i < 4; i++) begin : gen_shuffle_mask_not\n        assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[i] | SHUFFLE_MASK_R[i]);\n      end\n      logic shuffle_flip;\n      assign shuffle_flip = operator_i == ALU_UNSHFL;\n      logic [3:0] shuffle_mode;\n      always_comb begin\n        shuffle_result = operand_a_i;\n        if (shuffle_flip) begin\n          shuffle_mode[3] = shift_amt[0];\n          shuffle_mode[2] = shift_amt[1];\n          shuffle_mode[1] = shift_amt[2];\n          shuffle_mode[0] = shift_amt[3];\n        end else begin\n          shuffle_mode = shift_amt[3:0];\n        end\n        if (shuffle_flip) begin\n          shuffle_result = (shuffle_result & 32'h8822_4411) |\n              ((shuffle_result << 6)  & FLIP_MASK_L[0]) |\n              ((shuffle_result >> 6)  & FLIP_MASK_R[0]) |\n              ((shuffle_result << 9)  & FLIP_MASK_L[1]) |\n              ((shuffle_result >> 9)  & FLIP_MASK_R[1]) |\n              ((shuffle_result << 15) & FLIP_MASK_L[2]) |\n              ((shuffle_result >> 15) & FLIP_MASK_R[2]) |\n              ((shuffle_result << 21) & FLIP_MASK_L[3]) |\n              ((shuffle_result >> 21) & FLIP_MASK_R[3]);\n        end\n        if (shuffle_mode[3]) begin\n          shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) |\n              (((shuffle_result << 8) & SHUFFLE_MASK_L[0]) |\n              ((shuffle_result >> 8) & SHUFFLE_MASK_R[0]));\n        end\n        if (shuffle_mode[2]) begin\n          shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) |\n              (((shuffle_result << 4) & SHUFFLE_MASK_L[1]) |\n              ((shuffle_result >> 4) & SHUFFLE_MASK_R[1]));\n        end\n        if (shuffle_mode[1]) begin\n          shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) |\n              (((shuffle_result << 2) & SHUFFLE_MASK_L[2]) |\n              ((shuffle_result >> 2) & SHUFFLE_MASK_R[2]));\n        end\n        if (shuffle_mode[0]) begin\n          shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) |\n              (((shuffle_result << 1) & SHUFFLE_MASK_L[3]) |\n              ((shuffle_result >> 1) & SHUFFLE_MASK_R[3]));\n        end\n        if (shuffle_flip) begin\n          shuffle_result = (shuffle_result & 32'h8822_4411) |\n              ((shuffle_result << 6)  & FLIP_MASK_L[0]) |\n              ((shuffle_result >> 6)  & FLIP_MASK_R[0]) |\n              ((shuffle_result << 9)  & FLIP_MASK_L[1]) |\n              ((shuffle_result >> 9)  & FLIP_MASK_R[1]) |\n              ((shuffle_result << 15) & FLIP_MASK_L[2]) |\n              ((shuffle_result >> 15) & FLIP_MASK_R[2]) |\n              ((shuffle_result << 21) & FLIP_MASK_L[3]) |\n              ((shuffle_result >> 21) & FLIP_MASK_R[3]);\n        end\n      end\n      //////////////\n      // Crossbar //\n      //////////////\n      // The crossbar permutation instructions xperm.[nbh] (Zbp) can be implemented using 8\n      // parallel 4-bit-wide, 8-input crossbars. Basically, we permute the 8 nibbles of operand_a_i\n      // based on operand_b_i.\n      // Generate selector indices and valid signals.\n      // - sel_n[x] indicates which nibble of operand_a_i is selected for output nibble x.\n      // - vld_n[x] indicates if the selection is valid.\n      logic  [7:0][2:0] sel_n; // nibbles\n      logic  [7:0]      vld_n; // nibbles\n      logic  [3:0][1:0] sel_b; // bytes\n      logic  [3:0]      vld_b; // bytes\n      logic  [1:0][0:0] sel_h; // half words\n      logic  [1:0]      vld_h; // half words\n      // Per nibble, 3 bits are needed for the selection. Other bits must be zero.\n      // sel_n bit mask: 32'b0111_0111_0111_0111_0111_0111_0111_0111\n      // vld_n bit mask: 32'b1000_1000_1000_1000_1000_1000_1000_1000\n      for (genvar i = 0; i < 8; i++) begin : gen_sel_vld_n\n        assign sel_n[i] =   operand_b_i[i*4     +: 3];\n        assign vld_n[i] = ~|operand_b_i[i*4 + 3 +: 1];\n      end\n      // Per byte, 2 bits are needed for the selection. Other bits must be zero.\n      // sel_b bit mask: 32'b0000_0011_0000_0011_0000_0011_0000_0011\n      // vld_b bit mask: 32'b1111_1100_1111_1100_1111_1100_1111_1100\n      for (genvar i = 0; i < 4; i++) begin : gen_sel_vld_b\n        assign sel_b[i] =   operand_b_i[i*8     +: 2];\n        assign vld_b[i] = ~|operand_b_i[i*8 + 2 +: 6];\n      end\n      // Per half word, 1 bit is needed for the selection only. All other bits must be zero.\n      // sel_h bit mask: 32'b0000_0000_0000_0001_0000_0000_0000_0001\n      // vld_h bit mask: 32'b1111_1111_1111_1110_1111_1111_1111_1110\n      for (genvar i = 0; i < 2; i++) begin : gen_sel_vld_h\n        assign sel_h[i] =   operand_b_i[i*16     +: 1];\n        assign vld_h[i] = ~|operand_b_i[i*16 + 1 +: 15];\n      end\n      // Convert selector indices and valid signals to control the nibble-based\n      // crossbar logic.\n      logic [7:0][2:0] sel;\n      logic [7:0]      vld;\n      always_comb begin\n        unique case (operator_i)\n          ALU_XPERM_N: begin\n            // No conversion needed.\n            sel = sel_n;\n            vld = vld_n;\n          end\n          ALU_XPERM_B: begin\n            // Convert byte to nibble indicies.\n            for (int b = 0; b < 4; b++) begin\n              sel[b*2 +  0] =   {sel_b[b], 1'b0};\n              sel[b*2 +  1] =   {sel_b[b], 1'b1};\n              vld[b*2 +: 2] = {2{vld_b[b]}};\n            end\n          end\n          ALU_XPERM_H: begin\n            // Convert half-word to nibble indices.\n            for (int h = 0; h < 2; h++) begin\n              sel[h*4 +  0] =   {sel_h[h], 2'b00};\n              sel[h*4 +  1] =   {sel_h[h], 2'b01};\n              sel[h*4 +  2] =   {sel_h[h], 2'b10};\n              sel[h*4 +  3] =   {sel_h[h], 2'b11};\n              vld[h*4 +: 4] = {4{vld_h[h]}};\n            end\n          end\n          default: begin\n            // Tie valid to zero to disable the crossbar unless we need it.\n            sel = sel_n;\n            vld = '0;\n          end\n        endcase\n      end\n      // The actual nibble-based crossbar logic.\n      logic [7:0][3:0] val_n;\n      logic [7:0][3:0] xperm_n;\n      assign val_n = operand_a_i;\n      for (genvar i = 0; i < 8; i++) begin : gen_xperm_n\n        assign xperm_n[i] = vld[i] ? val_n[sel[i]] : '0;\n      end\n      assign xperm_result = xperm_n;\n      ///////////////////////////////////////////////////\n      // Carry-less Multiply + Cyclic Redundancy Check //\n      ///////////////////////////////////////////////////\n      // Carry-less multiplication can be understood as multiplication based on\n      // the addition interpreted as the bit-wise xor operation.\n      //\n      // Example: 1101 X 1011 = 1111111:\n      //\n      //       1011 X 1101\n      //       -----------\n      //              1101\n      //         xor 1101\n      //         ---------\n      //             10111\n      //        xor 0000\n      //        ----------\n      //            010111\n      //       xor 1101\n      //       -----------\n      //           1111111\n      //\n      // Architectural details:\n      //         A 32 x 32-bit array\n      //         [ operand_b[i] ? (operand_a << i) : '0 for i in 0 ... 31 ]\n      //         is generated. The entries of the array are pairwise 'xor-ed'\n      //         together in a 5-stage binary tree.\n      //\n      //\n      // Cyclic Redundancy Check:\n      //\n      // CRC-32 (CRC-32/ISO-HDLC) and CRC-32C (CRC-32/ISCSI) are directly implemented. For\n      // documentation of the crc configuration (crc-polynomials, initialization, reflection, etc.)\n      // see http://reveng.sourceforge.net/crc-catalogue/all.htm\n      // A useful guide to crc arithmetic and algorithms is given here:\n      // http://www.piclist.com/techref/method/math/crcguide.html.\n      //\n      // The CRC operation solves the following equation using binary polynomial arithmetic:\n      //\n      // rev(rd)(x) = rev(rs1)(x) * x**n mod {1, P}(x)\n      //\n      // where P denotes lower 32 bits of the corresponding CRC polynomial, rev(a) the bit reversal\n      // of a, n = 8,16, or 32 for .b, .h, .w -variants. {a, b} denotes bit concatenation.\n      //\n      // Using barret reduction, one can show that\n      //\n      // M(x) mod P(x) = R(x) =\n      //          (M(x) * x**n) & {deg(P(x)'{1'b1}}) ^ (M(x) x**-(deg(P(x) - n)) cx mu(x) cx P(x),\n      //\n      // Where mu(x) = polydiv(x**64, {1,P}) & 0xffffffff. Here, 'cx' refers to carry-less\n      // multiplication. Substituting rev(rd)(x) for R(x) and rev(rs1)(x) for M(x) and solving for\n      // rd(x) with P(x) a crc32 polynomial (deg(P(x)) = 32), we get\n      //\n      // rd = rev( (rev(rs1) << n)  ^ ((rev(rs1) >> (32-n)) cx mu cx P)\n      //    = (rs1 >> n) ^ rev(rev( (rs1 << (32-n)) cx rev(mu)) cx P)\n      //                       ^-- cycle 0--------------------^\n      //      ^- cycle 1 -------------------------------------------^\n      //\n      // In the last step we used the fact that carry-less multiplication is bit-order agnostic:\n      // rev(a cx b) = rev(a) cx rev(b).\n      logic clmul_rmode;\n      logic clmul_hmode;\n      logic [31:0] clmul_op_a;\n      logic [31:0] clmul_op_b;\n      logic [31:0] operand_b_rev;\n      logic [31:0] clmul_and_stage[32];\n      logic [31:0] clmul_xor_stage1[16];\n      logic [31:0] clmul_xor_stage2[8];\n      logic [31:0] clmul_xor_stage3[4];\n      logic [31:0] clmul_xor_stage4[2];\n      logic [31:0] clmul_result_raw;\n      for (genvar i = 0; i < 32; i++) begin : gen_rev_operand_b\n        assign operand_b_rev[i] = operand_b_i[31-i];\n      end\n      assign clmul_rmode = operator_i == ALU_CLMULR;\n      assign clmul_hmode = operator_i == ALU_CLMULH;\n      // CRC\n      localparam logic [31:0] CRC32_POLYNOMIAL = 32'h04c1_1db7;\n      localparam logic [31:0] CRC32_MU_REV = 32'hf701_1641;\n      localparam logic [31:0] CRC32C_POLYNOMIAL = 32'h1edc_6f41;\n      localparam logic [31:0] CRC32C_MU_REV = 32'hdea7_13f1;\n      logic crc_op;\n      logic crc_cpoly;\n      logic [31:0] crc_operand;\n      logic [31:0] crc_poly;\n      logic [31:0] crc_mu_rev;\n      assign crc_op = (operator_i == ALU_CRC32C_W) | (operator_i == ALU_CRC32_W) |\n                      (operator_i == ALU_CRC32C_H) | (operator_i == ALU_CRC32_H) |\n                      (operator_i == ALU_CRC32C_B) | (operator_i == ALU_CRC32_B);\n      assign crc_cpoly = (operator_i == ALU_CRC32C_W) |\n                         (operator_i == ALU_CRC32C_H) |\n                         (operator_i == ALU_CRC32C_B);\n      assign crc_hmode = (operator_i == ALU_CRC32_H) | (operator_i == ALU_CRC32C_H);\n      assign crc_bmode = (operator_i == ALU_CRC32_B) | (operator_i == ALU_CRC32C_B);\n      assign crc_poly   = crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL;\n      assign crc_mu_rev = crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV;\n      always_comb begin\n        unique case (1'b1)\n          crc_bmode: crc_operand = {operand_a_i[7:0], 24'h0};\n          crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0};\n          default:   crc_operand = operand_a_i;\n        endcase\n      end\n      // Select clmul input\n      always_comb begin\n        if (crc_op) begin\n          clmul_op_a = instr_first_cycle_i ? crc_operand : imd_val_q_i[0];\n          clmul_op_b = instr_first_cycle_i ? crc_mu_rev : crc_poly;\n        end else begin\n          clmul_op_a = clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i;\n          clmul_op_b = clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i;\n        end\n      end\n      for (genvar i = 0; i < 32; i++) begin : gen_clmul_and_op\n        assign clmul_and_stage[i] = clmul_op_b[i] ? clmul_op_a << i : '0;\n      end\n      for (genvar i = 0; i < 16; i++) begin : gen_clmul_xor_op_l1\n        assign clmul_xor_stage1[i] = clmul_and_stage[2*i] ^ clmul_and_stage[2*i+1];\n      end\n      for (genvar i = 0; i < 8; i++) begin : gen_clmul_xor_op_l2\n        assign clmul_xor_stage2[i] = clmul_xor_stage1[2*i] ^ clmul_xor_stage1[2*i+1];\n      end\n      for (genvar i = 0; i < 4; i++) begin : gen_clmul_xor_op_l3\n        assign clmul_xor_stage3[i] = clmul_xor_stage2[2*i] ^ clmul_xor_stage2[2*i+1];\n      end\n      for (genvar i = 0; i < 2; i++) begin : gen_clmul_xor_op_l4\n        assign clmul_xor_stage4[i] = clmul_xor_stage3[2*i] ^ clmul_xor_stage3[2*i+1];\n      end\n      assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1];\n      for (genvar i = 0; i < 32; i++) begin : gen_rev_clmul_result\n        assign clmul_result_rev[i] = clmul_result_raw[31-i];\n      end\n      // clmulr_result = rev(clmul(rev(a), rev(b)))\n      // clmulh_result = clmulr_result >> 1\n      always_comb begin\n        case (1'b1)\n          clmul_rmode: clmul_result = clmul_result_rev;\n          clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]};\n          default:     clmul_result = clmul_result_raw;\n        endcase\n      end\n    end else begin : gen_alu_rvb_not_otearlgrey_full\n      assign shuffle_result       = '0;\n      assign xperm_result         = '0;\n      assign clmul_result         = '0;\n      // support signals\n      assign clmul_result_rev     = '0;\n      assign crc_bmode            = '0;\n      assign crc_hmode            = '0;\n    end\n    if (RV32B == RV32BFull) begin : gen_alu_rvb_full\n      ///////////////\n      // Butterfly //\n      ///////////////\n      // The butterfly / inverse butterfly network executing bcompress/bdecompress (zbe)\n      // instructions. For bdecompress, the control bits mask of a local left region is generated\n      // by the inverse of a n-bit left rotate and complement upon wrap (LROTC) operation by the\n      // number of ones in the deposit bitmask to the right of the segment. n hereby denotes the\n      // width of the according segment. The bitmask for a pertaining local right region is equal\n      // to the corresponding local left region. Bcompress uses an analogue inverse process.\n      // Consider the following 8-bit example.  For details, see Hilewitz et al. \"Fast Bit Gather,\n      // Bit Scatter and Bit Permuation Instructions for Commodity Microprocessors\", (2008).\n      //\n      // The bcompress/bdecompress instructions are completed in 2 cycles. In the first cycle, the\n      // control bitmask is prepared by executing the parallel prefix bit count. In the second\n      // cycle, the bit swapping is executed according to the control masks.\n      // 8-bit example:  (Hilewitz et al.)\n      // Consider the instruction bdecompress operand_a_i deposit_mask\n      // Let operand_a_i = 8'babcd_efgh\n      //    deposit_mask = 8'b1010_1101\n      //\n      // control bitmask for stage 1:\n      //  - number of ones in the right half of the deposit bitmask: 3\n      //  - width of the segment: 4\n      //  - control bitmask = ~LROTC(4'b0, 3)[3:0] = 4'b1000\n      //\n      // control bitmask:   c3 c2  c1 c0  c3 c2  c1 c0\n      //                    1  0   0  0   1  0   0  0\n      //                    <- L ----->   <- R ----->\n      // operand_a_i        a  b   c  d   e  f   g  h\n      //                    :\\ |   |  |  /:  |   |  |\n      //                    : +|---|--|-+ :  |   |  |\n      //                    :/ |   |  |  \\:  |   |  |\n      // stage 1            e  b   c  d   a  f   g  h\n      //                    <L->   <R->   <L->   <R->\n      // control bitmask:   c3 c2  c3 c2  c1 c0  c1 c0\n      //                    1  1   1  1   1  0   1  0\n      //                    :\\ :\\ /: /:   :\\ |  /:  |\n      //                    : +:-+-:+ :   : +|-+ :  |\n      //                    :/ :/ \\: \\:   :/ |  \\:  |\n      // stage 2            c  d   e  b   g  f   a  h\n      //                    L  R   L  R   L  R   L  R\n      // control bitmask:   c3 c3  c2 c2  c1 c1  c0 c0\n      //                    1  1   0  0   1  1   0  0\n      //                    :\\/:   |  |   :\\/:   |  |\n      //                    :  :   |  |   :  :   |  |\n      //                    :/\\:   |  |   :/\\:   |  |\n      // stage 3            d  c   e  b   f  g   a  h\n      // & deposit bitmask: 1  0   1  0   1  1   0  1\n      // result:            d  0   e  0   f  g   0  h\n      logic [ 5:0] bitcnt_partial_q [32];\n      // first cycle\n      // Store partial bitcnts\n      for (genvar i = 0; i < 32; i++) begin : gen_bitcnt_reg_in_lsb\n        assign bitcnt_partial_lsb_d[i] = bitcnt_partial[i][0];\n      end\n      for (genvar i = 0; i < 16; i++) begin : gen_bitcnt_reg_in_b1\n        assign bitcnt_partial_msb_d[i] = bitcnt_partial[2*i+1][1];\n      end\n      for (genvar i = 0; i < 8; i++) begin : gen_bitcnt_reg_in_b2\n        assign bitcnt_partial_msb_d[16+i] = bitcnt_partial[4*i+3][2];\n      end\n      for (genvar i = 0; i < 4; i++) begin : gen_bitcnt_reg_in_b3\n        assign bitcnt_partial_msb_d[24+i] = bitcnt_partial[8*i+7][3];\n      end\n      for (genvar i = 0; i < 2; i++) begin : gen_bitcnt_reg_in_b4\n        assign bitcnt_partial_msb_d[28+i] = bitcnt_partial[16*i+15][4];\n      end\n      assign bitcnt_partial_msb_d[30] = bitcnt_partial[31][5];\n      assign bitcnt_partial_msb_d[31] = 1'b0; // unused\n      // Second cycle\n      // Load partial bitcnts\n      always_comb begin\n        bitcnt_partial_q = '{default: '0};\n        for (int unsigned i = 0; i < 32; i++) begin : gen_bitcnt_reg_out_lsb\n          bitcnt_partial_q[i][0] = imd_val_q_i[0][i];\n        end\n        for (int unsigned i = 0; i < 16; i++) begin : gen_bitcnt_reg_out_b1\n          bitcnt_partial_q[2*i+1][1] = imd_val_q_i[1][i];\n        end\n        for (int unsigned i = 0; i < 8; i++) begin : gen_bitcnt_reg_out_b2\n          bitcnt_partial_q[4*i+3][2] = imd_val_q_i[1][16+i];\n        end\n        for (int unsigned i = 0; i < 4; i++) begin : gen_bitcnt_reg_out_b3\n          bitcnt_partial_q[8*i+7][3] = imd_val_q_i[1][24+i];\n        end\n        for (int unsigned i = 0; i < 2; i++) begin : gen_bitcnt_reg_out_b4\n          bitcnt_partial_q[16*i+15][4] = imd_val_q_i[1][28+i];\n        end\n        bitcnt_partial_q[31][5] = imd_val_q_i[1][30];\n      end\n      logic [31:0] butterfly_mask_l[5];\n      logic [31:0] butterfly_mask_r[5];\n      logic [31:0] butterfly_mask_not[5];\n      logic [31:0] lrotc_stage [5]; // left rotate and complement upon wrap\n      // number of bits in local r = 32 / 2**(stage + 1) = 16/2**stage\n      // bcompress / bdecompress control bit generation\n      for (genvar stg = 0; stg < 5; stg++) begin : gen_butterfly_ctrl_stage\n        // number of segs: 2** stg\n        for (genvar seg=0; seg<2**stg; seg++) begin : gen_butterfly_ctrl\n          assign lrotc_stage[stg][2*(16 >> stg)*(seg+1)-1 : 2*(16 >> stg)*seg] =\n              {{(16 >> stg){1'b0}},{(16 >> stg){1'b1}}} <<\n                bitcnt_partial_q[(16 >> stg)*(2*seg+1)-1][$clog2((16 >> stg)):0];\n          assign butterfly_mask_l[stg][(16 >> stg)*(2*seg+2)-1 : (16 >> stg)*(2*seg+1)]\n                   = ~lrotc_stage[stg][(16 >> stg)*(2*seg+2)-1 : (16 >> stg)*(2*seg+1)];\n          assign butterfly_mask_r[stg][(16 >> stg)*(2*seg+1)-1 : (16 >> stg)*(2*seg)]\n                   = ~lrotc_stage[stg][(16 >> stg)*(2*seg+2)-1 : (16 >> stg)*(2*seg+1)];\n          assign butterfly_mask_l[stg][(16 >> stg)*(2*seg+1)-1 : (16 >> stg)*(2*seg)]   = '0;\n          assign butterfly_mask_r[stg][(16 >> stg)*(2*seg+2)-1 : (16 >> stg)*(2*seg+1)] = '0;\n        end\n      end\n      for (genvar stg = 0; stg < 5; stg++) begin : gen_butterfly_not\n        assign butterfly_mask_not[stg] =\n            ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]);\n      end\n      always_comb begin\n        butterfly_result = operand_a_i;\n        butterfly_result = butterfly_result & butterfly_mask_not[0] |\n            ((butterfly_result & butterfly_mask_l[0]) >> 16)|\n            ((butterfly_result & butterfly_mask_r[0]) << 16);\n        butterfly_result = butterfly_result & butterfly_mask_not[1] |\n            ((butterfly_result & butterfly_mask_l[1]) >> 8)|\n            ((butterfly_result & butterfly_mask_r[1]) << 8);\n        butterfly_result = butterfly_result & butterfly_mask_not[2] |\n            ((butterfly_result & butterfly_mask_l[2]) >> 4)|\n            ((butterfly_result & butterfly_mask_r[2]) << 4);\n        butterfly_result = butterfly_result & butterfly_mask_not[3] |\n            ((butterfly_result & butterfly_mask_l[3]) >> 2)|\n            ((butterfly_result & butterfly_mask_r[3]) << 2);\n        butterfly_result = butterfly_result & butterfly_mask_not[4] |\n            ((butterfly_result & butterfly_mask_l[4]) >> 1)|\n            ((butterfly_result & butterfly_mask_r[4]) << 1);\n        butterfly_result = butterfly_result & operand_b_i;\n      end\n      always_comb begin\n        invbutterfly_result = operand_a_i & operand_b_i;\n        invbutterfly_result = invbutterfly_result & butterfly_mask_not[4] |\n            ((invbutterfly_result & butterfly_mask_l[4]) >> 1)|\n            ((invbutterfly_result & butterfly_mask_r[4]) << 1);\n        invbutterfly_result = invbutterfly_result & butterfly_mask_not[3] |\n            ((invbutterfly_result & butterfly_mask_l[3]) >> 2)|\n            ((invbutterfly_result & butterfly_mask_r[3]) << 2);\n        invbutterfly_result = invbutterfly_result & butterfly_mask_not[2] |\n            ((invbutterfly_result & butterfly_mask_l[2]) >> 4)|\n            ((invbutterfly_result & butterfly_mask_r[2]) << 4);\n        invbutterfly_result = invbutterfly_result & butterfly_mask_not[1] |\n            ((invbutterfly_result & butterfly_mask_l[1]) >> 8)|\n            ((invbutterfly_result & butterfly_mask_r[1]) << 8);\n        invbutterfly_result = invbutterfly_result & butterfly_mask_not[0] |\n            ((invbutterfly_result & butterfly_mask_l[0]) >> 16)|\n            ((invbutterfly_result & butterfly_mask_r[0]) << 16);\n      end\n    end else begin : gen_alu_rvb_not_full\n      logic [31:0] unused_imd_val_q_1;\n      assign unused_imd_val_q_1   = imd_val_q_i[1];\n      assign butterfly_result     = '0;\n      assign invbutterfly_result  = '0;\n      // support signals\n      assign bitcnt_partial_lsb_d = '0;\n      assign bitcnt_partial_msb_d = '0;\n    end\n    //////////////////////////////////////\n    // Multicycle Bitmanip Instructions //\n    //////////////////////////////////////\n    // Ternary instructions + Shift Rotations + Bit Compress/Decompress + CRC\n    // For ternary instructions (zbt), operand_a_i is tied to rs1 in the first cycle and rs3 in the\n    // second cycle. operand_b_i is always tied to rs2.\n    always_comb begin\n      unique case (operator_i)\n        ALU_CMOV: begin\n          multicycle_result = (operand_b_i == 32'h0) ? operand_a_i : imd_val_q_i[0];\n          imd_val_d_o = '{operand_a_i, 32'h0};\n          if (instr_first_cycle_i) begin\n            imd_val_we_o = 2'b01;\n          end else begin\n            imd_val_we_o = 2'b00;\n          end\n        end\n        ALU_CMIX: begin\n          multicycle_result = imd_val_q_i[0] | bwlogic_and_result;\n          imd_val_d_o = '{bwlogic_and_result, 32'h0};\n          if (instr_first_cycle_i) begin\n            imd_val_we_o = 2'b01;\n          end else begin\n            imd_val_we_o = 2'b00;\n          end\n        end\n        ALU_FSR, ALU_FSL,\n        ALU_ROL, ALU_ROR: begin\n          if (shift_amt[4:0] == 5'h0) begin\n            multicycle_result = shift_amt[5] ? operand_a_i : imd_val_q_i[0];\n          end else begin\n            multicycle_result = imd_val_q_i[0] | shift_result;\n          end\n          imd_val_d_o = '{shift_result, 32'h0};\n          if (instr_first_cycle_i) begin\n            imd_val_we_o = 2'b01;\n          end else begin\n            imd_val_we_o = 2'b00;\n          end\n        end\n        ALU_CRC32_W, ALU_CRC32C_W,\n        ALU_CRC32_H, ALU_CRC32C_H,\n        ALU_CRC32_B, ALU_CRC32C_B: begin\n          if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n            unique case (1'b1)\n              crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8);\n              crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16);\n              default:   multicycle_result = clmul_result_rev;\n            endcase\n            imd_val_d_o = '{clmul_result_rev, 32'h0};\n            if (instr_first_cycle_i) begin\n              imd_val_we_o = 2'b01;\n            end else begin\n              imd_val_we_o = 2'b00;\n            end\n          end else begin\n            imd_val_d_o = '{operand_a_i, 32'h0};\n            imd_val_we_o = 2'b00;\n            multicycle_result = '0;\n          end\n        end\n        ALU_BCOMPRESS, ALU_BDECOMPRESS: begin\n          if (RV32B == RV32BFull) begin\n            multicycle_result = (operator_i == ALU_BDECOMPRESS) ? butterfly_result :\n                                                                  invbutterfly_result;\n            imd_val_d_o = '{bitcnt_partial_lsb_d, bitcnt_partial_msb_d};\n            if (instr_first_cycle_i) begin\n              imd_val_we_o = 2'b11;\n            end else begin\n              imd_val_we_o = 2'b00;\n            end\n          end else begin\n            imd_val_d_o = '{operand_a_i, 32'h0};\n            imd_val_we_o = 2'b00;\n            multicycle_result = '0;\n          end\n        end\n        default: begin\n          imd_val_d_o = '{operand_a_i, 32'h0};\n          imd_val_we_o = 2'b00;\n          multicycle_result = '0;\n        end\n      endcase\n    end\n  end else begin : g_no_alu_rvb\n    logic [31:0] unused_imd_val_q[2];\n    assign unused_imd_val_q           = imd_val_q_i;\n    logic [31:0] unused_butterfly_result;\n    assign unused_butterfly_result    = butterfly_result;\n    logic [31:0] unused_invbutterfly_result;\n    assign unused_invbutterfly_result = invbutterfly_result;\n    // RV32B result signals\n    assign bitcnt_result       = '0;\n    assign minmax_result       = '0;\n    assign pack_result         = '0;\n    assign sext_result         = '0;\n    assign singlebit_result    = '0;\n    assign rev_result          = '0;\n    assign shuffle_result      = '0;\n    assign xperm_result        = '0;\n    assign butterfly_result    = '0;\n    assign invbutterfly_result = '0;\n    assign clmul_result        = '0;\n    assign multicycle_result   = '0;\n    // RV32B support signals\n    assign imd_val_d_o         = '{default: '0};\n    assign imd_val_we_o        = '{default: '0};\n  end\n  ////////////////\n  // Result mux //\n  ////////////////\n  always_comb begin\n    result_o   = '0;\n    unique case (operator_i)\n      // Bitwise Logic Operations (negate: RV32B)\n      ALU_XOR,  ALU_XNOR,\n      ALU_OR,   ALU_ORN,\n      ALU_AND,  ALU_ANDN: result_o = bwlogic_result;\n      // Adder Operations\n      ALU_ADD,  ALU_SUB,\n      // RV32B\n      ALU_SH1ADD, ALU_SH2ADD,\n      ALU_SH3ADD: result_o = adder_result;\n      // Shift Operations\n      ALU_SLL,  ALU_SRL,\n      ALU_SRA,\n      // RV32B\n      ALU_SLO,  ALU_SRO: result_o = shift_result;\n      // Shuffle Operations (RV32B)\n      ALU_SHFL, ALU_UNSHFL: result_o = shuffle_result;\n      // Crossbar Permutation Operations (RV32B)\n      ALU_XPERM_N, ALU_XPERM_B, ALU_XPERM_H: result_o = xperm_result;\n      // Comparison Operations\n      ALU_EQ,   ALU_NE,\n      ALU_GE,   ALU_GEU,\n      ALU_LT,   ALU_LTU,\n      ALU_SLT,  ALU_SLTU: result_o = {31'h0,cmp_result};\n      // MinMax Operations (RV32B)\n      ALU_MIN,  ALU_MAX,\n      ALU_MINU, ALU_MAXU: result_o = minmax_result;\n      // Bitcount Operations (RV32B)\n      ALU_CLZ, ALU_CTZ,\n      ALU_CPOP: result_o = {26'h0, bitcnt_result};\n      // Pack Operations (RV32B)\n      ALU_PACK, ALU_PACKH,\n      ALU_PACKU: result_o = pack_result;\n      // Sign-Extend (RV32B)\n      ALU_SEXTB, ALU_SEXTH: result_o = sext_result;\n      // Ternary Bitmanip Operations (RV32B)\n      ALU_CMIX, ALU_CMOV,\n      ALU_FSL,  ALU_FSR,\n      // Rotate Shift (RV32B)\n      ALU_ROL, ALU_ROR,\n      // Cyclic Redundancy Checks (RV32B)\n      ALU_CRC32_W, ALU_CRC32C_W,\n      ALU_CRC32_H, ALU_CRC32C_H,\n      ALU_CRC32_B, ALU_CRC32C_B,\n      // Bit Compress / Decompress (RV32B)\n      ALU_BCOMPRESS, ALU_BDECOMPRESS: result_o = multicycle_result;\n      // Single-Bit Bitmanip Operations (RV32B)\n      ALU_BSET, ALU_BCLR,\n      ALU_BINV, ALU_BEXT: result_o = singlebit_result;\n      // General Reverse / Or-combine (RV32B)\n      ALU_GREV, ALU_GORC: result_o = rev_result;\n      // Bit Field Place (RV32B)\n      ALU_BFP: result_o = bfp_result;\n      // Carry-less Multiply Operations (RV32B)\n      ALU_CLMUL, ALU_CLMULR,\n      ALU_CLMULH: result_o = clmul_result;\n      default: ;\n    endcase\n  end\n  logic unused_shift_amt_compl;\n  assign unused_shift_amt_compl = shift_amt_compl[5];\nendmodule\n", "mask_idx": {"conditional_statement": [[20280, 20329], [41141, 41425], [40404, 40620], [43411, 43638], [64856, 64993], [65345, 65482], [44119, 44346], [64551, 64688], [43647, 43874], [53181, 53536], [66023, 66168], [44355, 44915]], "blocking_assignment": [[40440, 40610], [38083, 38148], [20649, 20688], [65730, 65788], [22700, 22723], [53209, 53273], [28553, 28571], [63435, 63632]], "always_construct": [[36725, 38166], [21572, 21782], [31607, 31832], [22577, 22997], [29575, 30526], [38465, 38749], [62536, 63642], [42502, 44925], [33980, 34224], [40125, 41433], [19782, 20499], [52877, 53120], [30834, 31180], [54652, 54897], [20981, 21210], [21891, 22110], [28491, 29249], [33547, 33890], [27595, 27954], [61441, 62529], [39051, 39392], [68161, 70282], [59100, 59959], [47046, 48118], [64336, 67167], [53155, 53546], [20525, 20897]], "case_statement": [[52903, 53110], [21594, 21776], [38489, 38741], [28513, 29182], [31629, 31826], [54678, 54887], [68204, 70276], [47072, 48108], [65686, 65956], [19924, 20493], [34004, 34216], [21003, 21204], [22599, 22991], [30856, 31174], [39075, 39384], [29830, 30047], [64360, 67159], [20547, 20891]], "ansi_port_declaration": [[19230, 19273], [18690, 18728], [19143, 19178], [19051, 19092], [18731, 18777], [18829, 18875], [18878, 18918], [19181, 19227]], "continuous_assign": [[67440, 67496], [31183, 31266], [31458, 31529], [52563, 52641], [52648, 52726], [33895, 33975], [52396, 52556], [33003, 33048], [67603, 67635], [68002, 68046], [52733, 52802], [48394, 48424], [67242, 67290]], "parameter_declaration": [[13332, 13380], [12925, 13002], [12625, 12677], [12792, 12845], [12736, 12789], [13189, 13235], [12570, 12622], [12464, 12546], [13140, 13186], [6471, 6520]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[19483, 19527], [20923, 20978], [21231, 21305], [21308, 21361], [21364, 21405], [21785, 21827], [21830, 21866], [23000, 23040], [26842, 26912], [26915, 27009], [27012, 27048], [27051, 27125], [27189, 27229], [27238, 27361], [27490, 27542], [27545, 27592], [27985, 28122], [29252, 29298], [29301, 29437], [29440, 29548], [31183, 31266], [31269, 31329], [31332, 31392], [31395, 31455], [31458, 31529], [31532, 31604], [32953, 32998], [33003, 33048], [33053, 33100], [33105, 33147], [33477, 33542], [33895, 33975], [38231, 38293], [38377, 38416], [38421, 38460], [38799, 38944], [39824, 39866], [39871, 39993], [39998, 40120], [42303, 42373], [42416, 42463], [45956, 46002], [46011, 46057], [46354, 46400], [46409, 46455], [46764, 46811], [46820, 46868], [48236, 48263], [48329, 48377], [48394, 48424], [51583, 51627], [51644, 51690], [51697, 51743], [52148, 52389], [52396, 52556], [52563, 52641], [52648, 52726], [52733, 52802], [52809, 52870], [53618, 53683], [53768, 53843], [53927, 54004], [54088, 54165], [54249, 54326], [54343, 54411], [54487, 54539], [54957, 54990], [54997, 55030], [55037, 55070], [55102, 55135], [55142, 55175], [55182, 55215], [58274, 58328], [58414, 58472], [58557, 58618], [58703, 58764], [58849, 58912], [58929, 58985], [58992, 59041], [60479, 60690], [60701, 60867], [60878, 61042], [61053, 61136], [61147, 61230], [61330, 61424], [63730, 63775], [63782, 63815], [63822, 63855], [63887, 63920], [63927, 63960], [67242, 67290], [67337, 67390], [67440, 67496], [67529, 67561], [67566, 67598], [67603, 67635], [67640, 67672], [67677, 67709], [67714, 67746], [67751, 67783], [67788, 67820], [67825, 67857], [67862, 67894], [67899, 67931], [67936, 67968], [68002, 68046], [68051, 68095], [70317, 70368]], "blocking_assignment": [[19804, 19829], [19834, 19859], [19864, 19889], [19894, 19919], [20191, 20216], [20304, 20329], [20372, 20397], [20440, 20465], [20590, 20623], [20649, 20688], [20714, 20754], [20780, 20821], [20847, 20879], [21047, 21080], [21106, 21133], [21159, 21192], [21712, 21730], [21746, 21764], [21974, 22020], [22046, 22096], [22650, 22673], [22700, 22723], [22775, 22819], [22910, 22941], [22957, 22979], [27641, 27703], [27729, 27940], [28553, 28571], [28587, 28663], [28679, 28727], [28743, 28803], [28819, 28880], [28896, 29007], [29023, 29136], [29152, 29170], [29217, 29235], [29747, 29804], [29871, 29900], [29923, 29953], [29976, 30033], [30060, 30186], [30191, 30245], [30250, 30299], [30304, 30351], [30406, 30447], [30460, 30520], [30971, 31028], [31045, 31118], [31135, 31162], [31667, 31702], [31722, 31758], [31778, 31814], [33571, 33604], [33611, 33651], [33658, 33698], [33705, 33745], [33752, 33792], [33799, 33840], [33847, 33882], [34037, 34063], [34085, 34146], [34168, 34202], [36749, 36781], [36860, 36930], [37019, 37079], [37168, 37228], [37319, 37379], [37413, 37474], [37594, 37655], [37735, 37795], [37884, 37944], [37978, 38021], [38083, 38148], [38525, 38580], [38598, 38656], [38674, 38727], [39118, 39164], [39183, 39230], [39249, 39295], [39314, 39370], [40149, 40174], [40217, 40387], [40440, 40610], [40663, 40833], [40886, 41124], [41177, 41415], [42528, 42557], [42600, 42631], [42642, 42673], [42684, 42715], [42726, 42757], [42791, 42821], [42876, 43390], [43448, 43626], [43684, 43862], [43920, 44098], [44156, 44334], [44389, 44903], [47175, 47187], [47200, 47212], [47364, 47399], [47414, 47449], [47464, 47494], [47666, 47702], [47717, 47753], [47768, 47804], [47819, 47855], [47870, 47900], [48044, 48056], [48069, 48078], [52943, 52983], [53005, 53046], [53068, 53094], [53209, 53273], [53284, 53341], [53375, 53444], [53455, 53524], [54713, 54745], [54769, 54815], [54839, 54871], [59126, 59160], [59248, 59291], [59390, 59437], [59535, 59585], [59683, 59733], [59831, 59883], [59904, 59949], [61467, 61498], [61507, 61692], [61701, 61884], [61893, 62076], [62085, 62268], [62277, 62460], [62469, 62519], [62562, 62610], [62619, 62814], [62823, 63018], [63027, 63222], [63231, 63426], [63435, 63632], [64419, 64493], [64504, 64540], [64594, 64615], [64653, 64674], [64735, 64791], [64802, 64845], [64899, 64920], [64958, 64979], [65120, 65184], [65222, 65272], [65297, 65334], [65388, 65409], [65447, 65468], [65730, 65788], [65814, 65873], [65899, 65936], [65969, 66010], [66068, 66089], [66131, 66152], [66206, 66242], [66255, 66276], [66289, 66312], [66437, 66596], [66609, 66669], [66727, 66748], [66790, 66811], [66865, 66901], [66914, 66935], [66948, 66971], [67031, 67067], [67078, 67099], [67110, 67133], [68183, 68199], [68356, 68382], [68497, 68521], [68628, 68652], [68717, 68743], [68838, 68862], [68994, 69024], [69111, 69136], [69214, 69248], [69326, 69349], [69407, 69430], [69803, 69832], [69933, 69961], [70034, 70056], [70105, 70127], [70223, 70247]], "nonblocking_assignment": [], "case_statement": [[19924, 20493], [20547, 20891], [21003, 21204], [21594, 21776], [22599, 22991], [28513, 29182], [29830, 30047], [30856, 31174], [31629, 31826], [34004, 34216], [38489, 38741], [39075, 39384], [47072, 48108], [52903, 53110], [54678, 54887], [64360, 67159], [65686, 65956], [68204, 70276]], "conditional_statement": [[20280, 20329], [20348, 20397], [20416, 20465], [21913, 22104], [27617, 27948], [29187, 29243], [29711, 30055], [40181, 40397], [40404, 40620], [40627, 40843], [40850, 41134], [41141, 41425], [42566, 42833], [42842, 43402], [43411, 43638], [43647, 43874], [43883, 44110], [44119, 44346], [44355, 44915], [53181, 53536], [64551, 64688], [64856, 64993], [65074, 65286], [65345, 65482], [65616, 66326], [66023, 66168], [66395, 66985], [66682, 66827]], "always_construct": [[19782, 20499], [20525, 20897], [20981, 21210], [21572, 21782], [21891, 22110], [22577, 22997], [27595, 27954], [28491, 29249], [29575, 30526], [30834, 31180], [31607, 31832], [33547, 33890], [33980, 34224], [36725, 38166], [38465, 38749], [39051, 39392], [40125, 41433], [42502, 44925], [47046, 48118], [52877, 53120], [53155, 53546], [54652, 54897], [59100, 59959], [61441, 62529], [62536, 63642], [64336, 67167], [68161, 70282]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096], [18547, 18602]], "ansi_port_declaration": [[18609, 18646], [18649, 18687], [18690, 18728], [18731, 18777], [18780, 18826], [18829, 18875], [18878, 18918], [18921, 18962], [18965, 19006], [19009, 19048], [19051, 19092], [19095, 19140], [19143, 19178], [19181, 19227], [19230, 19273]]}}
{"sample_i": "p10", "topmodule": "cve2_multdiv_slow", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Slow Multiplier and Division\n *\n * Baugh-Wooley multiplier and Long Division\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_multdiv_slow\n(\n  input  logic             clk_i,\n  input  logic             rst_ni,\n  input  logic             mult_en_i,  // dynamic enable signal, for FSM control\n  input  logic             div_en_i,   // dynamic enable signal, for FSM control\n  input  logic             mult_sel_i, // static decoder output, for data muxes\n  input  logic             div_sel_i,  // static decoder output, for data muxes\n  input  cve2_pkg::md_op_e operator_i,\n  input  logic  [1:0]      signed_mode_i,\n  input  logic [31:0]      op_a_i,\n  input  logic [31:0]      op_b_i,\n  input  logic [33:0]      alu_adder_ext_i,\n  input  logic [31:0]      alu_adder_i,\n  input  logic             equal_to_zero_i,\n  output logic [32:0]      alu_operand_a_o,\n  output logic [32:0]      alu_operand_b_o,\n  input  logic [33:0]      imd_val_q_i[2],\n  output logic [33:0]      imd_val_d_o[2],\n  output logic  [1:0]      imd_val_we_o,\n  input  logic             multdiv_ready_id_i,\n  output logic [31:0]      multdiv_result_o,\n  output logic             valid_o\n);\n  import cve2_pkg::*;\n  typedef enum logic [2:0] {\n    MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH\n  } md_fsm_e;\n  md_fsm_e md_state_q, md_state_d;\n  logic [32:0] accum_window_q, accum_window_d;\n  logic        unused_imd_val0;\n  logic [ 1:0] unused_imd_val1;\n  logic [32:0] res_adder_l;\n  logic [32:0] res_adder_h;\n  logic [ 4:0] multdiv_count_q, multdiv_count_d;\n  logic [32:0] op_b_shift_q, op_b_shift_d;\n  logic [32:0] op_a_shift_q, op_a_shift_d;\n  logic [32:0] op_a_ext, op_b_ext;\n  logic [32:0] one_shift;\n  logic [32:0] op_a_bw_pp, op_a_bw_last_pp;\n  logic [31:0] b_0;\n  logic        sign_a, sign_b;\n  logic [32:0] next_quotient;\n  logic [31:0] next_remainder;\n  logic [31:0] op_numerator_q, op_numerator_d;\n  logic        is_greater_equal;\n  logic        div_change_sign, rem_change_sign;\n  logic        div_by_zero_d, div_by_zero_q;\n  logic        multdiv_hold;\n  logic        multdiv_en;\n   // (accum_window_q + op_a_shift_q)\n  assign res_adder_l = alu_adder_ext_i[32:0];\n   // (accum_window_q + op_a_shift_q)>>1\n  assign res_adder_h = alu_adder_ext_i[33:1];\n  /////////////////////\n  // ALU Operand MUX //\n  /////////////////////\n  // Intermediate value register shared with ALU\n  assign imd_val_d_o[0]  = {1'b0,accum_window_d};\n  assign imd_val_we_o[0] = ~multdiv_hold;\n  assign accum_window_q  = imd_val_q_i[0][32:0];\n  assign unused_imd_val0 = imd_val_q_i[0][33];\n  assign imd_val_d_o[1]  = {2'b00, op_numerator_d};\n  assign imd_val_we_o[1] = multdiv_en;\n  assign op_numerator_q  = imd_val_q_i[1][31:0];\n  assign unused_imd_val1 = imd_val_q_i[1][33:32];\n  always_comb begin\n    alu_operand_a_o = accum_window_q;\n    unique case (operator_i)\n      MD_OP_MULL: begin\n        alu_operand_b_o = op_a_bw_pp;\n      end\n      MD_OP_MULH: begin\n        alu_operand_b_o = (md_state_q == MD_LAST) ? op_a_bw_last_pp : op_a_bw_pp;\n      end\n      MD_OP_DIV,\n      MD_OP_REM: begin\n        unique case (md_state_q)\n          MD_IDLE: begin\n            // 0 - B = 0 iff B == 0\n            alu_operand_a_o = {32'h0  , 1'b1};\n            alu_operand_b_o = {~op_b_i, 1'b1};\n          end\n          MD_ABS_A: begin\n            // ABS(A) = 0 - A\n            alu_operand_a_o = {32'h0  , 1'b1};\n            alu_operand_b_o = {~op_a_i, 1'b1};\n          end\n          MD_ABS_B: begin\n            // ABS(B) = 0 - B\n            alu_operand_a_o = {32'h0  , 1'b1};\n            alu_operand_b_o = {~op_b_i, 1'b1};\n          end\n          MD_CHANGE_SIGN: begin\n            // ABS(Quotient) = 0 - Quotient (or Reminder)\n            alu_operand_a_o = {32'h0  , 1'b1};\n            alu_operand_b_o = {~accum_window_q[31:0], 1'b1};\n          end\n          default: begin\n            // Division\n            alu_operand_a_o = {accum_window_q[31:0], 1'b1}; // it contains the remainder\n            alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1};  // -denominator two's compliment\n          end\n        endcase\n      end\n      default: begin\n        alu_operand_a_o = accum_window_q;\n        alu_operand_b_o = {~op_b_shift_q[31:0], 1'b1};\n      end\n    endcase\n  end\n  // Multiplier partial product calculation\n  assign b_0             = {32{op_b_shift_q[0]}};\n  assign op_a_bw_pp      = { ~(op_a_shift_q[32] & op_b_shift_q[0]),  (op_a_shift_q[31:0] & b_0) };\n  assign op_a_bw_last_pp = {  (op_a_shift_q[32] & op_b_shift_q[0]), ~(op_a_shift_q[31:0] & b_0) };\n  // Sign extend the input operands\n  assign sign_a   = op_a_i[31] & signed_mode_i[0];\n  assign sign_b   = op_b_i[31] & signed_mode_i[1];\n  assign op_a_ext = {sign_a, op_a_i};\n  assign op_b_ext = {sign_b, op_b_i};\n  // Divider calculations\n  // The adder in the ALU computes Remainder - Divisor. If Remainder - Divisor >= 0,\n  // is_greater_equal is true, the next Remainder is the subtraction result and the Quotient\n  // multdiv_count_q-th bit is set to 1.\n  assign is_greater_equal = (accum_window_q[31] == op_b_shift_q[31]) ?\n      ~res_adder_h[31] : accum_window_q[31];\n  assign one_shift      = {32'b0, 1'b1} << multdiv_count_q;\n  assign next_remainder = is_greater_equal ? res_adder_h[31:0]        : accum_window_q[31:0];\n  assign next_quotient  = is_greater_equal ? op_a_shift_q | one_shift : op_a_shift_q;\n  assign div_change_sign  = (sign_a ^ sign_b) & ~div_by_zero_q;\n  assign rem_change_sign  = sign_a;\n  always_comb begin\n    multdiv_count_d  = multdiv_count_q;\n    accum_window_d   = accum_window_q;\n    op_b_shift_d     = op_b_shift_q;\n    op_a_shift_d     = op_a_shift_q;\n    op_numerator_d   = op_numerator_q;\n    md_state_d       = md_state_q;\n    multdiv_hold     = 1'b0;\n    div_by_zero_d    = div_by_zero_q;\n    if (mult_sel_i || div_sel_i) begin\n      unique case (md_state_q)\n        MD_IDLE: begin\n          unique case (operator_i)\n            MD_OP_MULL: begin\n              op_a_shift_d   = op_a_ext << 1;\n              accum_window_d = {       ~(op_a_ext[32]   &     op_b_i[0]),\n                                         op_a_ext[31:0] & {32{op_b_i[0]}}  };\n              op_b_shift_d   = op_b_ext >> 1;\n              // Proceed with multiplication by 0/1 in data-independent time mode\n              // SEC_CM: CORE.DATA_REG_SW.SCA\n              md_state_d     = ((op_b_ext >> 1) == 0) ? MD_LAST : MD_COMP;\n            end\n            MD_OP_MULH: begin\n              op_a_shift_d   = op_a_ext;\n              accum_window_d = { 1'b1, ~(op_a_ext[32]   &     op_b_i[0]),\n                                         op_a_ext[31:1] & {31{op_b_i[0]}}  };\n              op_b_shift_d   = op_b_ext >> 1;\n              md_state_d     = MD_COMP;\n            end\n            MD_OP_DIV: begin\n              // Check if the denominator is 0\n              // quotient for division by 0 is specified to be -1\n              // Note with data-independent time option, the full divide operation will proceed as\n              // normal and will naturally return -1\n              accum_window_d = {33{1'b1}};\n              // SEC_CM: CORE.DATA_REG_SW.SCA\n              md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;\n              // Record that this is a div by zero to stop the sign change at the end of the\n              // division (in data_ind_timing mode).\n              div_by_zero_d  = equal_to_zero_i;\n            end\n            MD_OP_REM: begin\n              // Check if the denominator is 0\n              // remainder for division by 0 is specified to be the numerator (operand a)\n              // Note with data-independent time option, the full divide operation will proceed as\n              // normal and will naturally return operand a\n              accum_window_d = op_a_ext;\n              // SEC_CM: CORE.DATA_REG_SW.SCA\n              md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;\n            end\n            default:;\n          endcase\n          multdiv_count_d   = 5'd31;\n        end\n        MD_ABS_A: begin\n          // quotient\n          op_a_shift_d   = '0;\n          // A abs value\n          op_numerator_d = sign_a ? alu_adder_i : op_a_i;\n          md_state_d     = MD_ABS_B;\n        end\n        MD_ABS_B: begin\n          // remainder\n          accum_window_d = {32'h0, op_numerator_q[31]};\n          // B abs value\n          op_b_shift_d   = sign_b ? {1'b0, alu_adder_i} : {1'b0, op_b_i};\n          md_state_d     = MD_COMP;\n        end\n        MD_COMP: begin\n          multdiv_count_d = multdiv_count_q - 5'h1;\n          unique case (operator_i)\n            MD_OP_MULL: begin\n              accum_window_d = res_adder_l;\n              op_a_shift_d   = op_a_shift_q << 1;\n              op_b_shift_d   = op_b_shift_q >> 1;\n              // Multiplication is complete once op_b is zero, unless in data_ind_timing mode where\n              // the maximum possible shift-add operations will be completed regardless of op_b\n              // SEC_CM: CORE.DATA_REG_SW.SCA\n              md_state_d     = ((op_b_shift_d == 0) ||\n                                (multdiv_count_q == 5'd1)) ? MD_LAST : MD_COMP;\n            end\n            MD_OP_MULH: begin\n              accum_window_d = res_adder_h;\n              op_a_shift_d   = op_a_shift_q;\n              op_b_shift_d   = op_b_shift_q >> 1;\n              md_state_d     = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP;\n            end\n            MD_OP_DIV,\n            MD_OP_REM: begin\n              accum_window_d = {next_remainder[31:0], op_numerator_q[multdiv_count_d]};\n              op_a_shift_d   = next_quotient;\n              md_state_d     = (multdiv_count_q == 5'd1) ? MD_LAST : MD_COMP;\n            end\n            default: ;\n          endcase\n        end\n        MD_LAST: begin\n          unique case (operator_i)\n            MD_OP_MULL: begin\n              accum_window_d = res_adder_l;\n              // Note no state transition will occur if multdiv_hold is set\n              md_state_d   = MD_IDLE;\n              multdiv_hold = ~multdiv_ready_id_i;\n            end\n            MD_OP_MULH: begin\n              accum_window_d = res_adder_l;\n              md_state_d     = MD_IDLE;\n              // Note no state transition will occur if multdiv_hold is set\n              md_state_d   = MD_IDLE;\n              multdiv_hold = ~multdiv_ready_id_i;\n            end\n            MD_OP_DIV: begin\n              // this time we save the quotient in accum_window_q since we do not need anymore the\n              // remainder\n              accum_window_d = next_quotient;\n              md_state_d     = MD_CHANGE_SIGN;\n            end\n            MD_OP_REM: begin\n              // this time we do not save the quotient anymore since we need only the remainder\n              accum_window_d = {1'b0, next_remainder[31:0]};\n              md_state_d     = MD_CHANGE_SIGN;\n            end\n            default: ;\n          endcase\n        end\n        MD_CHANGE_SIGN: begin\n          md_state_d = MD_FINISH;\n          unique case (operator_i)\n            MD_OP_DIV:\n              accum_window_d = div_change_sign ? {1'b0,alu_adder_i} : accum_window_q;\n            MD_OP_REM:\n              accum_window_d = rem_change_sign ? {1'b0,alu_adder_i} : accum_window_q;\n            default: ;\n          endcase\n        end\n        MD_FINISH: begin\n          // Note no state transition will occur if multdiv_hold is set\n          md_state_d   = MD_IDLE;\n          multdiv_hold = ~multdiv_ready_id_i;\n        end\n        default: begin\n          md_state_d = MD_IDLE;\n        end\n      endcase // md_state_q\n    end // (mult_sel_i || div_sel_i)\n  end\n  //////////////////////////////////////////\n  // Mutliplier / Divider state registers //\n  //////////////////////////////////////////\n  assign multdiv_en = (mult_en_i | div_en_i) & ~multdiv_hold;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      multdiv_count_q  <= 5'h0;\n      op_b_shift_q     <= 33'h0;\n      op_a_shift_q     <= 33'h0;\n      md_state_q       <= MD_IDLE;\n      div_by_zero_q    <= 1'b0;\n    end else if (multdiv_en) begin\n      multdiv_count_q  <= multdiv_count_d;\n      op_b_shift_q     <= op_b_shift_d;\n      op_a_shift_q     <= op_a_shift_d;\n      md_state_q       <= md_state_d;\n      div_by_zero_q    <= div_by_zero_d;\n    end\n  end\n  /////////////\n  // Outputs //\n  /////////////\n  assign valid_o = (md_state_q == MD_FINISH) |\n                   (md_state_q == MD_LAST &\n                   (operator_i == MD_OP_MULL |\n                    operator_i == MD_OP_MULH));\n  assign multdiv_result_o = div_en_i ? accum_window_q[31:0] : res_adder_l[31:0];\n  ////////////////\n  // Assertions //\n  ////////////////\n  // State must be valid.\nendmodule\n", "mask_idx": {"conditional_statement": [[28548, 34336], [34597, 35025], [34794, 35025]], "blocking_assignment": [[33686, 33709], [30493, 30519], [30703, 30729], [28294, 28328], [33544, 33576], [32011, 32046], [30854, 30901], [29402, 29433]], "always_construct": [[25551, 27022], [34542, 35031], [28232, 34342]], "case_statement": [[32507, 33633], [33720, 34003], [25611, 27016], [28589, 34299], [28647, 30692], [25872, 26866], [31286, 32461]], "ansi_port_declaration": [[22940, 22971], [23526, 23563], [23566, 23607], [23825, 23869], [23370, 23409], [23872, 23914], [23009, 23087]], "continuous_assign": [[27353, 27401], [25006, 25049], [25173, 25220], [25223, 25262], [25361, 25410], [27776, 27889], [27218, 27314], [28132, 28193]], "parameter_declaration": [[16850, 16895], [16993, 17037], [13787, 13814], [16802, 16847], [16898, 16943], [16946, 16990], [13622, 13688], [16755, 16799]], "nonblocking_assignment": [[34822, 34858], [34865, 34898], [34945, 34976], [34983, 35017], [34905, 34938]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[24919, 24962], [25006, 25049], [25173, 25220], [25223, 25262], [25265, 25311], [25314, 25358], [25361, 25410], [25413, 25449], [25452, 25498], [25501, 25548], [27069, 27116], [27119, 27215], [27218, 27314], [27353, 27401], [27404, 27452], [27455, 27490], [27493, 27528], [27776, 27889], [27892, 27949], [27952, 28043], [28046, 28129], [28132, 28193], [28196, 28229], [34480, 34539], [35082, 35265], [35268, 35346]], "blocking_assignment": [[25573, 25606], [25668, 25697], [25740, 25813], [25970, 26004], [26017, 26051], [26134, 26168], [26181, 26215], [26298, 26332], [26345, 26379], [26496, 26530], [26543, 26591], [26667, 26743], [26756, 26836], [26906, 26939], [26948, 26994], [28254, 28289], [28294, 28328], [28333, 28365], [28370, 28402], [28407, 28441], [28446, 28476], [28481, 28505], [28510, 28543], [28716, 28747], [28762, 28899], [28914, 28945], [29088, 29148], [29209, 29235], [29250, 29387], [29402, 29433], [29448, 29473], [29798, 29826], [29887, 29943], [30104, 30137], [30493, 30519], [30580, 30636], [30703, 30729], [30798, 30818], [30854, 30901], [30912, 30938], [31008, 31053], [31089, 31152], [31163, 31188], [31234, 31275], [31355, 31384], [31399, 31434], [31449, 31484], [31741, 31861], [31922, 31951], [31966, 31996], [32011, 32046], [32061, 32124], [32207, 32280], [32295, 32326], [32341, 32404], [32576, 32605], [32696, 32719], [32734, 32769], [32830, 32859], [32874, 32899], [32990, 33013], [33028, 33063], [33249, 33280], [33295, 33327], [33483, 33529], [33544, 33576], [33686, 33709], [33782, 33853], [33891, 33962], [34123, 34146], [34157, 34192], [34238, 34259]], "nonblocking_assignment": [[34622, 34647], [34654, 34680], [34687, 34713], [34720, 34748], [34755, 34780], [34822, 34858], [34865, 34898], [34905, 34938], [34945, 34976], [34983, 35017]], "case_statement": [[25611, 27016], [25872, 26866], [28589, 34299], [28647, 30692], [31286, 32461], [32507, 33633], [33720, 34003]], "conditional_statement": [[28548, 34336], [34597, 35025], [34794, 35025]], "always_construct": [[25551, 27022], [28232, 34342], [34542, 35031]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096]], "ansi_port_declaration": [[22940, 22971], [22974, 23006], [23009, 23087], [23090, 23168], [23171, 23248], [23251, 23328], [23331, 23367], [23370, 23409], [23412, 23444], [23447, 23479], [23482, 23523], [23526, 23563], [23566, 23607], [23610, 23651], [23654, 23695], [23698, 23738], [23741, 23781], [23784, 23822], [23825, 23869], [23872, 23914], [23917, 23949]]}}
{"sample_i": "p11", "topmodule": "cve2_pmp", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// The CVE2 does not officially support Physical Memory Protection (PMP), as \n// defined by rule PVL-40 of the CV32E20 core functional requirements.\nmodule cve2_pmp #(\n  // Granularity of NAPOT access,\n  // 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.\n  parameter int unsigned PMPGranularity = 0,\n  // Number of access channels (e.g. i-side + d-side)\n  parameter int unsigned PMPNumChan     = 2,\n  // Number of implemented regions\n  parameter int unsigned PMPNumRegions  = 4\n) (\n  // Clock and Reset\n  input  logic                    clk_i,\n  input  logic                    rst_ni,\n  // Interface to CSRs\n  input  cve2_pkg::pmp_cfg_t      csr_pmp_cfg_i     [PMPNumRegions],\n  input  logic [33:0]             csr_pmp_addr_i    [PMPNumRegions],\n  input  cve2_pkg::pmp_mseccfg_t  csr_pmp_mseccfg_i,\n  input  cve2_pkg::priv_lvl_e     priv_mode_i    [PMPNumChan],\n  // Access checking channels\n  input  logic [33:0]             pmp_req_addr_i [PMPNumChan],\n  input  cve2_pkg::pmp_req_e      pmp_req_type_i [PMPNumChan],\n  output logic                    pmp_req_err_o  [PMPNumChan]\n);\n  import cve2_pkg::*;\n  // Access Checking Signals\n  logic [33:0]                                region_start_addr [PMPNumRegions];\n  logic [33:PMPGranularity+2]                 region_addr_mask  [PMPNumRegions];\n  logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_match_gt;\n  logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_match_lt;\n  logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_match_eq;\n  logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_match_all;\n  logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_basic_perm_check;\n  logic [PMPNumChan-1:0][PMPNumRegions-1:0]   region_mml_perm_check;\n  logic [PMPNumChan-1:0]                      access_fault;\n  $warning(\"CVE2 does not officially support PMP, see rule PVL-40.\");\n  // ---------------\n  // Access checking\n  // ---------------\n  for (genvar r = 0; r < PMPNumRegions; r++) begin : g_addr_exp\n    // Start address for TOR matching\n    if (r == 0) begin : g_entry0\n      assign region_start_addr[r] = (csr_pmp_cfg_i[r].mode == PMP_MODE_TOR) ? 34'h000000000 :\n                                                                              csr_pmp_addr_i[r];\n    end else begin : g_oth\n      assign region_start_addr[r] = (csr_pmp_cfg_i[r].mode == PMP_MODE_TOR) ? csr_pmp_addr_i[r-1] :\n                                                                              csr_pmp_addr_i[r];\n    end\n    // Address mask for NA matching\n    for (genvar b = PMPGranularity + 2; b < 34; b++) begin : g_bitmask\n      if (b == 2) begin : g_bit0\n        // Always mask bit 2 for NAPOT\n        assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT);\n      end else begin : g_others\n        // We will mask this bit if it is within the programmed granule\n        // i.e. addr = yyyy 0111\n        //                  ^\n        //                  | This bit pos is the top of the mask, all lower bits set\n        // thus mask = 1111 0000\n        if (PMPGranularity == 0) begin : g_region_addr_mask_zero_granularity\n          assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT) |\n                                          ~&csr_pmp_addr_i[r][b-1:2];\n        end else begin : g_region_addr_mask_other_granularity\n          assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT) |\n                                          ~&csr_pmp_addr_i[r][b-1:PMPGranularity+1];\n        end\n      end\n    end\n  end\n  for (genvar c = 0; c < PMPNumChan; c++) begin : g_access_check\n    for (genvar r = 0; r < PMPNumRegions; r++) begin : g_regions\n      // Comparators are sized according to granularity\n      assign region_match_eq[c][r] = (pmp_req_addr_i[c][33:PMPGranularity+2] &\n                                      region_addr_mask[r]) ==\n                                     (region_start_addr[r][33:PMPGranularity+2] &\n                                      region_addr_mask[r]);\n      assign region_match_gt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] >\n                                     region_start_addr[r][33:PMPGranularity+2];\n      assign region_match_lt[c][r] = pmp_req_addr_i[c][33:PMPGranularity+2] <\n                                     csr_pmp_addr_i[r][33:PMPGranularity+2];\n      always_comb begin\n        region_match_all[c][r] = 1'b0;\n        unique case (csr_pmp_cfg_i[r].mode)\n          PMP_MODE_OFF:   region_match_all[c][r] = 1'b0;\n          PMP_MODE_NA4:   region_match_all[c][r] = region_match_eq[c][r];\n          PMP_MODE_NAPOT: region_match_all[c][r] = region_match_eq[c][r];\n          PMP_MODE_TOR: begin\n            region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &\n                                     region_match_lt[c][r];\n          end\n          default:        region_match_all[c][r] = 1'b0;\n        endcase\n      end\n      // Check specific required permissions\n      assign region_basic_perm_check[c][r] =\n          ((pmp_req_type_i[c] == PMP_ACC_EXEC)  & csr_pmp_cfg_i[r].exec) |\n          ((pmp_req_type_i[c] == PMP_ACC_WRITE) & csr_pmp_cfg_i[r].write) |\n          ((pmp_req_type_i[c] == PMP_ACC_READ)  & csr_pmp_cfg_i[r].read);\n      // Compute permission checks that apply when MSECCFG.MML is set.\n      always_comb begin\n        region_mml_perm_check[c][r] = 1'b0;\n        if (!csr_pmp_cfg_i[r].read && csr_pmp_cfg_i[r].write) begin\n          // Special-case shared regions where R = 0, W = 1\n          unique case ({csr_pmp_cfg_i[r].lock, csr_pmp_cfg_i[r].exec})\n            // Read/write in M, read only in S/U\n            2'b00: region_mml_perm_check[c][r] =\n                (pmp_req_type_i[c] == PMP_ACC_READ) |\n                ((pmp_req_type_i[c] == PMP_ACC_WRITE) & (priv_mode_i[c] == PRIV_LVL_M));\n            // Read/write in M/S/U\n            2'b01: region_mml_perm_check[c][r] =\n                (pmp_req_type_i[c] == PMP_ACC_READ) | (pmp_req_type_i[c] == PMP_ACC_WRITE);\n            // Execute only on M/S/U\n            2'b10: region_mml_perm_check[c][r] = (pmp_req_type_i[c] == PMP_ACC_EXEC);\n            // Read/execute in M, execute only on S/U\n            2'b11: region_mml_perm_check[c][r] =\n                (pmp_req_type_i[c] == PMP_ACC_EXEC) |\n                ((pmp_req_type_i[c] == PMP_ACC_READ) & (priv_mode_i[c] == PRIV_LVL_M));\n            default: ;\n          endcase\n        end else begin\n          if (csr_pmp_cfg_i[r].read & csr_pmp_cfg_i[r].write & csr_pmp_cfg_i[r].exec\n              & csr_pmp_cfg_i[r].lock) begin\n            // Special-case shared read only region when R = 1, W = 1, X = 1, L = 1\n            region_mml_perm_check[c][r] = pmp_req_type_i[c] == PMP_ACC_READ;\n          end else begin\n            // Otherwise use basic permission check. Permission is always denied if in S/U mode and\n            // L is set or if in M mode and L is unset.\n            region_mml_perm_check[c][r] =\n              priv_mode_i[c] == PRIV_LVL_M ? csr_pmp_cfg_i[r].lock & region_basic_perm_check[c][r] :\n                                            ~csr_pmp_cfg_i[r].lock & region_basic_perm_check[c][r];\n          end\n        end\n      end\n    end\n    // Access fault determination / prioritization\n    always_comb begin\n      // When MSECCFG.MMWP is set default deny always, otherwise allow for M-mode, deny for other\n      // modes\n      access_fault[c] = csr_pmp_mseccfg_i.mmwp | (priv_mode_i[c] != PRIV_LVL_M);\n      // PMP entries are statically prioritized, from 0 to N-1\n      // The lowest-numbered PMP entry which matches an address determines accessability\n      for (int r = PMPNumRegions - 1; r >= 0; r--) begin\n        if (region_match_all[c][r]) begin\n          if (csr_pmp_mseccfg_i.mml) begin\n            // When MSECCFG.MML is set use MML specific permission check\n            access_fault[c] = ~region_mml_perm_check[c][r];\n          end else begin\n            // Otherwise use original PMP behaviour\n            access_fault[c] = (priv_mode_i[c] == PRIV_LVL_M) ?\n                // For M-mode, any region which matches with the L-bit clear, or with sufficient\n                // access permissions will be allowed\n                (csr_pmp_cfg_i[r].lock & ~region_basic_perm_check[c][r]) :\n                // For other modes, the lock bit doesn't matter\n                ~region_basic_perm_check[c][r];\n          end\n        end\n      end\n    end\n    assign pmp_req_err_o[c] = access_fault[c];\n  end\n  // RLB, rule locking bypass, is only relevant to cve2_cs_registers which controls writes to the\n  // PMP CSRs. Tie to unused signal here to prevent lint warnings.\n  logic unused_csr_pmp_mseccfg_rlb;\n  assign unused_csr_pmp_mseccfg_rlb = csr_pmp_mseccfg_i.rlb;\nendmodule\n", "mask_idx": {"conditional_statement": [[26079, 26736], [23752, 25532], [24802, 25520], [26035, 26748]], "blocking_assignment": [[25018, 25082], [24556, 24727], [22968, 23015], [24011, 24183], [22736, 22766], [22894, 22941], [23708, 23743], [25743, 25817]], "always_construct": [[25606, 26766], [23682, 25542], [22710, 23289]], "case_statement": [[23882, 24768], [22775, 23279]], "ansi_port_declaration": [[18977, 19016], [19326, 19386], [19180, 19230], [19452, 19511], [18936, 18974], [19389, 19449], [19111, 19177]], "continuous_assign": [[22114, 22390], [22397, 22548], [23341, 23604], [26771, 26813], [21059, 21133], [27023, 27081], [20455, 20639], [20673, 20863]], "parameter_declaration": [[13332, 13380], [6668, 6702], [12464, 12546], [12680, 12733], [12736, 12789], [13092, 13137], [6471, 6520], [13622, 13688], [12379, 12461], [6631, 6665]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[20455, 20639], [20673, 20863], [21059, 21133], [21507, 21652], [21725, 21885], [22114, 22390], [22397, 22548], [22555, 22703], [23341, 23604], [26771, 26813], [27023, 27081]], "blocking_assignment": [[22736, 22766], [22837, 22867], [22894, 22941], [22968, 23015], [23058, 23192], [23233, 23263], [23708, 23743], [24011, 24183], [24238, 24359], [24416, 24482], [24556, 24727], [25018, 25082], [25276, 25506], [25743, 25817], [26197, 26244], [26334, 26722]], "nonblocking_assignment": [], "case_statement": [[22775, 23279], [23882, 24768]], "conditional_statement": [[23752, 25532], [24802, 25520], [26035, 26748], [26079, 26736]], "always_construct": [[22710, 23289], [23682, 25542], [25606, 26766]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096], [18688, 18730], [18787, 18829], [18867, 18908]], "ansi_port_declaration": [[18936, 18974], [18977, 19016], [19042, 19108], [19111, 19177], [19180, 19230], [19233, 19293], [19326, 19386], [19389, 19449], [19452, 19511]]}}
{"sample_i": "p12", "topmodule": "cve2_prefetch_buffer", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Fetch Fifo for 32 bit memory interface\n *\n * input port: send address and data to the FIFO\n * clear_i clears the FIFO for the following cycle, including any new request\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_fetch_fifo #(\n  parameter int unsigned NUM_REQS = 2\n) (\n  input  logic                clk_i,\n  input  logic                rst_ni,\n  // control signals\n  input  logic                clear_i,   // clears the contents of the FIFO\n  output logic [NUM_REQS-1:0] busy_o,\n  // input port\n  input  logic                in_valid_i,\n  input  logic [31:0]         in_addr_i,\n  input  logic [31:0]         in_rdata_i,\n  input  logic                in_err_i,\n  // output port\n  output logic                out_valid_o,\n  input  logic                out_ready_i,\n  output logic [31:0]         out_addr_o,\n  output logic [31:0]         out_rdata_o,\n  output logic                out_err_o,\n  output logic                out_err_plus2_o\n);\n  localparam int unsigned DEPTH = NUM_REQS+1;\n  // index 0 is used for output\n  logic [DEPTH-1:0] [31:0]  rdata_d,   rdata_q;\n  logic [DEPTH-1:0]         err_d,     err_q;\n  logic [DEPTH-1:0]         valid_d,   valid_q;\n  logic [DEPTH-1:0]         lowest_free_entry;\n  logic [DEPTH-1:0]         valid_pushed, valid_popped;\n  logic [DEPTH-1:0]         entry_en;\n  logic                     pop_fifo;\n  logic             [31:0]  rdata, rdata_unaligned;\n  logic                     err,   err_unaligned, err_plus2;\n  logic                     valid, valid_unaligned;\n  logic                     aligned_is_compressed, unaligned_is_compressed;\n  logic                     addr_incr_two;\n  logic [31:1]              instr_addr_next;\n  logic [31:1]              instr_addr_d, instr_addr_q;\n  logic                     instr_addr_en;\n  logic                     unused_addr_in;\n  /////////////////\n  // Output port //\n  /////////////////\n  assign rdata = valid_q[0] ? rdata_q[0] : in_rdata_i;\n  assign err   = valid_q[0] ? err_q[0]   : in_err_i;\n  assign valid = valid_q[0] | in_valid_i;\n  // The FIFO contains word aligned memory fetches, but the instructions contained in each entry\n  // might be half-word aligned (due to compressed instructions)\n  // e.g.\n  //              | 31               16 | 15               0 |\n  // FIFO entry 0 | Instr 1 [15:0]      | Instr 0 [15:0]     |\n  // FIFO entry 1 | Instr 2 [15:0]      | Instr 1 [31:16]    |\n  //\n  // The FIFO also has a direct bypass path, so a complete instruction might be made up of data\n  // from the FIFO and new incoming data.\n  //\n  // Construct the output data for an unaligned instruction\n  assign rdata_unaligned = valid_q[1] ? {rdata_q[1][15:0], rdata[31:16]} :\n                                        {in_rdata_i[15:0], rdata[31:16]};\n  // If entry[1] is valid, an error can come from entry[0] or entry[1], unless the\n  // instruction in entry[0] is compressed (entry[1] is a new instruction)\n  // If entry[1] is not valid, and entry[0] is, an error can come from entry[0] or the incoming\n  // data, unless the instruction in entry[0] is compressed\n  // If entry[0] is not valid, the error must come from the incoming data\n  assign err_unaligned   = valid_q[1] ? ((err_q[1] & ~unaligned_is_compressed) | err_q[0]) :\n                                        ((valid_q[0] & err_q[0]) |\n                                         (in_err_i & (~valid_q[0] | ~unaligned_is_compressed)));\n  // Record when an error is caused by the second half of an unaligned 32bit instruction.\n  // Only needs to be correct when unaligned and if err_unaligned is set\n  assign err_plus2       = valid_q[1] ? (err_q[1] & ~err_q[0]) :\n                                        (in_err_i & valid_q[0] & ~err_q[0]);\n  // An uncompressed unaligned instruction is only valid if both parts are available\n  assign valid_unaligned = valid_q[1] ? 1'b1 :\n                                        (valid_q[0] & in_valid_i);\n  // If there is an error, rdata is unknown\n  assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err;\n  assign aligned_is_compressed   = (rdata[ 1: 0] != 2'b11) & ~err;\n  ////////////////////////////////////////\n  // Instruction aligner (if unaligned) //\n  ////////////////////////////////////////\n  always_comb begin\n    if (out_addr_o[1]) begin\n      // unaligned case\n      out_rdata_o     = rdata_unaligned;\n      out_err_o       = err_unaligned;\n      out_err_plus2_o = err_plus2;\n      if (unaligned_is_compressed) begin\n        out_valid_o = valid;\n      end else begin\n        out_valid_o = valid_unaligned;\n      end\n    end else begin\n      // aligned case\n      out_rdata_o     = rdata;\n      out_err_o       = err;\n      out_err_plus2_o = 1'b0;\n      out_valid_o     = valid;\n    end\n  end\n  /////////////////////////\n  // Instruction address //\n  /////////////////////////\n  // Update the address on branches and every time an instruction is driven\n  assign instr_addr_en = clear_i | (out_ready_i & out_valid_o);\n  // Increment the address by two every time a compressed instruction is popped\n  assign addr_incr_two = instr_addr_q[1] ? unaligned_is_compressed :\n                                           aligned_is_compressed;\n  assign instr_addr_next = (instr_addr_q[31:1] +\n                            // Increment address by 4 or 2\n                            {29'd0,~addr_incr_two,addr_incr_two});\n  assign instr_addr_d = clear_i ? in_addr_i[31:1] :\n                                  instr_addr_next;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      instr_addr_q <= '0;\n    end else if (instr_addr_en) begin\n      instr_addr_q <= instr_addr_d;\n    end\n  end\n  // Output PC of current instruction\n  assign out_addr_o      = {instr_addr_q, 1'b0};\n  // The LSB of the address is unused, since all addresses are halfword aligned\n  assign unused_addr_in = in_addr_i[0];\n  /////////////////\n  // FIFO status //\n  /////////////////\n  // Indicate the fill level of fifo-entries. This is used to determine when a new request can be\n  // made on the bus. The prefetch buffer only needs to know about the upper entries which overlap\n  // with NUM_REQS.\n  assign busy_o = valid_q[DEPTH-1:DEPTH-NUM_REQS];\n  /////////////////////\n  // FIFO management //\n  /////////////////////\n  // Since an entry can contain unaligned instructions, popping an entry can leave the entry valid\n  assign pop_fifo = out_ready_i & out_valid_o & (~aligned_is_compressed | out_addr_o[1]);\n  for (genvar i = 0; i < (DEPTH - 1); i++) begin : g_fifo_next\n    // Calculate lowest free entry (write pointer)\n    if (i == 0) begin : g_ent0\n      assign lowest_free_entry[i] = ~valid_q[i];\n    end else begin : g_ent_others\n      assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i-1];\n    end\n    // An entry is set when an incoming request chooses the lowest available entry\n    assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) |\n                             valid_q[i];\n    // Popping the FIFO shifts all entries down\n    assign valid_popped[i] = pop_fifo ? valid_pushed[i+1] : valid_pushed[i];\n    // All entries are wiped out on a clear\n    assign valid_d[i] = valid_popped[i] & ~clear_i;\n    // data flops are enabled if there is new data to shift into it, or\n    assign entry_en[i] = (valid_pushed[i+1] & pop_fifo) |\n                         // a new request is incoming and this is the lowest free entry\n                         (in_valid_i & lowest_free_entry[i] & ~pop_fifo);\n    // take the next entry or the incoming data\n    assign rdata_d[i]  = valid_q[i+1] ? rdata_q[i+1] : in_rdata_i;\n    assign err_d  [i]  = valid_q[i+1] ? err_q  [i+1] : in_err_i;\n  end\n  // The top entry is similar but with simpler muxing\n  assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & valid_q[DEPTH-2];\n  assign valid_pushed     [DEPTH-1] = valid_q[DEPTH-1] | (in_valid_i & lowest_free_entry[DEPTH-1]);\n  assign valid_popped     [DEPTH-1] = pop_fifo ? 1'b0 : valid_pushed[DEPTH-1];\n  assign valid_d [DEPTH-1]          = valid_popped[DEPTH-1] & ~clear_i;\n  assign entry_en[DEPTH-1]          = in_valid_i & lowest_free_entry[DEPTH-1];\n  assign rdata_d [DEPTH-1]          = in_rdata_i;\n  assign err_d   [DEPTH-1]          = in_err_i;\n  ////////////////////\n  // FIFO registers //\n  ////////////////////\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      valid_q <= '0;\n    end else begin\n      valid_q <= valid_d;\n    end\n  end\n  for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs\n      always_ff @(posedge clk_i or negedge rst_ni) begin\n        if (!rst_ni) begin\n          rdata_q[i] <= '0;\n          err_q[i]   <= '0;\n        end else if (entry_en[i]) begin\n          rdata_q[i] <= rdata_d[i];\n          err_q[i]   <= err_d[i];\n        end\n      end\n  end\n  ////////////////\n  // Assertions //\n  ////////////////\n  // Must not push and pop simultaneously when FIFO full.\n  // Must not push to FIFO when full.\nendmodule\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Prefetcher Buffer for 32 bit memory interface\n *\n * Prefetch Buffer that caches instructions. This cuts overly long critical\n * paths to the instruction cache.\n */\nmodule cve2_prefetch_buffer #(\n) (\n  input  logic        clk_i,\n  input  logic        rst_ni,\n  input  logic        req_i,\n  input  logic        branch_i,\n  input  logic [31:0] addr_i,\n  input  logic        ready_i,\n  output logic        valid_o,\n  output logic [31:0] rdata_o,\n  output logic [31:0] addr_o,\n  output logic        err_o,\n  output logic        err_plus2_o,\n  // goes to instruction memory / instruction cache\n  output logic        instr_req_o,\n  input  logic        instr_gnt_i,\n  output logic [31:0] instr_addr_o,\n  input  logic [31:0] instr_rdata_i,\n  input  logic        instr_err_i,\n  input  logic        instr_rvalid_i,\n  // Prefetch Buffer Status\n  output logic        busy_o\n);\n  localparam int unsigned NUM_REQS  = 2;\n  logic                valid_new_req, valid_req;\n  logic                valid_req_d, valid_req_q;\n  logic                discard_req_d, discard_req_q;\n  logic [NUM_REQS-1:0] rdata_outstanding_n, rdata_outstanding_s, rdata_outstanding_q;\n  logic [NUM_REQS-1:0] branch_discard_n, branch_discard_s, branch_discard_q;\n  logic [NUM_REQS-1:0] rdata_outstanding_rev;\n  logic [31:0]         stored_addr_d, stored_addr_q;\n  logic                stored_addr_en;\n  logic [31:0]         fetch_addr_d, fetch_addr_q;\n  logic                fetch_addr_en;\n  logic [31:0]         instr_addr, instr_addr_w_aligned;\n  logic                fifo_valid;\n  logic [31:0]         fifo_addr;\n  logic                fifo_ready;\n  logic                fifo_clear;\n  logic [NUM_REQS-1:0] fifo_busy;\n  logic                valid_raw;\n  ////////////////////////////\n  // Prefetch buffer status //\n  ////////////////////////////\n  assign busy_o = (|rdata_outstanding_q) | instr_req_o;\n  //////////////////////////////////////////////\n  // Fetch fifo - consumes addresses and data //\n  //////////////////////////////////////////////\n  // A branch will invalidate any previously fetched instructions.\n  // Note that the FENCE.I instruction relies on this flushing behaviour on branch. If it is\n  // altered the FENCE.I implementation may require changes.\n  assign fifo_clear = branch_i;\n  // Reversed version of rdata_outstanding_q which can be overlaid with fifo fill state\n  for (genvar i = 0; i < NUM_REQS; i++) begin : gen_rd_rev\n    assign rdata_outstanding_rev[i] = rdata_outstanding_q[NUM_REQS-1-i];\n  end\n  // The fifo is ready to accept a new request if it is not full - including space reserved for\n  // requests already outstanding.\n  // Overlay the fifo fill state with the outstanding requests to see if there is space.\n  assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev);\n  cve2_fetch_fifo #(\n    .NUM_REQS (NUM_REQS)\n  ) fifo_i (\n      .clk_i                 ( clk_i             ),\n      .rst_ni                ( rst_ni            ),\n      .clear_i               ( fifo_clear        ),\n      .busy_o                ( fifo_busy         ),\n      .in_valid_i            ( fifo_valid        ),\n      .in_addr_i             ( fifo_addr         ),\n      .in_rdata_i            ( instr_rdata_i     ),\n      .in_err_i              ( instr_err_i       ),\n      .out_valid_o           ( valid_raw         ),\n      .out_ready_i           ( ready_i           ),\n      .out_rdata_o           ( rdata_o           ),\n      .out_addr_o            ( addr_o            ),\n      .out_err_o             ( err_o             ),\n      .out_err_plus2_o       ( err_plus2_o       )\n  );\n  //////////////\n  // Requests //\n  //////////////\n  // Make a new request any time there is space in the FIFO, and space in the request queue\n  assign valid_new_req = req_i & (fifo_ready | branch_i) &\n                         ~rdata_outstanding_q[NUM_REQS-1];\n  assign valid_req = valid_req_q | valid_new_req;\n  // Hold the request stable for requests that didn't get granted\n  assign valid_req_d = valid_req & ~instr_gnt_i;\n  // Record whether an outstanding bus request is cancelled by a branch\n  assign discard_req_d = valid_req_q & (branch_i | discard_req_q);\n  ////////////////\n  // Fetch addr //\n  ////////////////\n  // Two addresses are tracked in the prefetch buffer:\n  // 1. stored_addr_q - This is the address issued on the bus. It stays stable until\n  //                    the request is granted.\n  // 2. fetch_addr_q  - This is our next address to fetch from. It is updated on branches to\n  //                    capture the new address, and then for each new request issued.\n  // A third address is tracked in the fetch FIFO itself:\n  // 3. instr_addr_q  - This is the address at the head of the FIFO, efectively our oldest fetched\n  //                    address. This address is updated on branches, and does its own increment\n  //                    each time the FIFO is popped.\n  // 1. stored_addr_q\n  // Only update stored_addr_q for new ungranted requests\n  assign stored_addr_en = valid_new_req & ~valid_req_q & ~instr_gnt_i;\n  // Store whatever address was issued on the bus\n  assign stored_addr_d = instr_addr;\n  // CPU resets with a branch, so no need to reset these addresses\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      stored_addr_q <= '0;\n    end else if (stored_addr_en) begin\n      stored_addr_q <= stored_addr_d;\n    end\n  end\n  // 2. fetch_addr_q\n  // Update on a branch or as soon as a request is issued\n  assign fetch_addr_en = branch_i | (valid_new_req & ~valid_req_q);\n  assign fetch_addr_d = (branch_i            ? addr_i :\n                                               {fetch_addr_q[31:2], 2'b00}) +\n                        // Current address + 4\n                        {{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00};\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      fetch_addr_q <= '0;\n    end else if (fetch_addr_en) begin\n      fetch_addr_q <= fetch_addr_d;\n    end\n  end\n  // Address mux\n  assign instr_addr = valid_req_q         ? stored_addr_q :\n                      branch_i            ? addr_i :\n                                            fetch_addr_q;\n  assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};\n  ///////////////////////////////\n  // Request outstanding queue //\n  ///////////////////////////////\n  for (genvar i = 0; i < NUM_REQS; i++) begin : g_outstanding_reqs\n    // Request 0 (always the oldest outstanding request)\n    if (i == 0) begin : g_req0\n      // A request becomes outstanding once granted, and is cleared once the rvalid is received.\n      // Outstanding requests shift down the queue towards entry 0.\n      assign rdata_outstanding_n[i] = (valid_req & instr_gnt_i) |\n                                      rdata_outstanding_q[i];\n      // If a branch is received at any point while a request is outstanding, it must be tracked\n      // to ensure we discard the data once received\n      assign branch_discard_n[i]    = (valid_req & instr_gnt_i & discard_req_d) |\n                                      (branch_i & rdata_outstanding_q[i]) |\n                                      branch_discard_q[i];\n    end else begin : g_reqtop\n    // Entries > 0 consider the FIFO fill state to calculate their next state (by checking\n    // whether the previous entry is valid)\n      assign rdata_outstanding_n[i] = (valid_req & instr_gnt_i &\n                                       rdata_outstanding_q[i-1]) |\n                                      rdata_outstanding_q[i];\n      assign branch_discard_n[i]    = (valid_req & instr_gnt_i & discard_req_d &\n                                       rdata_outstanding_q[i-1]) |\n                                      (branch_i & rdata_outstanding_q[i]) |\n                                      branch_discard_q[i];\n    end\n  end\n  // Shift the entries down on each instr_rvalid_i\n  assign rdata_outstanding_s = instr_rvalid_i ? {1'b0,rdata_outstanding_n[NUM_REQS-1:1]} :\n                                                rdata_outstanding_n;\n  assign branch_discard_s    = instr_rvalid_i ? {1'b0,branch_discard_n[NUM_REQS-1:1]} :\n                                                branch_discard_n;\n  // Push a new entry to the FIFO once complete (and not cancelled by a branch)\n  assign fifo_valid = instr_rvalid_i & ~branch_discard_q[0];\n  assign fifo_addr = addr_i;\n  ///////////////\n  // Registers //\n  ///////////////\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      valid_req_q          <= 1'b0;\n      discard_req_q        <= 1'b0;\n      rdata_outstanding_q  <= 'b0;\n      branch_discard_q     <= 'b0;\n    end else begin\n      valid_req_q          <= valid_req_d;\n      discard_req_q        <= discard_req_d;\n      rdata_outstanding_q  <= rdata_outstanding_s;\n      branch_discard_q     <= branch_discard_s;\n    end\n  end\n  /////////////\n  // Outputs //\n  /////////////\n  assign instr_req_o  = valid_req;\n  assign instr_addr_o = instr_addr_w_aligned;\n  assign valid_o = valid_raw;\nendmodule\n", "mask_idx": {"conditional_statement": [[19537, 19663], [19595, 19663], [10106, 10174], [8964, 9097], [10048, 10174], [18999, 19070], [12851, 12943], [18940, 19070], [13164, 13268]], "blocking_assignment": [[8890, 8922], [9057, 9087], [9205, 9228], [8849, 8883], [9007, 9027], [9176, 9198], [8929, 8957], [9145, 9169]], "module_program_interface_instantiation": [[16491, 17279]], "always_construct": [[18885, 19076], [8772, 9273], [12796, 12949], [22081, 22516], [9993, 10180], [13013, 13278], [19482, 19669]], "ansi_port_declaration": [[5157, 5196], [5074, 5113], [4848, 4882], [14419, 14453], [5468, 5511], [4885, 4920], [14136, 14164]], "continuous_assign": [[6503, 6553], [17780, 17844], [15528, 15581], [21998, 22024], [12100, 12160], [17425, 17540], [20623, 20833], [11520, 11592], [9715, 9887]], "parameter_declaration": [[4806, 4841]], "nonblocking_assignment": [[13233, 13256], [19626, 19655], [22410, 22454], [19031, 19062], [22322, 22358], [13197, 13222], [22365, 22403], [10137, 10166], [12916, 12935], [22461, 22502]]}, "all_mask_idx": {"module_program_interface_instantiation": [[16491, 17279]], "continuous_assign": [[6448, 6500], [6503, 6553], [6556, 6595], [7167, 7313], [7704, 7958], [8124, 8263], [8351, 8462], [8509, 8573], [8576, 8640], [9436, 9497], [9580, 9712], [9715, 9887], [9890, 9990], [10221, 10267], [10350, 10387], [10667, 10715], [10889, 10976], [11128, 11170], [11211, 11268], [11364, 11467], [11520, 11592], [11641, 11688], [11765, 11980], [12033, 12095], [12100, 12160], [12223, 12296], [12299, 12396], [12399, 12475], [12478, 12547], [12550, 12626], [12629, 12676], [12679, 12724], [15528, 15581], [15952, 15981], [16133, 16201], [16430, 16488], [17425, 17540], [17543, 17590], [17659, 17705], [17780, 17844], [18660, 18728], [18781, 18815], [19158, 19223], [19226, 19479], [19689, 19857], [19860, 19916], [20345, 20466], [20623, 20833], [21005, 21192], [21199, 21475], [21543, 21700], [21703, 21854], [21937, 21995], [21998, 22024], [22567, 22599], [22602, 22645], [22648, 22675]], "blocking_assignment": [[8849, 8883], [8890, 8922], [8929, 8957], [9007, 9027], [9057, 9087], [9145, 9169], [9176, 9198], [9205, 9228], [9235, 9259]], "nonblocking_assignment": [[10073, 10092], [10137, 10166], [12876, 12890], [12916, 12935], [13101, 13118], [13129, 13146], [13197, 13222], [13233, 13256], [18965, 18985], [19031, 19062], [19562, 19581], [19626, 19655], [22161, 22190], [22197, 22226], [22233, 22261], [22268, 22296], [22322, 22358], [22365, 22403], [22410, 22454], [22461, 22502]], "case_statement": [], "conditional_statement": [[8794, 9267], [8964, 9097], [10048, 10174], [10106, 10174], [12851, 12943], [13072, 13268], [13164, 13268], [18940, 19070], [18999, 19070], [19537, 19663], [19595, 19663], [22136, 22510]], "always_construct": [[8772, 9273], [9993, 10180], [12796, 12949], [13013, 13278], [18885, 19076], [19482, 19669], [22081, 22516]], "parameter_declaration": [[4806, 4841]], "ansi_port_declaration": [[4848, 4882], [4885, 4920], [4944, 5017], [5020, 5055], [5074, 5113], [5116, 5154], [5157, 5196], [5199, 5236], [5256, 5296], [5299, 5339], [5342, 5381], [5384, 5424], [5427, 5465], [5468, 5511], [13924, 13950], [13953, 13980], [13983, 14009], [14012, 14041], [14044, 14071], [14074, 14102], [14105, 14133], [14136, 14164], [14167, 14194], [14197, 14223], [14226, 14258], [14313, 14345], [14348, 14380], [14383, 14416], [14419, 14453], [14456, 14488], [14491, 14526], [14557, 14583]]}}
{"sample_i": "p13", "topmodule": "cve2_wb", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Writeback passthrough\n *\n * The writeback stage is not present therefore this module acts as\n * a simple passthrough to write data direct to the register file.\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Include FCOV RTL by default. Disable it for synthesis and where explicitly requested (by defining\n// DV_FCOV_DISABLE).\n// Disable instantiations of FCOV coverpoints or covergroups.\n// Instantiates a covergroup in an interface or module.\n//\n// This macro assumes that a covergroup of the same name as the NAME_ arg is defined in the\n// interface or module. It just adds some extra signals and logic to control the creation of the\n// covergroup instance with ~bit en_<cg_name>~. This defaults to 0. It is ORed with the external\n// COND_ signal. The testbench can modify it at t = 0 based on the test being run.\n// NOTE: This is not meant to be invoked inside a class.\n//\n// NAME_ : Name of the covergroup.\n// COND_ : External condition / expr that controls the creation of the covergroup.\n// ARGS_ : Arguments to covergroup instance, if any. Args MUST BE wrapped in (..).\n// Creates a coverpoint for an expression where only the expression true case is of interest for\n// coverage (e.g. where the expression indicates an event has occured).\n// Creates a SVA cover that can be used in a covergroup.\n//\n// This macro creates an unnamed SVA cover from the property (or an expression) `PROP_` and an event\n// with the name `EV_NAME_`. When the SVA cover is hit, the event is triggered. A coverpoint can\n// cover the `triggered` property of the event.\n// Coverage support is not always available but it's useful to include extra fcov signals for\n// linting purposes. They need to be marked as unused to avoid warnings.\n// Define a signal and expression in the design for capture in functional coverage\n// Define a signal and expression in the design for capture in functional coverage depending on\n// design configuration. The input GEN_COND_ must be a constant or parameter.\nmodule cve2_wb #(\n) (\n  input  logic                     clk_i,\n  input  logic                     rst_ni,\n  input  logic                     en_wb_i,\n  input  logic                     instr_is_compressed_id_i,\n  input  logic                     instr_perf_count_id_i,\n  output logic                     perf_instr_ret_wb_o,\n  output logic                     perf_instr_ret_compressed_wb_o,\n  input  logic [4:0]               rf_waddr_id_i,\n  input  logic [31:0]              rf_wdata_id_i,\n  input  logic                     rf_we_id_i,\n  input  logic [31:0]              rf_wdata_lsu_i,\n  input  logic                     rf_we_lsu_i,\n  output logic [4:0]               rf_waddr_wb_o,\n  output logic [31:0]              rf_wdata_wb_o,\n  output logic                     rf_we_wb_o,\n  input logic                      lsu_resp_valid_i,\n  input logic                      lsu_resp_err_i\n);\n  import cve2_pkg::*;\n  // 0 == RF write from ID\n  // 1 == RF write from LSU\n  logic [31:0] rf_wdata_wb_mux    [2];\n  logic [1:0]  rf_wdata_wb_mux_we;\n    // without writeback stage just pass through register write signals\n    assign rf_waddr_wb_o         = rf_waddr_id_i;\n    assign rf_wdata_wb_mux[0]    = rf_wdata_id_i;\n    assign rf_wdata_wb_mux_we[0] = rf_we_id_i;\n    // Increment instruction retire counters for valid instructions which are not lsu errors.\n    assign perf_instr_ret_wb_o                 = instr_perf_count_id_i & en_wb_i &\n                                                 ~(lsu_resp_valid_i & lsu_resp_err_i);\n    assign perf_instr_ret_compressed_wb_o      = perf_instr_ret_wb_o & instr_is_compressed_id_i;\n  assign rf_wdata_wb_mux[1]    = rf_wdata_lsu_i;\n  assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;\n  // RF write data can come from ID results (all RF writes that aren't because of loads will come\n  // from here) or the LSU (RF writes for load data)\n  assign rf_wdata_wb_o = ({32{rf_wdata_wb_mux_we[0]}} & rf_wdata_wb_mux[0]) |\n                         ({32{rf_wdata_wb_mux_we[1]}} & rf_wdata_wb_mux[1]);\n  assign rf_we_wb_o    = |rf_wdata_wb_mux_we;\nendmodule\n", "mask_idx": {"ansi_port_declaration": [[25433, 25478], [24906, 24946], [25235, 25282], [24993, 25051], [25382, 25430], [25335, 25379], [25531, 25578]], "continuous_assign": [[26711, 26863], [26370, 26462], [26866, 26909], [26514, 26557], [26465, 26511], [25959, 26004], [26200, 26365], [26009, 26054]], "parameter_declaration": [[16802, 16847], [13551, 13619], [13787, 13814], [16708, 16752], [13622, 13688], [16898, 16943], [16850, 16895], [16946, 16990]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[25959, 26004], [26009, 26054], [26059, 26101], [26200, 26365], [26370, 26462], [26465, 26511], [26514, 26557], [26711, 26863], [26866, 26909]], "blocking_assignment": [], "nonblocking_assignment": [], "case_statement": [], "conditional_statement": [], "always_construct": [], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096]], "ansi_port_declaration": [[24864, 24903], [24906, 24946], [24949, 24990], [24993, 25051], [25054, 25109], [25112, 25165], [25168, 25232], [25235, 25282], [25285, 25332], [25335, 25379], [25382, 25430], [25433, 25478], [25481, 25528], [25531, 25578], [25581, 25625], [25628, 25678], [25681, 25728]]}}
{"sample_i": "p2", "topmodule": "cve2_branch_predict", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Branch Predictor\n *\n * This implements static branch prediction. It takes an instruction and its PC and determines if\n * it's a branch or a jump and calculates its target. For jumps it will always predict taken. For\n * branches it will predict taken if the PC offset is negative.\n *\n * This handles both compressed and uncompressed instructions. Compressed instructions must be in\n * the lower 16-bits of instr.\n *\n * The predictor is entirely combinational but takes clk/rst_n signals for use by assertions.\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_branch_predict (\n  input  logic clk_i,\n  input  logic rst_ni,\n  // Instruction from fetch stage\n  input  logic [31:0] fetch_rdata_i,\n  input  logic [31:0] fetch_pc_i,\n  input  logic        fetch_valid_i,\n  // Prediction for supplied instruction\n  output logic        predict_branch_taken_o,\n  output logic [31:0] predict_branch_pc_o\n);\n  import cve2_pkg::*;\n  logic [31:0] imm_j_type;\n  logic [31:0] imm_b_type;\n  logic [31:0] imm_cj_type;\n  logic [31:0] imm_cb_type;\n  logic [31:0] branch_imm;\n  logic [31:0] instr;\n  logic instr_j;\n  logic instr_b;\n  logic instr_cj;\n  logic instr_cb;\n  logic instr_b_taken;\n  // Provide short internal name for fetch_rdata_i due to reduce line wrapping\n  assign instr = fetch_rdata_i;\n  // Extract and sign-extend to 32-bit the various immediates that may be used to calculate the\n  // target\n  // Uncompressed immediates\n  assign imm_j_type = { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 };\n  assign imm_b_type = { {19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 };\n  // Compressed immediates\n  assign imm_cj_type = { {20{instr[12]}}, instr[12], instr[8], instr[10:9], instr[6], instr[7],\n    instr[2], instr[11], instr[5:3], 1'b0 };\n  assign imm_cb_type = { {23{instr[12]}}, instr[12], instr[6:5], instr[2], instr[11:10],\n    instr[4:3], 1'b0};\n  // Determine if the instruction is a branch or a jump\n  // Uncompressed branch/jump\n  assign instr_b = opcode_e'(instr[6:0]) == OPCODE_BRANCH;\n  assign instr_j = opcode_e'(instr[6:0]) == OPCODE_JAL;\n  // Compressed branch/jump\n  assign instr_cb = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b110) | (instr[15:13] == 3'b111));\n  assign instr_cj = (instr[1:0] == 2'b01) & ((instr[15:13] == 3'b101) | (instr[15:13] == 3'b001));\n  // Select out the branch offset for target calculation based upon the instruction type\n  always_comb begin\n    branch_imm = imm_b_type;\n    unique case (1'b1)\n      instr_j  : branch_imm = imm_j_type;\n      instr_b  : branch_imm = imm_b_type;\n      instr_cj : branch_imm = imm_cj_type;\n      instr_cb : branch_imm = imm_cb_type;\n      default : ;\n    endcase\n  end\n  // Determine branch prediction, taken if offset is negative\n  assign instr_b_taken = (instr_b & imm_b_type[31]) | (instr_cb & imm_cb_type[31]);\n  // Always predict jumps taken otherwise take prediction from `instr_b_taken`\n  assign predict_branch_taken_o = fetch_valid_i & (instr_j | instr_cj | instr_b_taken);\n  // Calculate target\n  assign predict_branch_pc_o    = fetch_pc_i + branch_imm;\nendmodule\n", "mask_idx": {"blocking_assignment": [[25333, 25358], [25290, 25315], [25206, 25230], [25248, 25272], [25141, 25165]], "always_construct": [[25119, 25394]], "case_statement": [[25170, 25388]], "ansi_port_declaration": [[23525, 23568], [23297, 23316], [23447, 23481], [23319, 23339], [23413, 23444], [23571, 23610], [23376, 23410]], "continuous_assign": [[25732, 25788], [23969, 23998], [24138, 24223], [24748, 24801], [24689, 24745], [24226, 24320], [24350, 24488], [24491, 24600]], "parameter_declaration": [[13551, 13619], [16946, 16990], [16898, 16943], [16993, 17037], [16850, 16895], [16755, 16799], [13622, 13688], [16802, 16847]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[23969, 23998], [24138, 24223], [24226, 24320], [24350, 24488], [24491, 24600], [24689, 24745], [24748, 24801], [24832, 24928], [24931, 25027], [25459, 25540], [25622, 25707], [25732, 25788]], "blocking_assignment": [[25141, 25165], [25206, 25230], [25248, 25272], [25290, 25315], [25333, 25358]], "nonblocking_assignment": [], "case_statement": [[25170, 25388]], "conditional_statement": [], "always_construct": [[25119, 25394]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096]], "ansi_port_declaration": [[23297, 23316], [23319, 23339], [23376, 23410], [23413, 23444], [23447, 23481], [23525, 23568], [23571, 23610]]}}
{"sample_i": "p3", "topmodule": "cve2_compressed_decoder", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Compressed instruction decoder\n *\n * Decodes RISC-V compressed instructions into their RV32 equivalent.\n * This module is fully combinatorial, clock and reset are used for\n * assertions only.\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_compressed_decoder (\n  input  logic        clk_i,\n  input  logic        rst_ni,\n  input  logic        valid_i,\n  input  logic [31:0] instr_i,\n  output logic [31:0] instr_o,\n  output logic        is_compressed_o,\n  output logic        illegal_instr_o\n);\n  import cve2_pkg::*;\n  // valid_i indicates if instr_i is valid and is used for assertions only.\n  // The following signal is used to avoid possible lint errors.\n  logic unused_valid;\n  assign unused_valid = valid_i;\n  ////////////////////////\n  // Compressed decoder //\n  ////////////////////////\n  always_comb begin\n    // By default, forward incoming instruction, mark it as legal.\n    instr_o         = instr_i;\n    illegal_instr_o = 1'b0;\n    // Check if incoming instruction is compressed.\n    unique case (instr_i[1:0])\n      // C0\n      2'b00: begin\n        unique case (instr_i[15:13])\n          3'b000: begin\n            // c.addi4spn -> addi rd', x2, imm\n            instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5],\n                       instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {OPCODE_OP_IMM}};\n            if (instr_i[12:5] == 8'b0)  illegal_instr_o = 1'b1;\n          end\n          3'b010: begin\n            // c.lw -> lw rd', imm(rs1')\n            instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6],\n                       2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD}};\n          end\n          3'b110: begin\n            // c.sw -> sw rs2', imm(rs1')\n            instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2],\n                       2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6],\n                       2'b00, {OPCODE_STORE}};\n          end\n          3'b001,\n          3'b011,\n          3'b100,\n          3'b101,\n          3'b111: begin\n            illegal_instr_o = 1'b1;\n          end\n          default: begin\n            illegal_instr_o = 1'b1;\n          end\n        endcase\n      end\n      // C1\n      //\n      // Register address checks for RV32E are performed in the regular instruction decoder.\n      // If this check fails, an illegal instruction exception is triggered and the controller\n      // writes the actual faulting instruction to mtval.\n      2'b01: begin\n        unique case (instr_i[15:13])\n          3'b000: begin\n            // c.addi -> addi rd, rd, nzimm\n            // c.nop\n            instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2],\n                       instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP_IMM}};\n          end\n          3'b001, 3'b101: begin\n            // 001: c.jal -> jal x1, imm\n            // 101: c.j   -> jal x0, imm\n            instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6],\n                       instr_i[7], instr_i[2], instr_i[11], instr_i[5:3],\n                       {9 {instr_i[12]}}, 4'b0, ~instr_i[15], {OPCODE_JAL}};\n          end\n          3'b010: begin\n            // c.li -> addi rd, x0, nzimm\n            // (c.li hints are translated into an addi hint)\n            instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0,\n                       3'b0, instr_i[11:7], {OPCODE_OP_IMM}};\n          end\n          3'b011: begin\n            // c.lui -> lui rd, imm\n            // (c.lui hints are translated into a lui hint)\n            instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}};\n            if (instr_i[11:7] == 5'h02) begin\n              // c.addi16sp -> addi x2, x2, nzimm\n              instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2],\n                         instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}};\n            end\n            if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;\n          end\n          3'b100: begin\n            unique case (instr_i[11:10])\n              2'b00,\n              2'b01: begin\n                // 00: c.srli -> srli rd, rd, shamt\n                // 01: c.srai -> srai rd, rd, shamt\n                // (c.srli/c.srai hints are translated into a srli/srai hint)\n                instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7],\n                           3'b101, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};\n                if (instr_i[12] == 1'b1)  illegal_instr_o = 1'b1;\n              end\n              2'b10: begin\n                // c.andi -> andi rd, rd, imm\n                instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7],\n                           3'b111, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};\n              end\n              2'b11: begin\n                unique case ({instr_i[12], instr_i[6:5]})\n                  3'b000: begin\n                    // c.sub -> sub rd', rd', rs2'\n                    instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7],\n                               3'b000, 2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b001: begin\n                    // c.xor -> xor rd', rd', rs2'\n                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100,\n                               2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b010: begin\n                    // c.or  -> or  rd', rd', rs2'\n                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110,\n                               2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b011: begin\n                    // c.and -> and rd', rd', rs2'\n                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111,\n                               2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b100,\n                  3'b101,\n                  3'b110,\n                  3'b111: begin\n                    // 100: c.subw\n                    // 101: c.addw\n                    illegal_instr_o = 1'b1;\n                  end\n                  default: begin\n                    illegal_instr_o = 1'b1;\n                  end\n                endcase\n              end\n              default: begin\n                illegal_instr_o = 1'b1;\n              end\n            endcase\n          end\n          3'b110, 3'b111: begin\n            // 0: c.beqz -> beq rs1', x0, imm\n            // 1: c.bnez -> bne rs1', x0, imm\n            instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01,\n                       instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3],\n                       instr_i[12], {OPCODE_BRANCH}};\n          end\n          default: begin\n            illegal_instr_o = 1'b1;\n          end\n        endcase\n      end\n      // C2\n      //\n      // Register address checks for RV32E are performed in the regular instruction decoder.\n      // If this check fails, an illegal instruction exception is triggered and the controller\n      // writes the actual faulting instruction to mtval.\n      2'b10: begin\n        unique case (instr_i[15:13])\n          3'b000: begin\n            // c.slli -> slli rd, rd, shamt\n            // (c.ssli hints are translated into a slli hint)\n            instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {OPCODE_OP_IMM}};\n            if (instr_i[12] == 1'b1)  illegal_instr_o = 1'b1; // reserved for custom extensions\n          end\n          3'b010: begin\n            // c.lwsp -> lw rd, imm(x2)\n            instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02,\n                       3'b010, instr_i[11:7], OPCODE_LOAD};\n            if (instr_i[11:7] == 5'b0)  illegal_instr_o = 1'b1;\n          end\n          3'b100: begin\n            if (instr_i[12] == 1'b0) begin\n              if (instr_i[6:2] != 5'b0) begin\n                // c.mv -> add rd/rs1, x0, rs2\n                // (c.mv hints are translated into an add hint)\n                instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}};\n              end else begin\n                // c.jr -> jalr x0, rd/rs1, 0\n                instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}};\n                if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;\n              end\n            end else begin\n              if (instr_i[6:2] != 5'b0) begin\n                // c.add -> add rd, rd, rs2\n                // (c.add hints are translated into an add hint)\n                instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}};\n              end else begin\n                if (instr_i[11:7] == 5'b0) begin\n                  // c.ebreak -> ebreak\n                  instr_o = {32'h00_10_00_73};\n                end else begin\n                  // c.jalr -> jalr x1, rs1, 0\n                  instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}};\n                end\n              end\n            end\n          end\n          3'b110: begin\n            // c.swsp -> sw rs2, imm(x2)\n            instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010,\n                       instr_i[11:9], 2'b00, {OPCODE_STORE}};\n          end\n          3'b001,\n          3'b011,\n          3'b101,\n          3'b111: begin\n            illegal_instr_o = 1'b1;\n          end\n          default: begin\n            illegal_instr_o = 1'b1;\n          end\n        endcase\n      end\n      // Incoming instruction is not compressed.\n      2'b11:;\n      default: begin\n        illegal_instr_o = 1'b1;\n      end\n    endcase\n  end\n  assign is_compressed_o = (instr_i[1:0] != 2'b11);\n  ////////////////\n  // Assertions //\n  ////////////////\n  // The valid_i signal used to gate below assertions must be known.\n  // Selectors must be known/valid.\nendmodule\n", "mask_idx": {"conditional_statement": [[31186, 31789], [26677, 26741], [30530, 30581], [24138, 24189], [30212, 30295], [27228, 27277], [30677, 31144], [31076, 31126], [31469, 31771]], "blocking_assignment": [[23681, 23707], [31685, 31751], [24526, 24715], [24281, 24433], [27067, 27211], [29323, 29532], [28266, 28398], [26042, 26166]], "always_construct": [[23592, 32418]], "case_statement": [[25271, 29637], [29942, 32264], [23792, 32412], [26792, 29172], [23858, 24966], [27598, 29047]], "ansi_port_declaration": [[23120, 23148], [23090, 23117], [23061, 23087], [23213, 23249], [23151, 23179], [23252, 23287], [23182, 23210]], "continuous_assign": [[32421, 32470]], "parameter_declaration": [[16993, 17037], [13787, 13814], [13551, 13619], [16802, 16847], [16708, 16752], [13622, 13688], [16850, 16895], [16755, 16799]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[23478, 23508], [32421, 32470]], "blocking_assignment": [[23681, 23707], [23712, 23735], [23970, 24125], [24166, 24189], [24281, 24433], [24526, 24715], [24838, 24861], [24913, 24936], [25401, 25534], [25675, 25888], [26042, 26166], [26313, 26387], [26498, 26648], [26718, 26741], [27067, 27211], [27254, 27277], [27385, 27536], [27743, 27882], [28008, 28140], [28266, 28398], [28524, 28656], [28879, 28902], [28978, 29001], [29111, 29134], [29323, 29532], [29584, 29607], [30113, 30199], [30238, 30295], [30386, 30517], [30558, 30581], [30836, 30907], [30999, 31059], [31103, 31126], [31343, 31423], [31560, 31588], [31685, 31751], [31897, 32031], [32136, 32159], [32211, 32234], [32367, 32390]], "nonblocking_assignment": [], "case_statement": [[23792, 32412], [23858, 24966], [25271, 29637], [26792, 29172], [27598, 29047], [29942, 32264]], "conditional_statement": [[24138, 24189], [26400, 26664], [26677, 26741], [27228, 27277], [30212, 30295], [30530, 30581], [30632, 31805], [30677, 31144], [31076, 31126], [31186, 31789], [31469, 31771]], "always_construct": [[23592, 32418]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096]], "ansi_port_declaration": [[23061, 23087], [23090, 23117], [23120, 23148], [23151, 23179], [23182, 23210], [23213, 23249], [23252, 23287]]}}
{"sample_i": "p4", "topmodule": "cve2_controller", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Main controller of the processor\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Include FCOV RTL by default. Disable it for synthesis and where explicitly requested (by defining\n// DV_FCOV_DISABLE).\n// Disable instantiations of FCOV coverpoints or covergroups.\n// Instantiates a covergroup in an interface or module.\n//\n// This macro assumes that a covergroup of the same name as the NAME_ arg is defined in the\n// interface or module. It just adds some extra signals and logic to control the creation of the\n// covergroup instance with ~bit en_<cg_name>~. This defaults to 0. It is ORed with the external\n// COND_ signal. The testbench can modify it at t = 0 based on the test being run.\n// NOTE: This is not meant to be invoked inside a class.\n//\n// NAME_ : Name of the covergroup.\n// COND_ : External condition / expr that controls the creation of the covergroup.\n// ARGS_ : Arguments to covergroup instance, if any. Args MUST BE wrapped in (..).\n// Creates a coverpoint for an expression where only the expression true case is of interest for\n// coverage (e.g. where the expression indicates an event has occured).\n// Creates a SVA cover that can be used in a covergroup.\n//\n// This macro creates an unnamed SVA cover from the property (or an expression) `PROP_` and an event\n// with the name `EV_NAME_`. When the SVA cover is hit, the event is triggered. A coverpoint can\n// cover the `triggered` property of the event.\n// Coverage support is not always available but it's useful to include extra fcov signals for\n// linting purposes. They need to be marked as unused to avoid warnings.\n// Define a signal and expression in the design for capture in functional coverage\n// Define a signal and expression in the design for capture in functional coverage depending on\n// design configuration. The input GEN_COND_ must be a constant or parameter.\nmodule cve2_controller #(\n ) (\n  input  logic                  clk_i,\n  input  logic                  rst_ni,\n  input  logic                  fetch_enable_i,          // core can fetch instructions leave RESET state\n  output logic                  ctrl_busy_o,             // core is busy processing instrs\n  // decoder related signals\n  input  logic                  illegal_insn_i,          // decoder has an invalid instr\n  input  logic                  ecall_insn_i,            // decoder has ECALL instr\n  input  logic                  mret_insn_i,             // decoder has MRET instr\n  input  logic                  dret_insn_i,             // decoder has DRET instr\n  input  logic                  wfi_insn_i,              // decoder has WFI instr\n  input  logic                  ebrk_insn_i,             // decoder has EBREAK instr\n  input  logic                  csr_pipe_flush_i,        // do CSR-related pipeline flush\n  input  logic                  xif_scoreboard_busy_i,   // tells if the the core is waiting for XIF\n  // instr from IF-ID pipeline stage\n  input  logic                  instr_valid_i,           // instr is valid\n  input  logic [31:0]           instr_i,                 // uncompressed instr data for mtval\n  input  logic [15:0]           instr_compressed_i,      // instr compressed data for mtval\n  input  logic                  instr_is_compressed_i,   // instr is compressed\n  input  logic                  instr_fetch_err_i,       // instr has error\n  input  logic                  instr_fetch_err_plus2_i, // instr error is x32\n  input  logic [31:0]           pc_id_i,                 // instr address\n  // to IF-ID pipeline stage\n  output logic                  instr_valid_clear_o,     // kill instr in IF-ID reg\n  output logic                  id_in_ready_o,           // ID stage is ready for new instr\n  output logic                  controller_run_o,        // Controller is in standard instruction\n                                                         // run mode\n  // to prefetcher\n  output logic                  instr_req_o,             // start fetching instructions\n  output logic                  pc_set_o,                // jump to address set by pc_mux\n  output cve2_pkg::pc_sel_e     pc_mux_o,                // IF stage fetch address selector\n                                                         // (boot, normal, exception...)\n  output cve2_pkg::exc_pc_sel_e exc_pc_mux_o,            // IF stage selector for exception PC\n  output cve2_pkg::exc_cause_e  exc_cause_o,             // for IF stage, CSRs\n  // LSU\n  input  logic [31:0]           lsu_addr_last_i,         // for mtval\n  input  logic                  load_err_i,\n  input  logic                  store_err_i,\n  // jump/branch signals\n  input  logic                  branch_set_i,            // branch set signal (branch definitely\n                                                         // taken)\n  input  logic                  jump_set_i,              // jump taken set signal\n  // interrupt signals\n  input  logic                  csr_mstatus_mie_i,       // M-mode interrupt enable bit\n  input  logic                  irq_pending_i,           // interrupt request pending\n  input  cve2_pkg::irqs_t       irqs_i,                  // interrupt requests qualified with\n                                                         // mie CSR\n  input  logic                  irq_nm_i,                // non-maskeable interrupt\n  output logic                  nmi_mode_o,              // core executing NMI handler\n  // debug signals\n  input  logic                  debug_req_i,\n  output cve2_pkg::dbg_cause_e  debug_cause_o,\n  output logic                  debug_csr_save_o,\n  output logic                  debug_mode_o,\n  input  logic                  debug_single_step_i,\n  input  logic                  debug_ebreakm_i,\n  input  logic                  debug_ebreaku_i,\n  input  logic                  trigger_match_i,\n  output logic                  csr_save_if_o,\n  output logic                  csr_save_id_o,\n  output logic                  csr_restore_mret_id_o,\n  output logic                  csr_restore_dret_id_o,\n  output logic                  csr_save_cause_o,\n  output logic [31:0]           csr_mtval_o,\n  input  cve2_pkg::priv_lvl_e   priv_mode_i,\n  input  logic                  csr_mstatus_tw_i,\n  // stall & flush signals\n  input  logic                  stall_id_i,\n  output logic                  flush_id_o,\n  // performance monitors\n  output logic                  perf_jump_o,             // we are executing a jump\n                                                         // instruction (j, jr, jal, jalr)\n  output logic                  perf_tbranch_o           // we are executing a taken branch\n                                                         // instruction\n);\n  import cve2_pkg::*;\n  // FSM state encoding\n  typedef enum logic [3:0] {\n    RESET, BOOT_SET, WAIT_SLEEP, SLEEP, FIRST_FETCH, DECODE, FLUSH,\n    IRQ_TAKEN, DBG_TAKEN_IF, DBG_TAKEN_ID\n  } ctrl_fsm_e;\n  ctrl_fsm_e ctrl_fsm_cs, ctrl_fsm_ns;\n  logic nmi_mode_q, nmi_mode_d;\n  logic debug_mode_q, debug_mode_d;\n  logic load_err_q, load_err_d;\n  logic store_err_q, store_err_d;\n  logic exc_req_q, exc_req_d;\n  logic illegal_insn_q, illegal_insn_d;\n  // Of the various exception/fault signals, which one takes priority in FLUSH and hence controls\n  // what happens next (setting exc_cause, csr_mtval etc)\n  logic instr_fetch_err_prio;\n  logic illegal_insn_prio;\n  logic ecall_insn_prio;\n  logic ebrk_insn_prio;\n  logic store_err_prio;\n  logic load_err_prio;\n  logic stall;\n  logic halt_if;\n  logic retain_id;\n  logic flush_id;\n  logic illegal_dret;\n  logic illegal_umode;\n  logic exc_req_lsu;\n  logic special_req;\n  logic special_req_pc_change;\n  logic special_req_flush_only;\n  logic do_single_step_d;\n  logic do_single_step_q;\n  logic enter_debug_mode_prio_d;\n  logic enter_debug_mode_prio_q;\n  logic enter_debug_mode;\n  logic ebreak_into_debug;\n  logic handle_irq;\n  logic [3:0] mfip_id;\n  logic       unused_irq_timer;\n  logic ecall_insn;\n  logic mret_insn;\n  logic dret_insn;\n  logic wfi_insn;\n  logic ebrk_insn;\n  logic csr_pipe_flush;\n  logic instr_fetch_err;\n  ////////////////\n  // Exceptions //\n  ////////////////\n  assign load_err_d  = load_err_i;\n  assign store_err_d = store_err_i;\n  // Decoder doesn't take instr_valid into account, factor it in here.\n  assign ecall_insn      = ecall_insn_i      & instr_valid_i;\n  assign mret_insn       = mret_insn_i       & instr_valid_i;\n  assign dret_insn       = dret_insn_i       & instr_valid_i;\n  assign wfi_insn        = wfi_insn_i        & instr_valid_i;\n  assign ebrk_insn       = ebrk_insn_i       & instr_valid_i;\n  assign csr_pipe_flush  = csr_pipe_flush_i  & instr_valid_i;\n  assign instr_fetch_err = instr_fetch_err_i & instr_valid_i;\n  // \"Executing DRET outside of Debug Mode causes an illegal instruction exception.\"\n  // [Debug Spec v0.13.2, p.41]\n  assign illegal_dret = dret_insn & ~debug_mode_q;\n  // Some instructions can only be executed in M-Mode\n  assign illegal_umode = (priv_mode_i != PRIV_LVL_M) &\n                         // MRET must be in M-Mode. TW means trap WFI to M-Mode.\n                         (mret_insn | (csr_mstatus_tw_i & wfi_insn));\n  // This is recorded in the illegal_insn_q flop to help timing.  Specifically\n  // it is needed to break the path from cve2_cs_registers/illegal_csr_insn_o\n  // to pc_set_o.  Clear when controller is in FLUSH so it won't remain set\n  // once illegal instruction is handled.\n  // All terms in this expression are qualified by instr_valid_i\n  assign illegal_insn_d = (illegal_insn_i | illegal_dret | illegal_umode) & (ctrl_fsm_cs != FLUSH);\n  // exception requests\n  // requests are flopped in exc_req_q.  This is cleared when controller is in\n  // the FLUSH state so the cycle following exc_req_q won't remain set for an\n  // exception request that has just been handled.\n  // All terms in this expression are qualified by instr_valid_i\n  assign exc_req_d = (ecall_insn | ebrk_insn | illegal_insn_d | instr_fetch_err) &\n                     (ctrl_fsm_cs != FLUSH);\n  // LSU exception requests\n  assign exc_req_lsu = store_err_i | load_err_i;\n  // special requests: special instructions, pipeline flushes, exceptions...\n  // All terms in these expressions are qualified by instr_valid_i except exc_req_lsu which can come\n  // from the Writeback stage with no instr_valid_i from the ID stage\n  // These special requests only cause a pipeline flush and in particular don't cause a PC change\n  // that is outside the normal execution flow\n  assign special_req_flush_only = wfi_insn | csr_pipe_flush;\n  // These special requests cause a change in PC\n  assign special_req_pc_change = mret_insn | dret_insn | exc_req_d | exc_req_lsu;\n  // generic special request signal, applies to all instructions\n  assign special_req = special_req_pc_change | special_req_flush_only;\n  // Exception/fault prioritisation is taken from Table 3.7 of Priviledged Spec v1.11\n    always_comb begin\n      instr_fetch_err_prio = 0;\n      illegal_insn_prio    = 0;\n      ecall_insn_prio      = 0;\n      ebrk_insn_prio       = 0;\n      store_err_prio       = 0;\n      load_err_prio        = 0;\n      if (instr_fetch_err) begin\n        instr_fetch_err_prio = 1'b1;\n      end else if (illegal_insn_q) begin\n        illegal_insn_prio = 1'b1;\n      end else if (ecall_insn) begin\n        ecall_insn_prio = 1'b1;\n      end else if (ebrk_insn) begin\n        ebrk_insn_prio = 1'b1;\n      end else if (store_err_q) begin\n        store_err_prio = 1'b1;\n      end else if (load_err_q) begin\n        load_err_prio  = 1'b1;\n      end\n    end\n  ////////////////\n  // Interrupts //\n  ////////////////\n  // Enter debug mode due to an external debug_req_i or because the core is in\n  // single step mode (dcsr.step == 1). Single step must be qualified with\n  // instruction valid otherwise the core will immediately enter debug mode\n  // due to a recently flushed IF (or a delay in an instruction returning from\n  // memory) before it has had anything to single step.\n  // Also enter debug mode on a trigger match (hardware breakpoint)\n  // Set `do_single_step_q` when a valid instruction is seen outside of debug mode and core is in\n  // single step mode. The first valid instruction on debug mode entry will clear it. Hold its value\n  // when there is no valid instruction so `do_single_step_d` remains asserted until debug mode is\n  // entered.\n  assign do_single_step_d = instr_valid_i ? ~debug_mode_q & debug_single_step_i : do_single_step_q;\n  // Enter debug mode due to:\n  // * external `debug_req_i`\n  // * core in single step mode (dcsr.step == 1).\n  // * trigger match (hardware breakpoint)\n  //\n  // `debug_req_i` and `do_single_step_d` request debug mode with priority. This results in a debug\n  // mode entry even if the controller goes to `FLUSH` in preparation for handling an exception or\n  // interrupt. `trigger_match_i` is not a priority entry into debug mode as it must be ignored\n  // where control flow changes such that the instruction causing the trigger is no longer being\n  // executed.\n  assign enter_debug_mode_prio_d = (debug_req_i | do_single_step_d) & ~debug_mode_q;\n  assign enter_debug_mode = enter_debug_mode_prio_d | (trigger_match_i & ~debug_mode_q);\n  // Set when an ebreak should enter debug mode rather than jump to exception\n  // handler\n  assign ebreak_into_debug = priv_mode_i == PRIV_LVL_M ? debug_ebreakm_i :\n                             priv_mode_i == PRIV_LVL_U ? debug_ebreaku_i :\n                                                         1'b0;\n  // Interrupts including NMI are ignored,\n  // - while in debug mode [Debug Spec v0.13.2, p.39],\n  // - while in NMI mode (nested NMIs are not supported, NMI has highest priority and\n  //   cannot be interrupted by regular interrupts).\n  // - while single stepping.\n  assign handle_irq = ~debug_mode_q & ~nmi_mode_q &\n      (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i));\n  // generate ID of fast interrupts, highest priority to lowest ID\n  always_comb begin : gen_mfip_id\n    mfip_id = 4'd0;\n    for (int i = 15; i >= 0; i--) begin\n      if (irqs_i.irq_fast[i]) begin\n        mfip_id = i[3:0];\n      end\n    end\n  end\n  assign unused_irq_timer = irqs_i.irq_timer;\n  /////////////////////\n  // Core controller //\n  /////////////////////\n  always_comb begin\n    // Default values\n    instr_req_o           = 1'b1;\n    csr_save_if_o         = 1'b0;\n    csr_save_id_o         = 1'b0;\n    csr_restore_mret_id_o = 1'b0;\n    csr_restore_dret_id_o = 1'b0;\n    csr_save_cause_o      = 1'b0;\n    csr_mtval_o           = '0;\n    // The values of pc_mux and exc_pc_mux are only relevant if pc_set is set. Some of the states\n    // below always set pc_mux and exc_pc_mux but only set pc_set if certain conditions are met.\n    // This avoid having to factor those conditions into the pc_mux and exc_pc_mux select signals\n    // helping timing.\n    pc_mux_o               = PC_BOOT;\n    pc_set_o               = 1'b0;\n    exc_pc_mux_o           = EXC_PC_IRQ;\n    exc_cause_o            = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00\n    ctrl_fsm_ns            = ctrl_fsm_cs;\n    ctrl_busy_o            = 1'b1;\n    halt_if                = 1'b0;\n    retain_id              = 1'b0;\n    flush_id               = 1'b0;\n    debug_csr_save_o       = 1'b0;\n    debug_cause_o          = DBG_CAUSE_EBREAK;\n    debug_mode_d           = debug_mode_q;\n    nmi_mode_d             = nmi_mode_q;\n    perf_tbranch_o         = 1'b0;\n    perf_jump_o            = 1'b0;\n    controller_run_o       = 1'b0;\n    unique case (ctrl_fsm_cs)\n      RESET: begin\n        instr_req_o   = 1'b0;\n        pc_mux_o      = PC_BOOT;\n        pc_set_o      = 1'b1;\n        if (fetch_enable_i == 1'b1)\n        begin\n          ctrl_fsm_ns = BOOT_SET;\n        end\n      end\n      BOOT_SET: begin\n        // copy boot address to instr fetch address\n        instr_req_o   = 1'b1;\n        pc_mux_o      = PC_BOOT;\n        pc_set_o      = 1'b1;\n        ctrl_fsm_ns = FIRST_FETCH;\n      end\n      WAIT_SLEEP: begin\n        ctrl_busy_o   = 1'b0;\n        instr_req_o   = 1'b0;\n        halt_if       = 1'b1;\n        flush_id      = 1'b1;\n        ctrl_fsm_ns   = SLEEP;\n      end\n      SLEEP: begin\n        // instruction in IF stage is already valid\n        // we begin execution when an interrupt has arrived\n        instr_req_o   = 1'b0;\n        halt_if       = 1'b1;\n        flush_id      = 1'b1;\n        // normal execution flow\n        // in debug mode or single step mode we leave immediately (wfi=nop)\n        if (irq_nm_i || irq_pending_i || debug_req_i || debug_mode_q || debug_single_step_i) begin\n          ctrl_fsm_ns = FIRST_FETCH;\n        end else begin\n          // Make sure clock remains disabled.\n          ctrl_busy_o = 1'b0;\n        end\n      end\n      FIRST_FETCH: begin\n        // Stall because of IF miss\n        if (id_in_ready_o) begin\n          ctrl_fsm_ns = DECODE;\n        end\n        // handle interrupts\n        if (handle_irq) begin\n          // We are handling an interrupt. Set halt_if to tell IF not to give\n          // us any more instructions before it redirects to the handler, but\n          // don't set flush_id: we must allow this instruction to complete\n          // (since it might have outstanding loads or stores).\n          ctrl_fsm_ns = IRQ_TAKEN;\n          halt_if     = 1'b1;\n        end\n        // enter debug mode\n        if (enter_debug_mode) begin\n          ctrl_fsm_ns = DBG_TAKEN_IF;\n          // Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the\n          // ID state is needed for correct debug mode entry\n          halt_if     = 1'b1;\n        end\n      end\n      DECODE: begin\n        // normal operating mode of the ID stage, in case of debug and interrupt requests,\n        // priorities are as follows (lower number == higher priority)\n        // 1. currently running (multicycle) instructions and exceptions caused by these\n        // 2. debug requests\n        // 3. interrupt requests\n        controller_run_o = 1'b1;\n        // Set PC mux for branch and jump here to ease timing. Value is only relevant if pc_set_o is\n        // also set. Setting the mux value here avoids factoring in special_req and instr_valid_i\n        // which helps timing.\n        pc_mux_o = PC_JUMP;\n        // Get ready for special instructions, exceptions, pipeline flushes\n        if (special_req) begin\n          // Halt IF but don't flush ID. This leaves a valid instruction in\n          // ID so controller can determine appropriate action in the\n          // FLUSH state.\n          retain_id = 1'b1;\n          // The FSM will always go directly to FLUSH.\n          // when X-IF is active and xif_scoreboard_busy_i, wait the scoreboard to be empty before switching state\n          ctrl_fsm_ns = xif_scoreboard_busy_i ? DECODE: FLUSH;\n        end\n        if (branch_set_i || jump_set_i) begin\n          pc_set_o       = 1'b1;\n          perf_tbranch_o = branch_set_i;\n          perf_jump_o    = jump_set_i;\n        end\n        // If entering debug mode or handling an IRQ the core needs to wait until any instruction in\n        // ID has finished executing. Stall IF during that time.\n        if ((enter_debug_mode || handle_irq) && (stall || instr_valid_i)) begin\n          halt_if = 1'b1;\n        end\n        if (!stall && !special_req && !instr_valid_i) begin\n          if (enter_debug_mode) begin\n            // enter debug mode\n            ctrl_fsm_ns = xif_scoreboard_busy_i ? DECODE : DBG_TAKEN_IF;\n            // Halt IF only for now, ID will be flushed in DBG_TAKEN_IF as the\n            // ID state is needed for correct debug mode entry\n            halt_if     = 1'b1;\n          end else if (handle_irq) begin\n            // handle interrupt (not in debug mode)\n            ctrl_fsm_ns = xif_scoreboard_busy_i ? DECODE : IRQ_TAKEN;\n            // We are handling an interrupt (not in debug mode). Set halt_if to\n            // tell IF not to give us any more instructions before it redirects\n            // to the handler, but don't set flush_id: we must allow this\n            // instruction to complete (since it might have outstanding loads\n            // or stores).\n            halt_if     = 1'b1;\n          end\n        end\n      end // DECODE\n      IRQ_TAKEN: begin\n        pc_mux_o     = PC_EXC;\n        exc_pc_mux_o = EXC_PC_IRQ;\n        if (handle_irq) begin\n          pc_set_o         = 1'b1;\n          csr_save_if_o    = 1'b1;\n          csr_save_cause_o = 1'b1;\n          // interrupt priorities according to Privileged Spec v1.11 p.31\n          if (irq_nm_i && !nmi_mode_q) begin\n            exc_cause_o = EXC_CAUSE_IRQ_NM;\n            nmi_mode_d  = 1'b1; // enter NMI mode\n          end else if (irqs_i.irq_fast != 16'b0) begin\n            // generate exception cause ID from fast interrupt ID:\n            // - first bit distinguishes interrupts from exceptions,\n            // - third bit adds 16 to fast interrupt ID so that the interrup 0 becomes 16 and the interrupt 15 becomes 31 (hence 5bits)\n            // - second bit is always 0 as the FAST interrupts are represented in the first 5bits, the 6th is always 0 cause is used by the NMI (in that case is 1 as represented by the number 32)\n            // for example EXC_CAUSE_IRQ_FAST_0 = {1'b1, 6'd16}\n            exc_cause_o = exc_cause_e'({3'b101, mfip_id});\n          end else if (irqs_i.irq_external) begin\n            exc_cause_o = EXC_CAUSE_IRQ_EXTERNAL_M;\n          end else if (irqs_i.irq_software) begin\n            exc_cause_o = EXC_CAUSE_IRQ_SOFTWARE_M;\n          end else begin // irqs_i.irq_timer\n            exc_cause_o = EXC_CAUSE_IRQ_TIMER_M;\n          end\n        end\n        ctrl_fsm_ns = DECODE;\n      end\n      DBG_TAKEN_IF: begin\n        pc_mux_o     = PC_EXC;\n        exc_pc_mux_o = EXC_PC_DBD;\n        // enter debug mode and save PC in IF to dpc\n        // jump to debug exception handler in debug memory\n        flush_id         = 1'b1;\n        pc_set_o         = 1'b1;\n        csr_save_if_o    = 1'b1;\n        debug_csr_save_o = 1'b1;\n        csr_save_cause_o = 1'b1;\n        if (trigger_match_i) begin\n          debug_cause_o = DBG_CAUSE_TRIGGER;     // (priority 4)\n        end else if (debug_req_i) begin\n          debug_cause_o = DBG_CAUSE_HALTREQ;     // (priority 1)\n        end else begin\n          debug_cause_o = DBG_CAUSE_STEP;        // (priority 0, lowest)\n        end\n        // enter debug mode\n        debug_mode_d = 1'b1;\n        ctrl_fsm_ns  = DECODE;\n      end\n      DBG_TAKEN_ID: begin\n        // enter debug mode and save PC in ID to dpc, used when encountering\n        // 1. EBREAK during debug mode\n        // 2. EBREAK with forced entry into debug mode (ebreakm or ebreaku set).\n        // regular ebreak's go through FLUSH.\n        //\n        // for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39]\n        // jump to debug exception handler in debug memory\n        flush_id      = 1'b1;\n        pc_mux_o      = PC_EXC;\n        pc_set_o      = 1'b1;\n        exc_pc_mux_o  = EXC_PC_DBD;\n        // update dcsr and dpc\n        if (ebreak_into_debug && !debug_mode_q) begin // ebreak with forced entry\n          // dpc (set to the address of the EBREAK, i.e. set to PC in ID stage)\n          csr_save_cause_o = 1'b1;\n          csr_save_id_o    = 1'b1;\n          // dcsr\n          debug_csr_save_o = 1'b1;\n          debug_cause_o    = DBG_CAUSE_EBREAK;\n        end\n        // enter debug mode\n        debug_mode_d = 1'b1;\n        ctrl_fsm_ns  = DECODE;\n      end\n      FLUSH: begin\n        // flush the pipeline\n        halt_if     = 1'b1;\n        flush_id    = 1'b1;\n        ctrl_fsm_ns = DECODE;\n        // As pc_mux and exc_pc_mux can take various values in this state they aren't set early\n        // here.\n        // exceptions: set exception PC, save PC and exception cause\n        // exc_req_lsu is high for one clock cycle only (in DECODE)\n        if (exc_req_q || store_err_q || load_err_q) begin\n          pc_set_o         = 1'b1;\n          pc_mux_o         = PC_EXC;\n          exc_pc_mux_o     = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC;\n          begin : g_no_writeback_mepc_save\n            csr_save_id_o  = 1'b0;\n          end\n          csr_save_cause_o = 1'b1;\n          // Exception/fault prioritisation logic will have set exactly 1 X_prio signal\n          unique case (1'b1)\n            instr_fetch_err_prio: begin\n              exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;\n              csr_mtval_o = instr_fetch_err_plus2_i ? (pc_id_i + 32'd2) : pc_id_i;\n            end\n            illegal_insn_prio: begin\n              exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;\n              csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i;\n            end\n            ecall_insn_prio: begin\n              exc_cause_o = (priv_mode_i == PRIV_LVL_M) ? EXC_CAUSE_ECALL_MMODE :\n                                                          EXC_CAUSE_ECALL_UMODE;\n            end\n            ebrk_insn_prio: begin\n              if (debug_mode_q | ebreak_into_debug) begin\n                /*\n                 * EBREAK in debug mode re-enters debug mode\n                 *\n                 * \"The only exception is EBREAK. When that is executed in Debug\n                 * Mode, it halts the hart again but without updating dpc or\n                 * dcsr.\" [Debug Spec v0.13.2, p.39]\n                 */\n                /*\n                 * dcsr.ebreakm == 1:\n                 * \"EBREAK instructions in M-mode enter Debug Mode.\"\n                 * [Debug Spec v0.13.2, p.42]\n                 */\n                pc_set_o         = 1'b0;\n                csr_save_id_o    = 1'b0;\n                csr_save_cause_o = 1'b0;\n                ctrl_fsm_ns      = DBG_TAKEN_ID;\n                flush_id         = 1'b0;\n              end else begin\n                /*\n                 * \"The EBREAK instruction is used by debuggers to cause control\n                 * to be transferred back to a debugging environment. It\n                 * generates a breakpoint exception and performs no other\n                 * operation. [...] ECALL and EBREAK cause the receiving\n                 * privilege mode's epc register to be set to the address of the\n                 * ECALL or EBREAK instruction itself, not the address of the\n                 * following instruction.\" [Privileged Spec v1.11, p.40]\n                 */\n                exc_cause_o      = EXC_CAUSE_BREAKPOINT;\n              end\n            end\n            store_err_prio: begin\n              exc_cause_o = EXC_CAUSE_STORE_ACCESS_FAULT;\n              csr_mtval_o = lsu_addr_last_i;\n            end\n            load_err_prio: begin\n              exc_cause_o = EXC_CAUSE_LOAD_ACCESS_FAULT;\n              csr_mtval_o = lsu_addr_last_i;\n            end\n            default: ;\n          endcase\n        end else begin\n          // special instructions and pipeline flushes\n          if (mret_insn) begin\n            pc_mux_o              = PC_ERET;\n            pc_set_o              = 1'b1;\n            csr_restore_mret_id_o = 1'b1;\n            if (nmi_mode_q) begin\n              nmi_mode_d          = 1'b0; // exit NMI mode\n            end\n          end else if (dret_insn) begin\n            pc_mux_o              = PC_DRET;\n            pc_set_o              = 1'b1;\n            debug_mode_d          = 1'b0;\n            csr_restore_dret_id_o = 1'b1;\n          end else if (wfi_insn) begin\n            ctrl_fsm_ns           = WAIT_SLEEP;\n          end\n        end // exc_req_q\n        // Entering debug mode due to either single step or debug_req. Ensure\n        // registers are set for exception but then enter debug handler rather\n        // than exception handler [Debug Spec v0.13.2, p.44]\n        // Leave all other signals as is to ensure CSRs and PC get set as if\n        // core was entering exception handler, entry to debug mode will then\n        // see the appropriate state and setup dpc correctly.\n        // If an EBREAK instruction is causing us to enter debug mode on the\n        // same cycle as a debug_req or single step, honor the EBREAK and\n        // proceed to DBG_TAKEN_ID, as it has the highest priority.\n        // [Debug Spec v1.0.0-STABLE, p.53]\n        // cause==EBREAK    -> prio 3 (highest)\n        // cause==debug_req -> prio 2\n        // cause==step      -> prio 1 (lowest)\n        if (enter_debug_mode_prio_q && !(ebrk_insn_prio && ebreak_into_debug)) begin\n          ctrl_fsm_ns = DBG_TAKEN_IF;\n        end\n      end // FLUSH\n      default: begin\n        instr_req_o = 1'b0;\n        ctrl_fsm_ns = RESET;\n      end\n    endcase\n  end\n  assign flush_id_o = flush_id;\n  // signal to CSR when in debug mode\n  assign debug_mode_o = debug_mode_q;\n  // signal to CSR when in an NMI handler (for nested exception handling)\n  assign nmi_mode_o = nmi_mode_q;\n  ///////////////////\n  // Stall control //\n  ///////////////////\n  // If high current instruction cannot complete this cycle. Either because it needs more cycles to\n  // finish (stall_id_i)\n  assign stall = stall_id_i;\n  // signal to IF stage that ID stage is ready for next instr\n  assign id_in_ready_o = ~stall & ~halt_if & ~retain_id;\n  // kill instr in IF-ID pipeline reg that are done, or if a\n  // multicycle instr causes an exception for example\n  // retain_id is another kind of stall, where the instr_valid bit must remain\n  // set (unless flush_id is set also). It cannot be factored directly into\n  // stall as this causes a combinational loop.\n  assign instr_valid_clear_o = ~(stall | retain_id) | flush_id;\n  // update registers\n  always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs\n    if (!rst_ni) begin\n      ctrl_fsm_cs             <= RESET;\n      nmi_mode_q              <= 1'b0;\n      do_single_step_q        <= 1'b0;\n      debug_mode_q            <= 1'b0;\n      enter_debug_mode_prio_q <= 1'b0;\n      load_err_q              <= 1'b0;\n      store_err_q             <= 1'b0;\n      exc_req_q               <= 1'b0;\n      illegal_insn_q          <= 1'b0;\n    end else begin\n      ctrl_fsm_cs             <= ctrl_fsm_ns;\n      nmi_mode_q              <= nmi_mode_d;\n      do_single_step_q        <= do_single_step_d;\n      debug_mode_q            <= debug_mode_d;\n      enter_debug_mode_prio_q <= enter_debug_mode_prio_d;\n      load_err_q              <= load_err_d;\n      store_err_q             <= store_err_d;\n      exc_req_q               <= exc_req_d;\n      illegal_insn_q          <= illegal_insn_d;\n    end\n  end\n  //////////\n  // FCOV //\n  //////////\n  ////////////////\n  // Assertions //\n  ////////////////\n  // Selectors must be known/valid.\nendmodule\n", "mask_idx": {"conditional_statement": [[44228, 44418], [41957, 42066], [49830, 49926], [44848, 45152], [33999, 34420], [34358, 34420], [39324, 39563], [34153, 34420], [45843, 46178], [51103, 51229], [34078, 34420], [41144, 41611]], "blocking_assignment": [[43423, 43460], [45776, 45803], [47409, 47485], [43188, 43212], [39155, 39176], [49788, 49817], [38461, 38482], [41040, 41059], [38109, 38151]], "always_construct": [[52316, 53219], [37116, 51354], [36818, 36995], [33783, 34428]], "case_statement": [[47090, 49579], [38345, 51348]], "ansi_port_declaration": [[26203, 26276], [29197, 29238], [26279, 26355], [25862, 25934], [28881, 28933], [25008, 25096], [27277, 27353], [26911, 26998], [28486, 28529]], "continuous_assign": [[35983, 36069], [31721, 31769], [31542, 31601], [36163, 36373], [33624, 33692], [51764, 51790], [52230, 52291]], "parameter_declaration": [[16946, 16990], [16850, 16895], [16993, 17037], [13622, 13688], [13551, 13619], [16898, 16943], [16755, 16799], [16708, 16752]], "nonblocking_assignment": [[52970, 53021], [53119, 53156], [53073, 53112], [52827, 52865], [53028, 53066], [52872, 52916], [52781, 52820], [53163, 53205], [52923, 52963]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[31028, 31060], [31063, 31096], [31170, 31229], [31232, 31291], [31294, 31353], [31356, 31415], [31418, 31477], [31480, 31539], [31542, 31601], [31721, 31769], [31826, 32029], [32372, 32469], [32769, 32894], [32925, 32971], [33367, 33425], [33477, 33556], [33624, 33692], [35233, 35330], [35898, 35980], [35983, 36069], [36163, 36373], [36643, 36748], [36998, 37041], [51357, 51386], [51427, 51462], [51539, 51570], [51764, 51790], [51855, 51909], [52230, 52291]], "blocking_assignment": [[33807, 33832], [33839, 33864], [33871, 33896], [33903, 33928], [33935, 33960], [33967, 33992], [34034, 34062], [34112, 34137], [34183, 34206], [34251, 34273], [34320, 34342], [34388, 34410], [36854, 36869], [36954, 36971], [37160, 37189], [37194, 37223], [37228, 37257], [37262, 37291], [37296, 37325], [37330, 37359], [37364, 37391], [37712, 37745], [37750, 37780], [37785, 37821], [37826, 37887], [37892, 37929], [37934, 37964], [37969, 37999], [38004, 38034], [38039, 38069], [38074, 38104], [38109, 38151], [38156, 38194], [38199, 38235], [38240, 38270], [38275, 38305], [38310, 38340], [38398, 38419], [38428, 38452], [38461, 38482], [38543, 38566], [38671, 38692], [38701, 38725], [38734, 38755], [38764, 38790], [38833, 38854], [38863, 38884], [38893, 38914], [38923, 38944], [38953, 38975], [39125, 39146], [39155, 39176], [39185, 39206], [39425, 39451], [39532, 39551], [39678, 39699], [40077, 40101], [40112, 40131], [40218, 40245], [40394, 40413], [40777, 40801], [41040, 41059], [41349, 41366], [41547, 41599], [41668, 41690], [41701, 41731], [41742, 41770], [42039, 42054], [42209, 42269], [42424, 42443], [42549, 42606], [42958, 42977], [43055, 43077], [43086, 43112], [43153, 43177], [43188, 43212], [43223, 43247], [43379, 43410], [43423, 43460], [44060, 44106], [44169, 44208], [44271, 44310], [44368, 44404], [44439, 44460], [44505, 44527], [44536, 44562], [44683, 44707], [44716, 44740], [44749, 44773], [44782, 44806], [44815, 44839], [44885, 44939], [44990, 45044], [45078, 45140], [45189, 45209], [45218, 45240], [45684, 45705], [45714, 45737], [45746, 45767], [45776, 45803], [46007, 46031], [46042, 46066], [46095, 46119], [46130, 46166], [46215, 46235], [46244, 46266], [46334, 46353], [46362, 46381], [46390, 46411], [46730, 46754], [46765, 46791], [46802, 46864], [46920, 46942], [46967, 46991], [47163, 47206], [47221, 47289], [47357, 47394], [47409, 47485], [47551, 47699], [48346, 48370], [48387, 48411], [48428, 48452], [48469, 48501], [48518, 48542], [49160, 49200], [49283, 49326], [49341, 49371], [49435, 49477], [49492, 49522], [49701, 49733], [49746, 49775], [49788, 49817], [49866, 49910], [49979, 50011], [50024, 50053], [50066, 50095], [50108, 50137], [50189, 50224], [51190, 51217], [51278, 51297], [51306, 51326]], "nonblocking_assignment": [[52410, 52443], [52450, 52482], [52489, 52521], [52528, 52560], [52567, 52599], [52606, 52638], [52645, 52677], [52684, 52716], [52723, 52755], [52781, 52820], [52827, 52865], [52872, 52916], [52923, 52963], [52970, 53021], [53028, 53066], [53073, 53112], [53119, 53156], [53163, 53205]], "case_statement": [[38345, 51348], [47090, 49579]], "conditional_statement": [[33999, 34420], [34078, 34420], [34153, 34420], [34222, 34420], [34289, 34420], [34358, 34420], [36916, 36981], [38491, 38578], [39324, 39563], [39643, 39711], [39749, 40143], [40180, 40425], [41144, 41611], [41620, 41782], [41957, 42066], [42075, 43003], [42137, 42991], [42463, 42991], [43121, 44430], [43332, 44418], [43480, 44418], [44126, 44418], [44228, 44418], [44848, 45152], [44957, 45152], [45843, 46178], [46670, 50263], [47764, 49218], [49668, 50238], [49830, 49926], [49946, 50238], [50157, 50238], [51103, 51229], [52385, 53213]], "always_construct": [[33783, 34428], [36818, 36995], [37116, 51354], [52316, 53219]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096]], "ansi_port_declaration": [[24823, 24859], [24862, 24899], [24902, 25005], [25008, 25096], [25128, 25214], [25217, 25298], [25301, 25381], [25384, 25464], [25467, 25546], [25549, 25631], [25634, 25721], [25724, 25822], [25862, 25934], [25937, 26028], [26031, 26120], [26123, 26200], [26203, 26276], [26279, 26355], [26358, 26429], [26461, 26542], [26545, 26634], [26637, 26732], [26823, 26908], [26911, 26998], [27001, 27090], [27182, 27274], [27277, 27353], [27365, 27432], [27435, 27476], [27479, 27521], [27549, 27643], [27713, 27792], [27818, 27903], [27906, 27989], [27992, 28083], [28154, 28235], [28238, 28322], [28344, 28386], [28389, 28433], [28436, 28483], [28486, 28529], [28532, 28582], [28585, 28631], [28634, 28680], [28683, 28729], [28732, 28776], [28779, 28823], [28826, 28878], [28881, 28933], [28936, 28983], [28986, 29028], [29031, 29073], [29076, 29123], [29153, 29194], [29197, 29238], [29267, 29348], [29442, 29531]]}}
{"sample_i": "p5", "topmodule": "cve2_cs_registers", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Control / status register primitive\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_csr #(\n  parameter int unsigned    Width      = 32,\n  parameter bit             ShadowCopy = 1'b0,\n  parameter bit [Width-1:0] ResetValue = '0\n ) (\n  input  logic             clk_i,\n  input  logic             rst_ni,\n  input  logic [Width-1:0] wr_data_i,\n  input  logic             wr_en_i,\n  output logic [Width-1:0] rd_data_o,\n  output logic             rd_error_o\n);\n  logic [Width-1:0] rdata_q;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      rdata_q <= ResetValue;\n    end else if (wr_en_i) begin\n      rdata_q <= wr_data_i;\n    end\n  end\n  assign rd_data_o = rdata_q;\n  if (ShadowCopy) begin : gen_shadow\n    logic [Width-1:0] shadow_q;\n    always_ff @(posedge clk_i or negedge rst_ni) begin\n      if (!rst_ni) begin\n        shadow_q <= ~ResetValue;\n      end else if (wr_en_i) begin\n        shadow_q <= ~wr_data_i;\n      end\n    end\n    assign rd_error_o = rdata_q != ~shadow_q;\n  end else begin : gen_no_shadow\n    assign rd_error_o = 1'b0;\n  end\nendmodule\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\nmodule cve2_counter #(\n  parameter int CounterWidth = 32,\n  // When set `counter_val_upd_o` provides an incremented version of the counter value, otherwise\n  // the output is hard-wired to 0. This is required to allow Xilinx DSP inference to work\n  // correctly. When `ProvideValUpd` is set no DSPs are inferred.\n  parameter bit ProvideValUpd = 0\n) (\n  input  logic        clk_i,\n  input  logic        rst_ni,\n  input  logic        counter_inc_i,\n  input  logic        counterh_we_i,\n  input  logic        counter_we_i,\n  input  logic [31:0] counter_val_i,\n  output logic [63:0] counter_val_o,\n  output logic [63:0] counter_val_upd_o\n);\n  logic [63:0]             counter;\n  logic [CounterWidth-1:0] counter_upd;\n  logic [63:0]             counter_load;\n  logic                    we;\n  logic [CounterWidth-1:0] counter_d;\n  // Increment\n  assign counter_upd = counter[CounterWidth-1:0] + {{CounterWidth - 1{1'b0}}, 1'b1};\n  // Update\n  always_comb begin\n    // Write\n    we = counter_we_i | counterh_we_i;\n    counter_load[63:32] = counter[63:32];\n    counter_load[31:0]  = counter_val_i;\n    if (counterh_we_i) begin\n      counter_load[63:32] = counter_val_i;\n      counter_load[31:0]  = counter[31:0];\n    end\n    // Next value logic\n    if (we) begin\n      counter_d = counter_load[CounterWidth-1:0];\n    end else if (counter_inc_i) begin\n      counter_d = counter_upd[CounterWidth-1:0];\n    end else begin\n      counter_d = counter[CounterWidth-1:0];\n    end\n  end\n  logic [CounterWidth-1:0] counter_q;\n  // Counter flop\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      counter_q <= '0;\n    end else begin\n      counter_q <= counter_d;\n    end\n  end\n  if (CounterWidth < 64) begin : g_counter_narrow\n    logic [63:CounterWidth] unused_counter_load;\n    assign counter[CounterWidth-1:0]           = counter_q;\n    assign counter[63:CounterWidth]            = '0;\n    if (ProvideValUpd) begin : g_counter_val_upd_o\n      assign counter_val_upd_o[CounterWidth-1:0] = counter_upd;\n    end else begin : g_no_counter_val_upd_o\n      assign counter_val_upd_o[CounterWidth-1:0] = '0;\n    end\n    assign counter_val_upd_o[63:CounterWidth]  = '0;\n    assign unused_counter_load                 = counter_load[63:CounterWidth];\n  end else begin : g_counter_full\n    assign counter           = counter_q;\n    if (ProvideValUpd) begin : g_counter_val_upd_o\n      assign counter_val_upd_o = counter_upd;\n    end else begin : g_no_counter_val_upd_o\n      assign counter_val_upd_o = '0;\n    end\n  end\n  assign counter_val_o = counter;\nendmodule\n// Keep helper defines file-local.\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Control and Status Registers\n *\n * Control and Status Registers (CSRs) following the RISC-V Privileged\n * Specification, draft version 1.11\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n // PRIM_ASSERT_SV\nmodule cve2_cs_registers #(\n  parameter bit               DbgTriggerEn      = 0,\n  parameter int unsigned      DbgHwBreakNum     = 1,\n  parameter int unsigned      MHPMCounterNum    = 10,\n  parameter int unsigned      MHPMCounterWidth  = 40,\n  parameter bit               PMPEnable         = 0,\n  parameter int unsigned      PMPGranularity    = 0,\n  parameter int unsigned      PMPNumRegions     = 4,\n  parameter bit               RV32E             = 0,\n  parameter cve2_pkg::rv32m_e RV32M             = cve2_pkg::RV32MFast,\n  parameter cve2_pkg::rv32b_e RV32B             = cve2_pkg::RV32BNone\n) (\n  // Clock and Reset\n  input  logic                 clk_i,\n  input  logic                 rst_ni,\n  // Hart ID\n  input  logic [31:0]          hart_id_i,\n  // Privilege mode\n  output cve2_pkg::priv_lvl_e  priv_mode_id_o,\n  output cve2_pkg::priv_lvl_e  priv_mode_lsu_o,\n  output logic                 csr_mstatus_tw_o,\n  // mtvec\n  output logic [31:0]          csr_mtvec_o,\n  input  logic                 csr_mtvec_init_i,\n  input  logic [31:0]          boot_addr_i,\n  // Interface to registers (SRAM like)\n  input  logic                 csr_access_i,\n  input  cve2_pkg::csr_num_e   csr_addr_i,\n  input  logic [31:0]          csr_wdata_i,\n  input  cve2_pkg::csr_op_e    csr_op_i,\n  input                        csr_op_en_i,\n  output logic [31:0]          csr_rdata_o,\n  // interrupts\n  input  logic                 irq_software_i,\n  input  logic                 irq_timer_i,\n  input  logic                 irq_external_i,\n  input  logic [15:0]          irq_fast_i,\n  input  logic                 nmi_mode_i,\n  output logic                 irq_pending_o,          // interrupt request pending\n  output cve2_pkg::irqs_t      irqs_o,                 // interrupt requests qualified with mie\n  output logic                 csr_mstatus_mie_o,\n  output logic [31:0]          csr_mepc_o,\n  // PMP\n  output cve2_pkg::pmp_cfg_t     csr_pmp_cfg_o  [PMPNumRegions],\n  output logic [33:0]            csr_pmp_addr_o [PMPNumRegions],\n  output cve2_pkg::pmp_mseccfg_t csr_pmp_mseccfg_o,\n  // debug\n  input  logic                 debug_mode_i,\n  input  cve2_pkg::dbg_cause_e debug_cause_i,\n  input  logic                 debug_csr_save_i,\n  output logic [31:0]          csr_depc_o,\n  output logic                 debug_single_step_o,\n  output logic                 debug_ebreakm_o,\n  output logic                 debug_ebreaku_o,\n  output logic                 trigger_match_o,\n  input  logic [31:0]          pc_if_i,\n  input  logic [31:0]          pc_id_i,\n  // Exception save/restore\n  input  logic                 csr_save_if_i,\n  input  logic                 csr_save_id_i,\n  input  logic                 csr_restore_mret_i,\n  input  logic                 csr_restore_dret_i,\n  input  logic                 csr_save_cause_i,\n  input  cve2_pkg::exc_cause_e csr_mcause_i,\n  input  logic [31:0]          csr_mtval_i,\n  output logic                 illegal_csr_insn_o,     // access to non-existent CSR,\n                                                        // with wrong priviledge level, or\n                                                        // missing write permissions\n  // Performance Counters\n  input  logic                 instr_ret_i,                 // instr retired in ID/EX stage\n  input  logic                 instr_ret_compressed_i,      // compressed instr retired\n  input  logic                 iside_wait_i,                // core waiting for the iside\n  input  logic                 jump_i,                      // jump instr seen (j, jr, jal, jalr)\n  input  logic                 branch_i,                    // branch instr seen (bf, bnf)\n  input  logic                 branch_taken_i,              // branch was taken\n  input  logic                 mem_load_i,                  // load from memory in this cycle\n  input  logic                 mem_store_i,                 // store to memory in this cycle\n  input  logic                 dside_wait_i,                // core waiting for the dside\n  input  logic                 wfi_wait_i,                  // core waiting for interrupt\n  input  logic                 div_wait_i                   // core waiting for divide\n);\nimport cve2_pkg::*;\n  localparam int unsigned RV32BEnabled = (RV32B == RV32BNone) ? 0 : 1;\n  localparam int unsigned RV32MEnabled = (RV32M == RV32MNone) ? 0 : 1;\n  localparam int unsigned PMPAddrWidth = (PMPGranularity > 0) ? 33 - PMPGranularity : 32;\n  // misa\n  localparam logic [31:0] MISA_VALUE =\n      (0                 <<  0)  // A - Atomic Instructions extension\n    | (RV32BEnabled      <<  1)  // B - Bit-Manipulation extension\n    | (1                 <<  2)  // C - Compressed extension\n    | (0                 <<  3)  // D - Double precision floating-point extension\n    | (32'(RV32E)        <<  4)  // E - RV32E base ISA\n    | (0                 <<  5)  // F - Single precision floating-point extension\n    | (32'(!RV32E)       <<  8)  // I - RV32I/64I/128I base ISA\n    | (RV32MEnabled      << 12)  // M - Integer Multiply/Divide extension\n    | (0                 << 13)  // N - User level interrupts supported\n    | (0                 << 18)  // S - Supervisor mode implemented\n    | (1                 << 20)  // U - User mode implemented\n    | (0                 << 23)  // X - Non-standard extensions present\n    | (32'(CSR_MISA_MXL) << 30); // M-XLEN\n  typedef struct packed {\n    logic      mie;\n    logic      mpie;\n    priv_lvl_e mpp;\n    logic      mprv;\n    logic      tw;\n  } status_t;\n  typedef struct packed {\n    logic      mpie;\n    priv_lvl_e mpp;\n  } status_stk_t;\n  typedef struct packed {\n      x_debug_ver_e xdebugver;\n      logic [11:0]  zero2;\n      logic         ebreakm;\n      logic         zero1;\n      logic         ebreaks;\n      logic         ebreaku;\n      logic         stepie;\n      logic         stopcount;\n      logic         stoptime;\n      dbg_cause_e   cause;\n      logic         zero0;\n      logic         mprven;\n      logic         nmip;\n      logic         step;\n      priv_lvl_e    prv;\n  } dcsr_t;\n  // Interrupt and exception control signals\n  logic [31:0] exception_pc;\n  // CSRs\n  priv_lvl_e   priv_lvl_q, priv_lvl_d;\n  status_t     mstatus_q, mstatus_d;\n  logic        mstatus_en;\n  irqs_t       mie_q, mie_d;\n  logic        mie_en;\n  logic [31:0] mscratch_q;\n  logic        mscratch_en;\n  logic [31:0] mepc_q, mepc_d;\n  logic        mepc_en;\n  logic  [6:0] mcause_q, mcause_d;\n  logic        mcause_en;\n  logic [31:0] mtval_q, mtval_d;\n  logic        mtval_en;\n  logic [31:0] mtvec_q, mtvec_d;\n  logic        mtvec_en;\n  irqs_t       mip;\n  dcsr_t       dcsr_q, dcsr_d;\n  logic        dcsr_en;\n  logic [31:0] depc_q, depc_d;\n  logic        depc_en;\n  logic [31:0] dscratch0_q;\n  logic [31:0] dscratch1_q;\n  logic        dscratch0_en, dscratch1_en;\n  // CSRs for recoverable NMIs\n  // NOTE: these CSRS are nonstandard, see https://github.com/riscv/riscv-isa-manual/issues/261\n  status_stk_t mstack_q, mstack_d;\n  logic        mstack_en;\n  logic [31:0] mstack_epc_q, mstack_epc_d;\n  logic  [6:0] mstack_cause_q, mstack_cause_d;\n  // PMP Signals\n  logic [31:0]                 pmp_addr_rdata  [PMP_MAX_REGIONS];\n  logic [PMP_CFG_W-1:0]        pmp_cfg_rdata   [PMP_MAX_REGIONS];\n  pmp_mseccfg_t                pmp_mseccfg;\n  // Hardware performance monitor signals\n  logic [31:0]                 mcountinhibit;\n  // Only have mcountinhibit flops for counters that actually exist\n  logic [MHPMCounterNum+3-1:0] mcountinhibit_d, mcountinhibit_q;\n  logic                        mcountinhibit_we;\n  // mhpmcounter flops are elaborated below providing only the precise number that is required based\n  // on MHPMCounterNum/MHPMCounterWidth. This signal connects to the Q output of these flops\n  // where they exist and is otherwise 0.\n  logic [63:0] mhpmcounter [32];\n  logic [31:0] mhpmcounter_we;\n  logic [31:0] mhpmcounterh_we;\n  logic [31:0] mhpmcounter_incr;\n  logic [31:0] mhpmevent [32];\n  logic  [4:0] mhpmcounter_idx;\n  logic        unused_mhpmcounter_we_1;\n  logic        unused_mhpmcounterh_we_1;\n  logic        unused_mhpmcounter_incr_1;\n  logic [63:0] minstret_raw;\n  // Debug / trigger registers\n  logic [31:0] tselect_rdata;\n  logic [31:0] tmatch_control_rdata;\n  logic [31:0] tmatch_value_rdata;\n  // CSR update logic\n  logic [31:0] csr_wdata_int;\n  logic [31:0] csr_rdata_int;\n  logic        csr_we_int;\n  logic        csr_wr;\n  // Access violation signals\n  logic        illegal_csr;\n  logic        illegal_csr_priv;\n  logic        illegal_csr_write;\n  logic [7:0]  unused_boot_addr;\n  logic [2:0]  unused_csr_addr;\n  assign unused_boot_addr = boot_addr_i[7:0];\n  /////////////\n  // CSR reg //\n  /////////////\n  logic [$bits(csr_num_e)-1:0] csr_addr;\n  assign csr_addr           = {csr_addr_i};\n  assign unused_csr_addr    = csr_addr[7:5];\n  assign mhpmcounter_idx    = csr_addr[4:0];\n  // See RISC-V Privileged Specification, version 1.11, Section 2.1\n  assign illegal_csr_priv   = (csr_addr[9:8] > {priv_lvl_q});\n  assign illegal_csr_write  = (csr_addr[11:10] == 2'b11) && csr_wr;\n  assign illegal_csr_insn_o = csr_access_i & (illegal_csr | illegal_csr_write | illegal_csr_priv);\n  // mip CSR is purely combinational - must be able to re-enable the clock upon WFI\n  assign mip.irq_software = irq_software_i;\n  assign mip.irq_timer    = irq_timer_i;\n  assign mip.irq_external = irq_external_i;\n  assign mip.irq_fast     = irq_fast_i;\n  // read logic\n  always_comb begin\n    csr_rdata_int = '0;\n    illegal_csr   = 1'b0;\n    unique case (csr_addr_i)\n      // mvendorid: encoding of manufacturer/provider\n      CSR_MVENDORID: csr_rdata_int = CSR_MVENDORID_VALUE;\n      // marchid: encoding of base microarchitecture\n      CSR_MARCHID: csr_rdata_int = CSR_MARCHID_VALUE;\n      // mimpid: encoding of processor implementation version\n      CSR_MIMPID: csr_rdata_int = CSR_MIMPID_VALUE;\n      // mhartid: unique hardware thread id\n      CSR_MHARTID: csr_rdata_int = hart_id_i;\n      // mconfigptr: pointer to configuration data structre\n      CSR_MCONFIGPTR: csr_rdata_int = CSR_MCONFIGPTR_VALUE;\n      // mstatus: always M-mode, contains IE bit\n      CSR_MSTATUS: begin\n        csr_rdata_int                                                   = '0;\n        csr_rdata_int[CSR_MSTATUS_MIE_BIT]                              = mstatus_q.mie;\n        csr_rdata_int[CSR_MSTATUS_MPIE_BIT]                             = mstatus_q.mpie;\n        csr_rdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q.mpp;\n        csr_rdata_int[CSR_MSTATUS_MPRV_BIT]                             = mstatus_q.mprv;\n        csr_rdata_int[CSR_MSTATUS_TW_BIT]                               = mstatus_q.tw;\n      end\n      // mstatush: All zeros for CVE2 (fixed little endian and all other bits reserved)\n      CSR_MSTATUSH: csr_rdata_int = '0;\n      // menvcfg: machine environment configuration, all zeros for CVE2 (none of the relevant\n      // features are implemented)\n      CSR_MENVCFG, CSR_MENVCFGH: csr_rdata_int = '0;\n      // misa\n      CSR_MISA: csr_rdata_int = MISA_VALUE;\n      // interrupt enable\n      CSR_MIE: begin\n        csr_rdata_int                                     = '0;\n        csr_rdata_int[CSR_MSIX_BIT]                       = mie_q.irq_software;\n        csr_rdata_int[CSR_MTIX_BIT]                       = mie_q.irq_timer;\n        csr_rdata_int[CSR_MEIX_BIT]                       = mie_q.irq_external;\n        csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mie_q.irq_fast;\n      end\n      // mcounteren: machine counter enable\n      CSR_MCOUNTEREN: begin\n        csr_rdata_int = '0;\n      end\n      CSR_MSCRATCH: csr_rdata_int = mscratch_q;\n      // mtvec: trap-vector base address\n      CSR_MTVEC: csr_rdata_int = mtvec_q;\n      // mepc: exception program counter\n      CSR_MEPC: csr_rdata_int = mepc_q;\n      // mcause: exception cause\n      CSR_MCAUSE: csr_rdata_int = {mcause_q[6], 25'b0, mcause_q[5:0]};\n      // mtval: trap value\n      CSR_MTVAL: csr_rdata_int = mtval_q;\n      // mip: interrupt pending\n      CSR_MIP: begin\n        csr_rdata_int                                     = '0;\n        csr_rdata_int[CSR_MSIX_BIT]                       = mip.irq_software;\n        csr_rdata_int[CSR_MTIX_BIT]                       = mip.irq_timer;\n        csr_rdata_int[CSR_MEIX_BIT]                       = mip.irq_external;\n        csr_rdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = mip.irq_fast;\n      end\n      CSR_MSECCFG: begin\n        if (PMPEnable) begin\n          csr_rdata_int                       = '0;\n          csr_rdata_int[CSR_MSECCFG_MML_BIT]  = pmp_mseccfg.mml;\n          csr_rdata_int[CSR_MSECCFG_MMWP_BIT] = pmp_mseccfg.mmwp;\n          csr_rdata_int[CSR_MSECCFG_RLB_BIT]  = pmp_mseccfg.rlb;\n        end else begin\n          illegal_csr = 1'b1;\n        end\n      end\n      CSR_MSECCFGH: begin\n        if (PMPEnable) begin\n          csr_rdata_int = '0;\n        end else begin\n          illegal_csr = 1'b1;\n        end\n      end\n      // PMP registers\n      CSR_PMPCFG0:   csr_rdata_int = {pmp_cfg_rdata[3],  pmp_cfg_rdata[2],\n                                      pmp_cfg_rdata[1],  pmp_cfg_rdata[0]};\n      CSR_PMPCFG1:   csr_rdata_int = {pmp_cfg_rdata[7],  pmp_cfg_rdata[6],\n                                      pmp_cfg_rdata[5],  pmp_cfg_rdata[4]};\n      CSR_PMPCFG2:   csr_rdata_int = {pmp_cfg_rdata[11], pmp_cfg_rdata[10],\n                                      pmp_cfg_rdata[9],  pmp_cfg_rdata[8]};\n      CSR_PMPCFG3:   csr_rdata_int = {pmp_cfg_rdata[15], pmp_cfg_rdata[14],\n                                      pmp_cfg_rdata[13], pmp_cfg_rdata[12]};\n      CSR_PMPADDR0:  csr_rdata_int = pmp_addr_rdata[0];\n      CSR_PMPADDR1:  csr_rdata_int = pmp_addr_rdata[1];\n      CSR_PMPADDR2:  csr_rdata_int = pmp_addr_rdata[2];\n      CSR_PMPADDR3:  csr_rdata_int = pmp_addr_rdata[3];\n      CSR_PMPADDR4:  csr_rdata_int = pmp_addr_rdata[4];\n      CSR_PMPADDR5:  csr_rdata_int = pmp_addr_rdata[5];\n      CSR_PMPADDR6:  csr_rdata_int = pmp_addr_rdata[6];\n      CSR_PMPADDR7:  csr_rdata_int = pmp_addr_rdata[7];\n      CSR_PMPADDR8:  csr_rdata_int = pmp_addr_rdata[8];\n      CSR_PMPADDR9:  csr_rdata_int = pmp_addr_rdata[9];\n      CSR_PMPADDR10: csr_rdata_int = pmp_addr_rdata[10];\n      CSR_PMPADDR11: csr_rdata_int = pmp_addr_rdata[11];\n      CSR_PMPADDR12: csr_rdata_int = pmp_addr_rdata[12];\n      CSR_PMPADDR13: csr_rdata_int = pmp_addr_rdata[13];\n      CSR_PMPADDR14: csr_rdata_int = pmp_addr_rdata[14];\n      CSR_PMPADDR15: csr_rdata_int = pmp_addr_rdata[15];\n      CSR_DCSR: begin\n        csr_rdata_int = dcsr_q;\n        illegal_csr = ~debug_mode_i;\n      end\n      CSR_DPC: begin\n        csr_rdata_int = depc_q;\n        illegal_csr = ~debug_mode_i;\n      end\n      CSR_DSCRATCH0: begin\n        csr_rdata_int = dscratch0_q;\n        illegal_csr = ~debug_mode_i;\n      end\n      CSR_DSCRATCH1: begin\n        csr_rdata_int = dscratch1_q;\n        illegal_csr = ~debug_mode_i;\n      end\n      // machine counter/timers\n      CSR_MCOUNTINHIBIT: csr_rdata_int = mcountinhibit;\n      CSR_MHPMEVENT3,\n      CSR_MHPMEVENT4,  CSR_MHPMEVENT5,  CSR_MHPMEVENT6,  CSR_MHPMEVENT7,\n      CSR_MHPMEVENT8,  CSR_MHPMEVENT9,  CSR_MHPMEVENT10, CSR_MHPMEVENT11,\n      CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15,\n      CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19,\n      CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23,\n      CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27,\n      CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT30, CSR_MHPMEVENT31: begin\n        csr_rdata_int = mhpmevent[mhpmcounter_idx];\n      end\n      CSR_MCYCLE,\n      CSR_MINSTRET,\n      CSR_MHPMCOUNTER3,\n      CSR_MHPMCOUNTER4,  CSR_MHPMCOUNTER5,  CSR_MHPMCOUNTER6,  CSR_MHPMCOUNTER7,\n      CSR_MHPMCOUNTER8,  CSR_MHPMCOUNTER9,  CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11,\n      CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15,\n      CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19,\n      CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23,\n      CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27,\n      CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin\n        csr_rdata_int = mhpmcounter[mhpmcounter_idx][31:0];\n      end\n      CSR_MCYCLEH,\n      CSR_MINSTRETH,\n      CSR_MHPMCOUNTER3H,\n      CSR_MHPMCOUNTER4H,  CSR_MHPMCOUNTER5H,  CSR_MHPMCOUNTER6H,  CSR_MHPMCOUNTER7H,\n      CSR_MHPMCOUNTER8H,  CSR_MHPMCOUNTER9H,  CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H,\n      CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H,\n      CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H,\n      CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H,\n      CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H,\n      CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin\n        csr_rdata_int = mhpmcounter[mhpmcounter_idx][63:32];\n      end\n      // Debug triggers\n      CSR_TSELECT: begin\n        csr_rdata_int = tselect_rdata;\n        illegal_csr   = ~DbgTriggerEn;\n      end\n      CSR_TDATA1: begin\n        csr_rdata_int = tmatch_control_rdata;\n        illegal_csr   = ~DbgTriggerEn;\n      end\n      CSR_TDATA2: begin\n        csr_rdata_int = tmatch_value_rdata;\n        illegal_csr   = ~DbgTriggerEn;\n      end\n      CSR_TDATA3: begin\n        csr_rdata_int = '0;\n        illegal_csr   = ~DbgTriggerEn;\n      end\n      CSR_MCONTEXT: begin\n        csr_rdata_int = '0;\n        illegal_csr   = ~DbgTriggerEn;\n      end\n      CSR_SCONTEXT: begin\n        csr_rdata_int = '0;\n        illegal_csr   = ~DbgTriggerEn;\n      end\n      // Custom CSR for LFSR re-seeding (cannot be read)\n      CSR_SECURESEED: begin\n        csr_rdata_int = '0;\n      end\n      default: begin\n        illegal_csr = 1'b1;\n      end\n    endcase\n    if (!PMPEnable) begin\n      if (csr_addr inside {CSR_PMPCFG0,   CSR_PMPCFG1,   CSR_PMPCFG2,   CSR_PMPCFG3,\n                           CSR_PMPADDR0,  CSR_PMPADDR1,  CSR_PMPADDR2,  CSR_PMPADDR3,\n                           CSR_PMPADDR4,  CSR_PMPADDR5,  CSR_PMPADDR6,  CSR_PMPADDR7,\n                           CSR_PMPADDR8,  CSR_PMPADDR9,  CSR_PMPADDR10, CSR_PMPADDR11,\n                           CSR_PMPADDR12, CSR_PMPADDR13, CSR_PMPADDR14, CSR_PMPADDR15}) begin\n        illegal_csr = 1'b1;\n      end\n    end\n  end\n  // write logic\n  always_comb begin\n    exception_pc = pc_id_i;\n    priv_lvl_d   = priv_lvl_q;\n    mstatus_en   = 1'b0;\n    mstatus_d    = mstatus_q;\n    mie_en       = 1'b0;\n    mscratch_en  = 1'b0;\n    mepc_en      = 1'b0;\n    mepc_d       = {csr_wdata_int[31:1], 1'b0};\n    mcause_en    = 1'b0;\n    mcause_d     = {csr_wdata_int[31], csr_wdata_int[5:0]};\n    mtval_en     = 1'b0;\n    mtval_d      = csr_wdata_int;\n    mtvec_en     = csr_mtvec_init_i;\n    // mtvec.MODE set to vectored\n    // mtvec.BASE must be 256-byte aligned\n    mtvec_d      = csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b0, 2'b01} :\n                                      {csr_wdata_int[31:8], 6'b0, 2'b01};\n    dcsr_en      = 1'b0;\n    dcsr_d       = dcsr_q;\n    depc_d       = {csr_wdata_int[31:1], 1'b0};\n    depc_en      = 1'b0;\n    dscratch0_en = 1'b0;\n    dscratch1_en = 1'b0;\n    mstack_en      = 1'b0;\n    mstack_d.mpie  = mstatus_q.mpie;\n    mstack_d.mpp   = mstatus_q.mpp;\n    mstack_epc_d   = mepc_q;\n    mstack_cause_d = mcause_q;\n    mcountinhibit_we = 1'b0;\n    mhpmcounter_we   = '0;\n    mhpmcounterh_we  = '0;\n    if (csr_we_int) begin\n      unique case (csr_addr_i)\n        // mstatus: IE bit\n        CSR_MSTATUS: begin\n          mstatus_en = 1'b1;\n          mstatus_d    = '{\n              mie:  csr_wdata_int[CSR_MSTATUS_MIE_BIT],\n              mpie: csr_wdata_int[CSR_MSTATUS_MPIE_BIT],\n              mpp:  priv_lvl_e'(csr_wdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW]),\n              mprv: csr_wdata_int[CSR_MSTATUS_MPRV_BIT],\n              tw:   csr_wdata_int[CSR_MSTATUS_TW_BIT]\n          };\n          // Convert illegal values to M-mode\n          if ((mstatus_d.mpp != PRIV_LVL_M) && (mstatus_d.mpp != PRIV_LVL_U)) begin\n            mstatus_d.mpp = PRIV_LVL_M;\n          end\n        end\n        // interrupt enable\n        CSR_MIE: mie_en = 1'b1;\n        CSR_MSCRATCH: mscratch_en = 1'b1;\n        // mepc: exception program counter\n        CSR_MEPC: mepc_en = 1'b1;\n        // mcause\n        CSR_MCAUSE: mcause_en = 1'b1;\n        // mtval: trap value\n        CSR_MTVAL: mtval_en = 1'b1;\n        // mtvec\n        CSR_MTVEC: mtvec_en = 1'b1;\n        CSR_DCSR: begin\n          dcsr_d = csr_wdata_int;\n          dcsr_d.xdebugver = XDEBUGVER_STD;\n          // Change to PRIV_LVL_M if software writes an unsupported value\n          if ((dcsr_d.prv != PRIV_LVL_M) && (dcsr_d.prv != PRIV_LVL_U)) begin\n            dcsr_d.prv = PRIV_LVL_M;\n          end\n          // Read-only for SW\n          dcsr_d.cause = dcsr_q.cause;\n          // Interrupts always disabled during single stepping\n          dcsr_d.stepie = 1'b0;\n          // currently not supported:\n          dcsr_d.nmip = 1'b0;\n          dcsr_d.mprven = 1'b0;\n          dcsr_d.stopcount = 1'b0;\n          dcsr_d.stoptime = 1'b0;\n          // forced to be zero\n          dcsr_d.zero0 = 1'b0;\n          dcsr_d.zero1 = 1'b0;\n          dcsr_d.zero2 = 12'h0;\n          dcsr_en      = 1'b1;\n        end\n        // dpc: debug program counter\n        CSR_DPC: depc_en = 1'b1;\n        CSR_DSCRATCH0: dscratch0_en = 1'b1;\n        CSR_DSCRATCH1: dscratch1_en = 1'b1;\n        // machine counter/timers\n        CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1;\n        CSR_MCYCLE,\n        CSR_MINSTRET,\n        CSR_MHPMCOUNTER3,\n        CSR_MHPMCOUNTER4,  CSR_MHPMCOUNTER5,  CSR_MHPMCOUNTER6,  CSR_MHPMCOUNTER7,\n        CSR_MHPMCOUNTER8,  CSR_MHPMCOUNTER9,  CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11,\n        CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15,\n        CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19,\n        CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23,\n        CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27,\n        CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31: begin\n          mhpmcounter_we[mhpmcounter_idx] = 1'b1;\n        end\n        CSR_MCYCLEH,\n        CSR_MINSTRETH,\n        CSR_MHPMCOUNTER3H,\n        CSR_MHPMCOUNTER4H,  CSR_MHPMCOUNTER5H,  CSR_MHPMCOUNTER6H,  CSR_MHPMCOUNTER7H,\n        CSR_MHPMCOUNTER8H,  CSR_MHPMCOUNTER9H,  CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11H,\n        CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15H,\n        CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19H,\n        CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23H,\n        CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27H,\n        CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31H: begin\n          mhpmcounterh_we[mhpmcounter_idx] = 1'b1;\n        end\n        default:;\n      endcase\n    end\n    // exception controller gets priority over other writes\n    unique case (1'b1)\n      csr_save_cause_i: begin\n        unique case (1'b1)\n          csr_save_if_i: begin\n            exception_pc = pc_if_i;\n          end\n          csr_save_id_i: begin\n            exception_pc = pc_id_i;\n          end\n          default:;\n        endcase\n        // Any exception, including debug mode, causes a switch to M-mode\n        priv_lvl_d = PRIV_LVL_M;\n        if (debug_csr_save_i) begin\n          // all interrupts are masked\n          // do not update cause, epc, tval, epc and status\n          dcsr_d.prv   = priv_lvl_q;\n          dcsr_d.cause = debug_cause_i;\n          dcsr_en      = 1'b1;\n          depc_d       = exception_pc;\n          depc_en      = 1'b1;\n        end else if (!debug_mode_i) begin\n          // In debug mode, \"exceptions do not update any registers. That\n          // includes cause, epc, tval, dpc and mstatus.\" [Debug Spec v0.13.2, p.39]\n          mtval_en       = 1'b1;\n          mtval_d        = csr_mtval_i;\n          mstatus_en     = 1'b1;\n          mstatus_d.mie  = 1'b0; // disable interrupts\n          // save current status\n          mstatus_d.mpie = mstatus_q.mie;\n          mstatus_d.mpp  = priv_lvl_q;\n          mepc_en        = 1'b1;\n          mepc_d         = exception_pc;\n          mcause_en      = 1'b1;\n          mcause_d       = {csr_mcause_i};\n          // save previous status for recoverable NMI\n          mstack_en      = 1'b1;\n        end\n      end // csr_save_cause_i\n      csr_restore_dret_i: begin // DRET\n        priv_lvl_d = dcsr_q.prv;\n      end // csr_restore_dret_i\n      csr_restore_mret_i: begin // MRET\n        priv_lvl_d     = mstatus_q.mpp;\n        mstatus_en     = 1'b1;\n        mstatus_d.mie  = mstatus_q.mpie; // re-enable interrupts\n        if (mstatus_q.mpp != PRIV_LVL_M) begin\n          mstatus_d.mprv = 1'b0;\n        end\n        // SEC_CM: EXCEPTION.CTRL_FLOW.LOCAL_ESC\n        // SEC_CM: EXCEPTION.CTRL_FLOW.GLOBAL_ESC\n        if (nmi_mode_i) begin\n          // when returning from an NMI restore state from mstack CSR\n          mstatus_d.mpie = mstack_q.mpie;\n          mstatus_d.mpp  = mstack_q.mpp;\n          mepc_en        = 1'b1;\n          mepc_d         = mstack_epc_q;\n          mcause_en      = 1'b1;\n          mcause_d       = mstack_cause_q;\n        end else begin\n          // otherwise just set mstatus.MPIE/MPP\n          // See RISC-V Privileged Specification, version 1.11, Section 3.1.6.1\n          mstatus_d.mpie = 1'b1;\n          mstatus_d.mpp  = PRIV_LVL_U;\n        end\n      end // csr_restore_mret_i\n      default:;\n    endcase\n  end\n  // Update current priv level\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      priv_lvl_q     <= PRIV_LVL_M;\n    end else begin\n      priv_lvl_q     <= priv_lvl_d;\n    end\n  end\n  // Send current priv level to the decoder\n  assign priv_mode_id_o = priv_lvl_q;\n  // Load/store instructions must factor in MPRV for PMP checking\n  assign priv_mode_lsu_o = mstatus_q.mprv ? mstatus_q.mpp : priv_lvl_q;\n  // CSR operation logic\n  always_comb begin\n    unique case (csr_op_i)\n      CSR_OP_WRITE: csr_wdata_int =  csr_wdata_i;\n      CSR_OP_SET:   csr_wdata_int =  csr_wdata_i | csr_rdata_o;\n      CSR_OP_CLEAR: csr_wdata_int = ~csr_wdata_i & csr_rdata_o;\n      CSR_OP_READ:  csr_wdata_int = csr_wdata_i;\n      default:      csr_wdata_int = csr_wdata_i;\n    endcase\n  end\n  assign csr_wr = (csr_op_i inside {CSR_OP_WRITE, CSR_OP_SET, CSR_OP_CLEAR});\n  // only write CSRs during one clock cycle\n  assign csr_we_int  = csr_wr & csr_op_en_i & ~illegal_csr_insn_o;\n  assign csr_rdata_o = csr_rdata_int;\n  // directly output some registers\n  assign csr_mepc_o  = mepc_q;\n  assign csr_depc_o  = depc_q;\n  assign csr_mtvec_o = mtvec_q;\n  assign csr_mstatus_mie_o   = mstatus_q.mie;\n  assign csr_mstatus_tw_o    = mstatus_q.tw;\n  assign debug_single_step_o = dcsr_q.step;\n  assign debug_ebreakm_o     = dcsr_q.ebreakm;\n  assign debug_ebreaku_o     = dcsr_q.ebreaku;\n  // Qualify incoming interrupt requests in mip CSR with mie CSR for controller and to re-enable\n  // clock upon WFI (must be purely combinational).\n  assign irqs_o        = mip & mie_q;\n  assign irq_pending_o = |irqs_o;\n  ////////////////////////\n  // CSR instantiations //\n  ////////////////////////\n  // MSTATUS\n  localparam status_t MSTATUS_RST_VAL = '{mie:  1'b0,\n                                          mpie: 1'b0,\n                                          mpp:  PRIV_LVL_M,\n                                          mprv: 1'b0,\n                                          tw:   1'b0};\n  cve2_csr #(\n    .Width     ($bits(status_t)),\n    .ResetValue({MSTATUS_RST_VAL})\n  ) u_mstatus_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i ({mstatus_d}),\n    .wr_en_i   (mstatus_en),\n    .rd_data_o (mstatus_q),\n    .rd_error_o()\n  );\n  // MEPC\n  cve2_csr #(\n    .Width     (32),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_mepc_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (mepc_d),\n    .wr_en_i   (mepc_en),\n    .rd_data_o (mepc_q),\n    .rd_error_o()\n  );\n  // MIE\n  assign mie_d.irq_software = csr_wdata_int[CSR_MSIX_BIT];\n  assign mie_d.irq_timer    = csr_wdata_int[CSR_MTIX_BIT];\n  assign mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT];\n  assign mie_d.irq_fast     = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW];\n  cve2_csr #(\n    .Width     ($bits(irqs_t)),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_mie_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i ({mie_d}),\n    .wr_en_i   (mie_en),\n    .rd_data_o (mie_q),\n    .rd_error_o()\n  );\n  // MSCRATCH\n  cve2_csr #(\n    .Width     (32),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_mscratch_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (csr_wdata_int),\n    .wr_en_i   (mscratch_en),\n    .rd_data_o (mscratch_q),\n    .rd_error_o()\n  );\n  // MCAUSE\n  cve2_csr #(\n    .Width     (7),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_mcause_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (mcause_d),\n    .wr_en_i   (mcause_en),\n    .rd_data_o (mcause_q),\n    .rd_error_o()\n  );\n  // MTVAL\n  cve2_csr #(\n    .Width     (32),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_mtval_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (mtval_d),\n    .wr_en_i   (mtval_en),\n    .rd_data_o (mtval_q),\n    .rd_error_o()\n  );\n  // MTVEC\n  cve2_csr #(\n    .Width     (32),\n    .ResetValue(32'd1)\n  ) u_mtvec_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (mtvec_d),\n    .wr_en_i   (mtvec_en),\n    .rd_data_o (mtvec_q),\n    .rd_error_o()\n  );\n  // DCSR\n  localparam dcsr_t DCSR_RESET_VAL = '{\n      xdebugver: XDEBUGVER_STD,\n      cause: DBG_CAUSE_NONE,  // 3'h0\n      prv: PRIV_LVL_M,\n      default: '0\n  };\n  cve2_csr #(\n    .Width     ($bits(dcsr_t)),\n    .ShadowCopy(1'b0),\n    .ResetValue({DCSR_RESET_VAL})\n  ) u_dcsr_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i ({dcsr_d}),\n    .wr_en_i   (dcsr_en),\n    .rd_data_o (dcsr_q),\n    .rd_error_o()\n  );\n  // DEPC\n  cve2_csr #(\n    .Width     (32),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_depc_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (depc_d),\n    .wr_en_i   (depc_en),\n    .rd_data_o (depc_q),\n    .rd_error_o()\n  );\n  // DSCRATCH0\n  cve2_csr #(\n    .Width     (32),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_dscratch0_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (csr_wdata_int),\n    .wr_en_i   (dscratch0_en),\n    .rd_data_o (dscratch0_q),\n    .rd_error_o()\n  );\n  // DSCRATCH1\n  cve2_csr #(\n    .Width     (32),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_dscratch1_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (csr_wdata_int),\n    .wr_en_i   (dscratch1_en),\n    .rd_data_o (dscratch1_q),\n    .rd_error_o()\n  );\n  // MSTACK\n  localparam status_stk_t MSTACK_RESET_VAL = '{mpie: 1'b1, mpp: PRIV_LVL_U};\n  cve2_csr #(\n    .Width     ($bits(status_stk_t)),\n    .ShadowCopy(1'b0),\n    .ResetValue({MSTACK_RESET_VAL})\n  ) u_mstack_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i ({mstack_d}),\n    .wr_en_i   (mstack_en),\n    .rd_data_o (mstack_q),\n    .rd_error_o()\n  );\n  // MSTACK_EPC\n  cve2_csr #(\n    .Width     (32),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_mstack_epc_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (mstack_epc_d),\n    .wr_en_i   (mstack_en),\n    .rd_data_o (mstack_epc_q),\n    .rd_error_o()\n  );\n  // MSTACK_CAUSE\n  cve2_csr #(\n    .Width     (7),\n    .ShadowCopy(1'b0),\n    .ResetValue('0)\n  ) u_mstack_cause_csr (\n    .clk_i     (clk_i),\n    .rst_ni    (rst_ni),\n    .wr_data_i (mstack_cause_d),\n    .wr_en_i   (mstack_en),\n    .rd_data_o (mstack_cause_q),\n    .rd_error_o()\n  );\n  // -----------------\n  // PMP registers\n  // -----------------\n  if (PMPEnable) begin : g_pmp_registers\n    // PMP reset values\n       // Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Default reset values for PMP CSRs. Where the number of regions\n// (PMPNumRegions) is less than 16 the reset values for the higher numbered\n// regions are ignored.\n//\n// See the CVE2 Reference Guide (Custom Reset Values under Physical Memory\n// Protection) for more information.\nlocalparam pmp_cfg_t pmp_cfg_rst[16] = '{\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 0\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 1\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 2\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 3\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 4\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 5\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 6\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 7\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 8\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 9\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 10\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 11\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 12\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 13\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}, // region 14\n  '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}  // region 15\n};\n// Addresses are given in byte granularity for readibility. A minimum of two\n// bits will be stripped off the bottom (PMPGranularity == 0) with more stripped\n// off at coarser granularities.\nlocalparam [33:0] pmp_addr_rst[16] = '{\n  34'h0, // region 0\n  34'h0, // region 1\n  34'h0, // region 2\n  34'h0, // region 3\n  34'h0, // region 4\n  34'h0, // region 5\n  34'h0, // region 6\n  34'h0, // region 7\n  34'h0, // region 8\n  34'h0, // region 9\n  34'h0, // region 10\n  34'h0, // region 11\n  34'h0, // region 12\n  34'h0, // region 13\n  34'h0, // region 14\n  34'h0  // region 15\n};\nlocalparam pmp_mseccfg_t pmp_mseccfg_rst = '{rlb : 1'b0, mmwp: 1'b0, mml: 1'b0};\n    pmp_mseccfg_t                pmp_mseccfg_q, pmp_mseccfg_d;\n    logic                        pmp_mseccfg_we;\n    logic                        pmp_mseccfg_err;\n    pmp_cfg_t                    pmp_cfg         [PMPNumRegions];\n    logic [PMPNumRegions-1:0]    pmp_cfg_locked;\n    pmp_cfg_t                    pmp_cfg_wdata   [PMPNumRegions];\n    logic [PMPAddrWidth-1:0]     pmp_addr        [PMPNumRegions];\n    logic [PMPNumRegions-1:0]    pmp_cfg_we;\n    logic [PMPNumRegions-1:0]    pmp_cfg_err;\n    logic [PMPNumRegions-1:0]    pmp_addr_we;\n    logic [PMPNumRegions-1:0]    pmp_addr_err;\n    logic                        any_pmp_entry_locked;\n    // Expanded / qualified register read data\n    for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_exp_rd_data\n      if (i < PMPNumRegions) begin : g_implemented_regions\n        // Add in zero padding for reserved fields\n        assign pmp_cfg_rdata[i] = {pmp_cfg[i].lock, 2'b00, pmp_cfg[i].mode,\n                                   pmp_cfg[i].exec, pmp_cfg[i].write, pmp_cfg[i].read};\n        // Address field read data depends on the current programmed mode and the granularity\n        // See RISC-V Privileged Specification, version 1.11, Section 3.6.1\n        if (PMPGranularity == 0) begin : g_pmp_g0\n          // If G == 0, read data is unmodified\n          assign pmp_addr_rdata[i] = pmp_addr[i];\n        end else if (PMPGranularity == 1) begin : g_pmp_g1\n          // If G == 1, bit [G-1] reads as zero in TOR or OFF mode\n          always_comb begin\n            pmp_addr_rdata[i] = pmp_addr[i];\n            if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin\n              pmp_addr_rdata[i][PMPGranularity-1:0] = '0;\n            end\n          end\n        end else begin : g_pmp_g2\n          // For G >= 2, bits are masked to one or zero depending on the mode\n          always_comb begin\n            // In NAPOT mode, bits [G-2:0] must read as one\n            pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity - 1{1'b1}}};\n            if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin\n              // In TOR or OFF mode, bits [G-1:0] must read as zero\n              pmp_addr_rdata[i][PMPGranularity-1:0] = '0;\n            end\n          end\n        end\n      end else begin : g_other_regions\n        // Non-implemented regions read as zero\n        assign pmp_cfg_rdata[i]  = '0;\n        assign pmp_addr_rdata[i] = '0;\n      end\n    end\n    // Write data calculation\n    for (genvar i = 0; i < PMPNumRegions; i++) begin : g_pmp_csrs\n      // -------------------------\n      // Instantiate cfg registers\n      // -------------------------\n      assign pmp_cfg_we[i] = csr_we_int & ~pmp_cfg_locked[i] &\n                             (csr_addr == (CSR_OFF_PMP_CFG + (i[11:0] >> 2)));\n      // Select the correct WDATA (each CSR contains 4 CFG fields, each with 2 RES bits)\n      assign pmp_cfg_wdata[i].lock  = csr_wdata_int[(i%4)*PMP_CFG_W+7];\n      // NA4 mode is not selectable when G > 0, mode is treated as OFF\n      always_comb begin\n        unique case (csr_wdata_int[(i%4)*PMP_CFG_W+3+:2])\n          2'b00   : pmp_cfg_wdata[i].mode = PMP_MODE_OFF;\n          2'b01   : pmp_cfg_wdata[i].mode = PMP_MODE_TOR;\n          2'b10   : pmp_cfg_wdata[i].mode = (PMPGranularity == 0) ? PMP_MODE_NA4:\n                                                                    PMP_MODE_OFF;\n          2'b11   : pmp_cfg_wdata[i].mode = PMP_MODE_NAPOT;\n          default : pmp_cfg_wdata[i].mode = PMP_MODE_OFF;\n        endcase\n      end\n      assign pmp_cfg_wdata[i].exec  = csr_wdata_int[(i%4)*PMP_CFG_W+2];\n      // When MSECCFG.MML is unset, W = 1, R = 0 is a reserved combination, so force W to 0 if R ==\n      // 0. Otherwise allow all possible values to be written.\n      assign pmp_cfg_wdata[i].write = pmp_mseccfg_q.mml ? csr_wdata_int[(i%4)*PMP_CFG_W+1] :\n                                                          &csr_wdata_int[(i%4)*PMP_CFG_W+:2];\n      assign pmp_cfg_wdata[i].read  = csr_wdata_int[(i%4)*PMP_CFG_W];\n      cve2_csr #(\n        .Width     ($bits(pmp_cfg_t)),\n        .ResetValue(pmp_cfg_rst[i])\n      ) u_pmp_cfg_csr (\n        .clk_i     (clk_i),\n        .rst_ni    (rst_ni),\n        .wr_data_i ({pmp_cfg_wdata[i]}),\n        .wr_en_i   (pmp_cfg_we[i]),\n        .rd_data_o (pmp_cfg[i]),\n        .rd_error_o(pmp_cfg_err[i])\n      );\n      // MSECCFG.RLB allows the lock bit to be bypassed (allowing cfg writes when MSECCFG.RLB is\n      // set).\n      assign pmp_cfg_locked[i] = pmp_cfg[i].lock & ~pmp_mseccfg_q.rlb;\n      // --------------------------\n      // Instantiate addr registers\n      // --------------------------\n      if (i < PMPNumRegions - 1) begin : g_lower\n        assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg_locked[i] &\n                                (~pmp_cfg_locked[i+1] | (pmp_cfg[i+1].mode != PMP_MODE_TOR)) &\n                                (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0]));\n      end else begin : g_upper\n        assign pmp_addr_we[i] = csr_we_int & ~pmp_cfg_locked[i] &\n                                (csr_addr == (CSR_OFF_PMP_ADDR + i[11:0]));\n      end\n      cve2_csr #(\n        .Width     (PMPAddrWidth),\n        .ResetValue(pmp_addr_rst[i][33-:PMPAddrWidth])\n      ) u_pmp_addr_csr (\n        .clk_i     (clk_i),\n        .rst_ni    (rst_ni),\n        .wr_data_i (csr_wdata_int[31-:PMPAddrWidth]),\n        .wr_en_i   (pmp_addr_we[i]),\n        .rd_data_o (pmp_addr[i]),\n        .rd_error_o(pmp_addr_err[i])\n      );\n      assign csr_pmp_cfg_o[i]  = pmp_cfg[i];\n      assign csr_pmp_addr_o[i] = {pmp_addr_rdata[i], 2'b00};\n    end\n    assign pmp_mseccfg_we = csr_we_int & (csr_addr == CSR_MSECCFG);\n    // MSECCFG.MML/MSECCFG.MMWP cannot be unset once set\n    assign pmp_mseccfg_d.mml  = pmp_mseccfg_q.mml  ? 1'b1 : csr_wdata_int[CSR_MSECCFG_MML_BIT];\n    assign pmp_mseccfg_d.mmwp = pmp_mseccfg_q.mmwp ? 1'b1 : csr_wdata_int[CSR_MSECCFG_MMWP_BIT];\n    // pmp_cfg_locked factors in MSECCFG.RLB so any_pmp_entry_locked will only be set if MSECCFG.RLB\n    // is unset\n    assign any_pmp_entry_locked = |pmp_cfg_locked;\n    // When any PMP entry is locked (A PMP entry has the L bit set and MSECCFG.RLB is unset),\n    // MSECCFG.RLB cannot be set again\n    assign pmp_mseccfg_d.rlb = any_pmp_entry_locked ? 1'b0 : csr_wdata_int[CSR_MSECCFG_RLB_BIT];\n    cve2_csr #(\n      .Width     ($bits(pmp_mseccfg_t)),\n      .ResetValue(pmp_mseccfg_rst)\n    ) u_pmp_mseccfg (\n      .clk_i     (clk_i),\n      .rst_ni    (rst_ni),\n      .wr_data_i (pmp_mseccfg_d),\n      .wr_en_i   (pmp_mseccfg_we),\n      .rd_data_o (pmp_mseccfg_q),\n      .rd_error_o(pmp_mseccfg_err)\n    );\n    assign pmp_mseccfg = pmp_mseccfg_q;\n  end else begin : g_no_pmp_tieoffs\n    // Generate tieoffs when PMP is not configured\n    for (genvar i = 0; i < PMP_MAX_REGIONS; i++) begin : g_rdata\n      assign pmp_addr_rdata[i] = '0;\n      assign pmp_cfg_rdata[i]  = '0;\n    end\n    for (genvar i = 0; i < PMPNumRegions; i++) begin : g_outputs\n      assign csr_pmp_cfg_o[i]  = pmp_cfg_t'(1'b0);\n      assign csr_pmp_addr_o[i] = '0;\n    end\n    assign pmp_mseccfg = '0;\n  end\n  assign csr_pmp_mseccfg_o = pmp_mseccfg;\n  //////////////////////////\n  //  Performance monitor //\n  //////////////////////////\n  // update enable signals\n  always_comb begin : mcountinhibit_update\n    if (mcountinhibit_we == 1'b1) begin\n      // bit 1 must always be 0\n      mcountinhibit_d = {csr_wdata_int[MHPMCounterNum+2:2], 1'b0, csr_wdata_int[0]};\n    end else begin\n      mcountinhibit_d = mcountinhibit_q;\n    end\n  end\n  // event selection (hardwired) & control\n  always_comb begin : gen_mhpmcounter_incr\n    // Assign inactive counters (first to prevent latch inference)\n    for (int unsigned i = 0; i < 32; i++) begin : gen_mhpmcounter_incr_inactive\n      mhpmcounter_incr[i] = 1'b0;\n    end\n    // When adding or altering performance counter meanings and default\n    // mappings please update dv/verilator/pcount/cpp/cve2_pcounts.cc\n    // appropriately.\n    //\n    // active counters\n    mhpmcounter_incr[0]  = 1'b1;                   // mcycle\n    mhpmcounter_incr[1]  = 1'b0;                   // reserved\n    mhpmcounter_incr[2]  = instr_ret_i;            // minstret\n    mhpmcounter_incr[3]  = dside_wait_i;           // cycles waiting for data memory\n    mhpmcounter_incr[4]  = iside_wait_i;           // cycles waiting for instr fetches\n    mhpmcounter_incr[5]  = mem_load_i;             // num of loads\n    mhpmcounter_incr[6]  = mem_store_i;            // num of stores\n    mhpmcounter_incr[7]  = jump_i;                 // num of jumps (unconditional)\n    mhpmcounter_incr[8]  = branch_i;               // num of branches (conditional)\n    mhpmcounter_incr[9]  = branch_taken_i;         // num of taken branches (conditional)\n    mhpmcounter_incr[10] = instr_ret_compressed_i; // num of compressed instr\n    mhpmcounter_incr[11] = wfi_wait_i;             // cycles waiting for multiply\n    mhpmcounter_incr[12] = div_wait_i;             // cycles waiting for divide\n  end\n  // event selector (hardwired, 0 means no event)\n  always_comb begin : gen_mhpmevent\n    // activate all\n    for (int i = 0; i < 32; i++) begin : gen_mhpmevent_active\n      mhpmevent[i]    =   '0;\n      mhpmevent[i][i] = 1'b1;\n    end\n    // deactivate\n    mhpmevent[1] = '0; // not existing, reserved\n    for (int unsigned i = 3 + MHPMCounterNum; i < 32; i++) begin : gen_mhpmevent_inactive\n      mhpmevent[i] = '0;\n    end\n  end\n  // mcycle\n  cve2_counter #(\n    .CounterWidth(64)\n  ) mcycle_counter_i (\n    .clk_i(clk_i),\n    .rst_ni(rst_ni),\n    .counter_inc_i(mhpmcounter_incr[0] & ~mcountinhibit[0]),\n    .counterh_we_i(mhpmcounterh_we[0]),\n    .counter_we_i(mhpmcounter_we[0]),\n    .counter_val_i(csr_wdata_int),\n    .counter_val_o(mhpmcounter[0]),\n    .counter_val_upd_o()\n  );\n  // minstret\n  cve2_counter #(\n    .CounterWidth(64),\n    .ProvideValUpd(1)\n  ) minstret_counter_i (\n    .clk_i(clk_i),\n    .rst_ni(rst_ni),\n    .counter_inc_i(mhpmcounter_incr[2] & ~mcountinhibit[2]),\n    .counterh_we_i(mhpmcounterh_we[2]),\n    .counter_we_i(mhpmcounter_we[2]),\n    .counter_val_i(csr_wdata_int),\n    .counter_val_o(minstret_raw),\n    .counter_val_upd_o()\n  );\n  // Where the writeback stage is present instruction in ID observing value of minstret must take\n  // into account any instruction in the writeback stage. If one is present the incremented value of\n  // minstret is used. A speculative version of the signal is used to aid timing. When the writeback\n  // stage sees an exception (so the speculative signal is incorrect) the ID stage will be flushed\n  // so the incorrect value doesn't matter. A similar behaviour is required for the compressed\n  // instruction retired counter below. When the writeback stage isn't present the speculative\n  // signals are always 0.\n  assign mhpmcounter[2] = minstret_raw;\n  // reserved:\n  assign mhpmcounter[1]            = '0;\n  assign unused_mhpmcounter_we_1   = mhpmcounter_we[1];\n  assign unused_mhpmcounterh_we_1  = mhpmcounterh_we[1];\n  assign unused_mhpmcounter_incr_1 = mhpmcounter_incr[1];\n  // Iterate through optionally included counters (MHPMCounterNum controls how many are included)\n  for (genvar i = 0; i < 29; i++) begin : gen_cntrs\n    localparam int Cnt = i + 3;\n    if (i < MHPMCounterNum) begin : gen_imp\n      logic [63:0] mhpmcounter_raw, mhpmcounter_next;\n      cve2_counter #(\n        .CounterWidth(MHPMCounterWidth),\n        .ProvideValUpd(Cnt == 10)\n      ) mcounters_variable_i (\n        .clk_i(clk_i),\n        .rst_ni(rst_ni),\n        .counter_inc_i(mhpmcounter_incr[Cnt] & ~mcountinhibit[Cnt]),\n        .counterh_we_i(mhpmcounterh_we[Cnt]),\n        .counter_we_i(mhpmcounter_we[Cnt]),\n        .counter_val_i(csr_wdata_int),\n        .counter_val_o(mhpmcounter_raw),\n        .counter_val_upd_o(mhpmcounter_next)\n      );\n      if (Cnt == 10) begin : gen_compressed_instr_cnt\n        // Special behaviour for reading compressed instruction retired counter, see comment on\n        // `mhpmcounter[2]` above for further information.\n        assign mhpmcounter[Cnt] =\n                                                              mhpmcounter_raw;\n      end else begin : gen_other_cnts\n        logic [63:0] unused_mhpmcounter_next;\n        // All other counters just see the raw counter value directly.\n        assign mhpmcounter[Cnt] = mhpmcounter_raw;\n        assign unused_mhpmcounter_next = mhpmcounter_next;\n      end\n    end else begin : gen_unimp\n      assign mhpmcounter[Cnt] = '0;\n    end\n  end\n  if (MHPMCounterNum < 29) begin : g_mcountinhibit_reduced\n    logic [29-MHPMCounterNum-1:0] unused_mhphcounter_we;\n    logic [29-MHPMCounterNum-1:0] unused_mhphcounterh_we;\n    logic [29-MHPMCounterNum-1:0] unused_mhphcounter_incr;\n    assign mcountinhibit = {{29 - MHPMCounterNum{1'b1}}, mcountinhibit_q};\n    // Lint tieoffs for unused bits\n    assign unused_mhphcounter_we   = mhpmcounter_we[31:MHPMCounterNum+3];\n    assign unused_mhphcounterh_we  = mhpmcounterh_we[31:MHPMCounterNum+3];\n    assign unused_mhphcounter_incr = mhpmcounter_incr[31:MHPMCounterNum+3];\n  end else begin : g_mcountinhibit_full\n    assign mcountinhibit = mcountinhibit_q;\n  end\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      mcountinhibit_q <= '0;\n    end else begin\n      mcountinhibit_q <= mcountinhibit_d;\n    end\n  end\n  /////////////////////////////\n  // Debug trigger registers //\n  /////////////////////////////\n  if (DbgTriggerEn) begin : gen_trigger_regs\n    localparam int unsigned DbgHwNumLen = DbgHwBreakNum > 1 ? $clog2(DbgHwBreakNum) : 1;\n    localparam int unsigned MaxTselect = DbgHwBreakNum - 1;\n    // Register values\n    logic [DbgHwNumLen-1:0]   tselect_d, tselect_q;\n    logic                     tmatch_control_d;\n    logic [DbgHwBreakNum-1:0] tmatch_control_q;\n    logic [31:0]              tmatch_value_d;\n    logic [31:0]              tmatch_value_q[DbgHwBreakNum];\n    logic                     selected_tmatch_control;\n    logic [31:0]              selected_tmatch_value;\n    // Write enables\n    logic                     tselect_we;\n    logic [DbgHwBreakNum-1:0] tmatch_control_we;\n    logic [DbgHwBreakNum-1:0] tmatch_value_we;\n    // Trigger comparison result\n    logic [DbgHwBreakNum-1:0] trigger_match;\n    // Write select\n    assign tselect_we = csr_we_int & debug_mode_i & (csr_addr_i == CSR_TSELECT);\n    for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_we\n      assign tmatch_control_we[i] = (i[DbgHwNumLen-1:0] == tselect_q) & csr_we_int & debug_mode_i &\n                                    (csr_addr_i == CSR_TDATA1);\n      assign tmatch_value_we[i]   = (i[DbgHwNumLen-1:0] == tselect_q) & csr_we_int & debug_mode_i &\n                                    (csr_addr_i == CSR_TDATA2);\n    end\n    // Debug interface tests the available number of triggers by writing and reading the trigger\n    // select register. Only allow changes to the register if it is within the supported region.\n    assign tselect_d = (csr_wdata_int < DbgHwBreakNum) ? csr_wdata_int[DbgHwNumLen-1:0] :\n                                                         MaxTselect[DbgHwNumLen-1:0];\n    // tmatch_control is enabled when the execute bit is set\n    assign tmatch_control_d = csr_wdata_int[2];\n    assign tmatch_value_d   = csr_wdata_int[31:0];\n    // Registers\n    cve2_csr #(\n      .Width     (DbgHwNumLen),\n      .ShadowCopy(1'b0),\n      .ResetValue('0)\n    ) u_tselect_csr (\n      .clk_i     (clk_i),\n      .rst_ni    (rst_ni),\n      .wr_data_i (tselect_d),\n      .wr_en_i   (tselect_we),\n      .rd_data_o (tselect_q),\n      .rd_error_o()\n    );\n    for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_tmatch_reg\n      cve2_csr #(\n        .Width     (1),\n        .ShadowCopy(1'b0),\n        .ResetValue('0)\n      ) u_tmatch_control_csr (\n        .clk_i     (clk_i),\n        .rst_ni    (rst_ni),\n        .wr_data_i (tmatch_control_d),\n        .wr_en_i   (tmatch_control_we[i]),\n        .rd_data_o (tmatch_control_q[i]),\n        .rd_error_o()\n      );\n      cve2_csr #(\n        .Width     (32),\n        .ShadowCopy(1'b0),\n        .ResetValue('0)\n      ) u_tmatch_value_csr (\n        .clk_i     (clk_i),\n        .rst_ni    (rst_ni),\n        .wr_data_i (tmatch_value_d),\n        .wr_en_i   (tmatch_value_we[i]),\n        .rd_data_o (tmatch_value_q[i]),\n        .rd_error_o()\n      );\n    end\n    // Assign read data\n    // TSELECT - number of supported triggers defined by parameter DbgHwBreakNum\n    localparam int unsigned TSelectRdataPadlen = DbgHwNumLen >= 32 ? 0 : (32 - DbgHwNumLen);\n    assign tselect_rdata = {{TSelectRdataPadlen{1'b0}}, tselect_q};\n    if (DbgHwBreakNum > 1) begin : g_dbg_tmatch_multiple_select\n      assign selected_tmatch_control = tmatch_control_q[tselect_q];\n      assign selected_tmatch_value   = tmatch_value_q[tselect_q];\n    end else begin : g_dbg_tmatch_single_select\n      assign selected_tmatch_control = tmatch_control_q[0];\n      assign selected_tmatch_value   = tmatch_value_q[0];\n    end\n    // TDATA0 - only support simple address matching\n    assign tmatch_control_rdata = {4'h2,                    // type    : address/data match\n                                   1'b1,                    // dmode   : access from D mode only\n                                   6'h00,                   // maskmax : exact match only\n                                   1'b0,                    // hit     : not supported\n                                   1'b0,                    // select  : address match only\n                                   1'b0,                    // timing  : match before execution\n                                   2'b00,                   // sizelo  : match any access\n                                   4'h1,                    // action  : enter debug mode\n                                   1'b0,                    // chain   : not supported\n                                   4'h0,                    // match   : simple match\n                                   1'b1,                    // m       : match in m-mode\n                                   1'b0,                    // 0       : zero\n                                   1'b0,                    // s       : not supported\n                                   1'b1,                    // u       : match in u-mode\n                                   selected_tmatch_control, // execute : match instruction address\n                                   1'b0,                    // store   : not supported\n                                   1'b0};                   // load    : not supported\n    // TDATA1 - address match value only\n    assign tmatch_value_rdata = selected_tmatch_value;\n    // Breakpoint matching\n    // We match against the next address, as the breakpoint must be taken before execution\n    for (genvar i = 0; i < DbgHwBreakNum; i++) begin : g_dbg_trigger_match\n      assign trigger_match[i] = tmatch_control_q[i] & (pc_if_i[31:0] == tmatch_value_q[i]);\n    end\n    assign trigger_match_o = |trigger_match;\n  end else begin : gen_no_trigger_regs\n    assign tselect_rdata        = 'b0;\n    assign tmatch_control_rdata = 'b0;\n    assign tmatch_value_rdata   = 'b0;\n    assign trigger_match_o      = 'b0;\n  end\n  //////////////////////////\n  // CPU control register //\n  //////////////////////////\n  ////////////////\n  // Assertions //\n  ////////////////\nendmodule\n", "mask_idx": {"conditional_statement": [[53195, 53312], [51262, 51969], [25578, 25676], [23261, 23376], [52480, 53040], [45257, 45762], [75216, 75332], [52289, 52372], [23610, 23670], [39771, 40104], [46870, 50486], [40149, 40264]], "blocking_assignment": [[70941, 71016], [45974, 45994], [45924, 45944], [25344, 25386], [25412, 25450], [38496, 38567], [52665, 52687], [47848, 47864], [46072, 46127]], "module_program_interface_instantiation": [[57857, 58119], [55085, 55344], [58793, 59053], [73359, 73821], [59074, 59339], [55357, 55597], [58491, 58774], [55867, 56116], [56926, 57150], [56133, 56392], [71826, 72189], [57319, 57586], [71469, 71809], [56407, 56654], [57599, 57839], [58137, 58399], [56668, 56912]], "always_construct": [[23206, 23382], [69602, 71022], [71075, 71454], [69285, 69556], [24932, 25464], [53140, 53318], [25523, 25682], [53566, 53904], [36761, 45768], [75161, 75338], [45788, 53106]], "case_statement": [[36833, 45252], [46898, 50478], [50551, 53100], [50608, 50824], [53588, 53898]], "ansi_port_declaration": [[29307, 29369], [28127, 28171], [29814, 29851], [30722, 30809], [24481, 24514], [30254, 30337], [28676, 28717], [31175, 31265], [24444, 24478]], "continuous_assign": [[36576, 36617], [55727, 55783], [36705, 36742], [81148, 81182], [36325, 36390], [53469, 53538], [36150, 36192]], "parameter_declaration": [[13332, 13380], [16946, 16990], [27543, 27594], [13140, 13186], [12379, 12461], [27809, 27877], [13434, 13482], [12680, 12733], [13238, 13284], [6523, 6571], [27436, 27486], [24310, 24341]], "nonblocking_assignment": [[75289, 75324], [23347, 23368], [53275, 53304], [25645, 25668]]}, "all_mask_idx": {"module_program_interface_instantiation": [[55085, 55344], [55357, 55597], [55867, 56116], [56133, 56392], [56407, 56654], [56668, 56912], [56926, 57150], [57319, 57586], [57599, 57839], [57857, 58119], [58137, 58399], [58491, 58774], [58793, 59053], [59074, 59339], [66071, 66393], [67160, 67514], [68349, 68656], [71469, 71809], [71826, 72189], [73359, 73821], [77311, 77594], [77673, 78002], [78009, 78331]], "continuous_assign": [[23385, 23412], [23683, 23724], [23762, 23787], [24835, 24917], [25786, 25841], [25846, 25894], [25952, 26009], [26060, 26108], [26121, 26169], [26174, 26249], [26288, 26325], [26383, 26422], [26473, 26503], [26520, 26551], [35926, 35969], [36061, 36102], [36105, 36147], [36150, 36192], [36263, 36322], [36325, 36390], [36393, 36489], [36576, 36617], [36620, 36658], [36661, 36702], [36705, 36742], [53365, 53400], [53469, 53538], [53907, 53982], [54029, 54093], [54096, 54131], [54170, 54198], [54201, 54229], [54232, 54261], [54264, 54307], [54310, 54352], [54355, 54396], [54399, 54443], [54446, 54490], [54642, 54677], [54680, 54711], [55609, 55665], [55668, 55724], [55727, 55783], [55786, 55864], [62917, 63072], [63351, 63390], [64404, 64434], [64443, 64473], [64699, 64834], [64930, 64995], [65579, 65644], [65814, 65994], [66001, 66064], [66512, 66576], [66742, 66970], [67010, 67143], [67521, 67559], [67566, 67620], [67633, 67696], [67758, 67849], [67854, 67946], [68068, 68114], [68252, 68344], [68661, 68696], [68855, 68885], [68892, 68922], [69002, 69046], [69053, 69083], [69096, 69120], [69129, 69168], [72808, 72845], [72863, 72901], [72904, 72957], [72960, 73014], [73017, 73072], [74039, 74143], [74307, 74349], [74358, 74408], [74456, 74485], [74737, 74807], [74848, 74917], [74922, 74992], [74997, 75068], [75113, 75152], [76276, 76352], [76430, 76587], [76594, 76751], [76958, 77129], [77195, 77238], [77243, 77289], [78542, 78605], [78676, 78737], [78744, 78803], [78858, 78911], [78918, 78969], [79035, 80553], [80599, 80649], [80849, 80934], [80947, 80987], [81031, 81065], [81070, 81104], [81109, 81143], [81148, 81182]], "blocking_assignment": [[24967, 25001], [25006, 25043], [25048, 25084], [25120, 25156], [25163, 25199], [25256, 25299], [25344, 25386], [25412, 25450], [36783, 36802], [36807, 36828], [36933, 36969], [37042, 37076], [37157, 37190], [37254, 37280], [37363, 37400], [37483, 37552], [37561, 37641], [37650, 37731], [37740, 37820], [37829, 37910], [37919, 37998], [38117, 38136], [38299, 38318], [38349, 38376], [38432, 38487], [38496, 38567], [38576, 38644], [38653, 38724], [38733, 38800], [38891, 38910], [38941, 38968], [39027, 39051], [39109, 39132], [39184, 39236], [39281, 39305], [39367, 39422], [39431, 39500], [39509, 39575], [39584, 39653], [39662, 39727], [39802, 39843], [39854, 39908], [39919, 39974], [39985, 40039], [40073, 40092], [40180, 40199], [40233, 40252], [40319, 40448], [40470, 40599], [40621, 40751], [40773, 40904], [40926, 40960], [40982, 41016], [41038, 41072], [41094, 41128], [41150, 41184], [41206, 41240], [41262, 41296], [41318, 41352], [41374, 41408], [41430, 41464], [41486, 41521], [41543, 41578], [41600, 41635], [41657, 41692], [41714, 41749], [41771, 41806], [41837, 41860], [41869, 41897], [41937, 41960], [41969, 41997], [42043, 42071], [42080, 42108], [42154, 42182], [42191, 42219], [42287, 42317], [42871, 42914], [43574, 43625], [44316, 44368], [44436, 44466], [44475, 44505], [44548, 44585], [44594, 44624], [44667, 44702], [44711, 44741], [44784, 44803], [44812, 44842], [44887, 44906], [44915, 44945], [44990, 45009], [45018, 45048], [45152, 45171], [45211, 45230], [45725, 45744], [45810, 45833], [45838, 45864], [45869, 45889], [45894, 45919], [45924, 45944], [45949, 45969], [45974, 45994], [45999, 46042], [46047, 46067], [46072, 46127], [46132, 46152], [46157, 46186], [46191, 46223], [46305, 46447], [46452, 46472], [46477, 46499], [46504, 46547], [46552, 46572], [46577, 46597], [46602, 46622], [46627, 46649], [46654, 46686], [46691, 46722], [46727, 46751], [46756, 46782], [46787, 46811], [46816, 46838], [46843, 46865], [46987, 47005], [47016, 47368], [47511, 47538], [47610, 47624], [47647, 47666], [47728, 47743], [47782, 47799], [47848, 47864], [47901, 47917], [47952, 47975], [47986, 48019], [48184, 48208], [48263, 48291], [48365, 48386], [48435, 48454], [48465, 48486], [48497, 48521], [48532, 48555], [48597, 48617], [48628, 48648], [48659, 48680], [48691, 48711], [48779, 48794], [48818, 48838], [48862, 48882], [48944, 48968], [49640, 49679], [50394, 50434], [50670, 50693], [50751, 50774], [50907, 50931], [51077, 51103], [51114, 51143], [51154, 51174], [51185, 51213], [51224, 51244], [51456, 51478], [51489, 51518], [51529, 51551], [51562, 51606], [51650, 51681], [51692, 51720], [51731, 51753], [51764, 51794], [51805, 51827], [51838, 51870], [51935, 51957], [52048, 52072], [52153, 52184], [52193, 52215], [52224, 52280], [52338, 52360], [52582, 52613], [52624, 52654], [52665, 52687], [52698, 52728], [52739, 52761], [52772, 52804], [52967, 52989], [53000, 53028], [53631, 53660], [53681, 53724], [53745, 53788], [53809, 53837], [53858, 53886], [63557, 63589], [63698, 63741], [63984, 64046], [64223, 64266], [65169, 65206], [65227, 65264], [65285, 65428], [65449, 65488], [65509, 65546], [69404, 69482], [69508, 69542], [69796, 69823], [70030, 70086], [70091, 70149], [70154, 70212], [70217, 70297], [70302, 70384], [70389, 70451], [70456, 70519], [70524, 70602], [70607, 70686], [70691, 70776], [70781, 70854], [70859, 70936], [70941, 71016], [71197, 71220], [71227, 71250], [71281, 71325], [71422, 71440]], "nonblocking_assignment": [[23286, 23308], [23347, 23368], [23570, 23594], [23637, 23660], [25603, 25619], [25645, 25668], [53220, 53249], [53275, 53304], [75241, 75263], [75289, 75324]], "case_statement": [[36833, 45252], [46898, 50478], [50551, 53100], [50608, 50824], [53588, 53898], [65099, 65562]], "conditional_statement": [[23261, 23376], [23322, 23376], [23543, 23670], [23610, 23670], [25089, 25207], [25236, 25458], [25313, 25458], [25578, 25676], [39771, 40104], [40149, 40264], [45257, 45762], [45285, 45754], [46870, 50486], [47425, 47552], [48104, 48222], [50940, 51969], [51262, 51969], [52289, 52372], [52480, 53040], [53195, 53312], [63602, 63757], [64059, 64282], [69330, 69550], [75216, 75332]], "always_construct": [[23206, 23382], [23486, 23678], [24932, 25464], [25523, 25682], [36761, 45768], [45788, 53106], [53140, 53318], [53566, 53904], [63527, 63771], [63894, 64296], [65073, 65572], [69285, 69556], [69602, 71022], [71075, 71454], [75161, 75338]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096], [22814, 22856], [22859, 22903], [22906, 22947], [24020, 24052], [24310, 24341], [27383, 27433], [27436, 27486], [27489, 27540], [27543, 27594], [27597, 27647], [27650, 27700], [27703, 27753], [27756, 27806], [27809, 27877], [27880, 27947]], "ansi_port_declaration": [[22955, 22986], [22989, 23021], [23024, 23059], [23062, 23095], [23098, 23133], [23136, 23171], [24348, 24374], [24377, 24404], [24407, 24441], [24444, 24478], [24481, 24514], [24517, 24551], [24554, 24588], [24591, 24628], [27975, 28010], [28013, 28049], [28065, 28104], [28127, 28171], [28174, 28219], [28222, 28268], [28282, 28323], [28326, 28372], [28375, 28416], [28459, 28501], [28504, 28544], [28547, 28588], [28591, 28629], [28632, 28673], [28676, 28717], [28736, 28780], [28783, 28824], [28827, 28871], [28874, 28914], [28917, 28957], [28960, 29041], [29044, 29137], [29140, 29187], [29190, 29230], [29242, 29304], [29307, 29369], [29372, 29421], [29435, 29477], [29480, 29523], [29526, 29572], [29575, 29615], [29618, 29667], [29670, 29715], [29718, 29763], [29766, 29811], [29814, 29851], [29854, 29891], [29922, 29965], [29968, 30011], [30014, 30062], [30065, 30113], [30116, 30162], [30165, 30207], [30210, 30251], [30254, 30337], [30542, 30631], [30634, 30719], [30722, 30809], [30812, 30907], [30910, 30998], [31001, 31078], [31081, 31172], [31175, 31265], [31268, 31355], [31358, 31445], [31448, 31532]]}}
{"sample_i": "p6", "topmodule": "cve2_decoder", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Instruction decoder\n *\n * This module is fully combinatorial, clock and reset are used for\n * assertions only.\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_decoder #(\n  parameter bit RV32E               = 0,\n  parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast,\n  parameter cve2_pkg::rv32b_e RV32B = cve2_pkg::RV32BNone,\n  parameter bit               XInterface    = 1'b0\n) (\n  input  logic                 clk_i,\n  input  logic                 rst_ni,\n  // to/from controller\n  output logic                 illegal_insn_o,        // illegal instr encountered\n  output logic                 ebrk_insn_o,           // trap instr encountered\n  output logic                 mret_insn_o,           // return from exception instr\n                                                      // encountered\n  output logic                 dret_insn_o,           // return from debug instr encountered\n  output logic                 ecall_insn_o,          // syscall instr encountered\n  output logic                 wfi_insn_o,            // wait for interrupt instr encountered\n  output logic                 jump_set_o,            // jump taken set signal\n  // from IF-ID pipeline register\n  input  logic                 instr_first_cycle_i,   // instruction read is in its first cycle\n  input  logic [31:0]          instr_rdata_i,         // instruction read from memory/cache\n  input  logic [31:0]          instr_rdata_alu_i,     // instruction read from memory/cache\n                                                      // replicated to ease fan-out)\n  input  logic                 illegal_c_insn_i,      // compressed instruction decode failed\n  // immediates\n  output cve2_pkg::imm_a_sel_e  imm_a_mux_sel_o,       // immediate selection for operand a\n  output cve2_pkg::imm_b_sel_e  imm_b_mux_sel_o,       // immediate selection for operand b\n  output logic [31:0]           imm_i_type_o,\n  output logic [31:0]           imm_s_type_o,\n  output logic [31:0]           imm_b_type_o,\n  output logic [31:0]           imm_u_type_o,\n  output logic [31:0]           imm_j_type_o,\n  output logic [31:0]           zimm_rs1_type_o,\n  // register file\n  output logic [XInterface:0]      rf_wdata_sel_o,   // RF write data selection\n  output logic                     rf_we_o,          // write enable for regfile\n  output logic [4:0]               rf_raddr_a_o,\n  output logic [4:0]               rf_raddr_b_o,\n  output logic [4:0]               rf_raddr_c_o,\n  output logic [4:0]               rf_waddr_o,\n  output logic                     rf_ren_a_o,          // Instruction reads from RF addr A\n  output logic                     rf_ren_b_o,          // Instruction reads from RF addr B\n  output logic                     rf_ren_c_o,          // Instruction reads from RF addr C (if X-IF if used)\n  // ALU\n  output cve2_pkg::alu_op_e        alu_operator_o,        // ALU operation selection\n  output cve2_pkg::op_a_sel_e      alu_op_a_mux_sel_o,    // operand a selection: reg value, PC,\n                                                          // immediate or zero\n  output cve2_pkg::op_b_sel_e      alu_op_b_mux_sel_o,    // operand b selection: reg value or\n                                                          // immediate\n  output logic                     alu_multicycle_o,      // ternary bitmanip instruction\n  // MULT & DIV\n  output logic                     mult_en_o,             // perform integer multiplication\n  output logic                     div_en_o,              // perform integer division or remainder\n  output logic                     mult_sel_o,            // as above but static, for data muxes\n  output logic                     div_sel_o,             // as above but static, for data muxes\n  output cve2_pkg::md_op_e         multdiv_operator_o,\n  output logic [1:0]               multdiv_signed_mode_o,\n  // CSRs\n  output logic                     csr_access_o,          // access to CSR\n  output cve2_pkg::csr_op_e        csr_op_o,              // operation to perform on CSR\n  // LSU\n  output logic                     data_req_o,            // start transaction to data memory\n  output logic                     data_we_o,             // write enable\n  output logic [1:0]               data_type_o,           // size of transaction: byte, half\n                                                          // word or word\n  output logic                     data_sign_extension_o, // sign extension for data read from\n                                                      // memory\n  // Core-V eXtension interface (CV-X-IF)\n  input  cve2_pkg::readregflags_t  x_issue_resp_register_read_i,\n  // jump/branches\n  output logic                     jump_in_dec_o,         // jump is being calculated in ALU\n  output logic                     branch_in_dec_o\n);\n  import cve2_pkg::*;\n  logic        illegal_insn;\n  logic        illegal_reg_rv32e;\n  logic        csr_illegal;\n  logic        rf_we;\n  logic [31:0] instr;\n  logic [31:0] instr_alu;\n  logic [9:0]  unused_instr_alu;\n  // Source/Destination register instruction index\n  logic [4:0] instr_rs1;\n  logic [4:0] instr_rs2;\n  logic [4:0] instr_rs3;\n  logic [4:0] instr_rd;\n  logic        use_rs3_d;\n  logic        use_rs3_q;\n  csr_op_e     csr_op;\n  opcode_e     opcode;\n  opcode_e     opcode_alu;\n  // To help timing the flops containing the current instruction are replicated to reduce fan-out.\n  // instr_alu is used to determine the ALU control logic and associated operand/imm select signals\n  // as the ALU is often on the more critical timing paths. instr is used for everything else.\n  assign instr     = instr_rdata_i;\n  assign instr_alu = instr_rdata_alu_i;\n  //////////////////////////////////////\n  // Register and immediate selection //\n  //////////////////////////////////////\n  // immediate extraction and sign extension\n  assign imm_i_type_o = { {20{instr[31]}}, instr[31:20] };\n  assign imm_s_type_o = { {20{instr[31]}}, instr[31:25], instr[11:7] };\n  assign imm_b_type_o = { {19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 };\n  assign imm_u_type_o = { instr[31:12], 12'b0 };\n  assign imm_j_type_o = { {12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 };\n  // immediate for CSR manipulation (zero extended)\n  assign zimm_rs1_type_o = { 27'b0, instr_rs1 }; // rs1\n  if (RV32B != RV32BNone) begin : gen_rs3_flop\n    // the use of rs3 is known one cycle ahead.\n    always_ff  @(posedge clk_i or negedge rst_ni) begin\n      if (!rst_ni) begin\n        use_rs3_q <= 1'b0;\n      end else begin\n        use_rs3_q <= use_rs3_d;\n      end\n    end\n  end else begin : gen_no_rs3_flop\n    logic unused_clk;\n    logic unused_rst_n;\n    // Clock and reset unused when there's no rs3 flop\n    assign unused_clk = clk_i;\n    assign unused_rst_n = rst_ni;\n    // always zero\n    assign use_rs3_q = use_rs3_d;\n  end\n  // source registers\n  assign instr_rs1 = instr[19:15];\n  assign instr_rs2 = instr[24:20];\n  assign instr_rs3 = instr[31:27];\n  assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i) ? instr_rs3 : instr_rs1; // rs3 / rs1\n  assign rf_raddr_b_o = instr_rs2; // rs2\n  assign rf_raddr_c_o = XInterface ? instr_rs3 : '0;\n  // destination register\n  assign instr_rd = instr[11:7];\n  assign rf_waddr_o   = instr_rd; // rd\n  ////////////////////\n  // Register check //\n  ////////////////////\n  if (RV32E) begin : gen_rv32e_reg_check_active\n    assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == OP_A_REG_A)) |\n                                (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == OP_B_REG_B)) |\n                                (rf_waddr_o[4]   & rf_we));\n  end else begin : gen_rv32e_reg_check_inactive\n    assign illegal_reg_rv32e = 1'b0;\n  end\n  ///////////////////////\n  // CSR operand check //\n  ///////////////////////\n  always_comb begin : csr_operand_check\n    csr_op_o = csr_op;\n    // CSRRSI/CSRRCI must not write 0 to CSRs (uimm[4:0]=='0)\n    // CSRRS/CSRRC must not write from x0 to CSRs (rs1=='0)\n    if ((csr_op == CSR_OP_SET || csr_op == CSR_OP_CLEAR) &&\n        instr_rs1 == '0) begin\n      csr_op_o = CSR_OP_READ;\n    end\n  end\n  /////////////\n  // Decoder //\n  /////////////\n  always_comb begin\n    jump_in_dec_o         = 1'b0;\n    jump_set_o            = 1'b0;\n    branch_in_dec_o       = 1'b0;\n    multdiv_operator_o    = MD_OP_MULL;\n    multdiv_signed_mode_o = 2'b00;\n    rf_wdata_sel_o        = $bits(rf_wdata_sel_o)'({RF_WD_EX});\n    rf_we                 = 1'b0;\n    rf_ren_a_o            = 1'b0;\n    rf_ren_b_o            = 1'b0;\n    rf_ren_c_o            = 1'b0;\n    csr_access_o          = 1'b0;\n    csr_illegal           = 1'b0;\n    csr_op                = CSR_OP_READ;\n    data_we_o             = 1'b0;\n    data_type_o           = 2'b00;\n    data_sign_extension_o = 1'b0;\n    data_req_o            = 1'b0;\n    illegal_insn          = 1'b0;\n    ebrk_insn_o           = 1'b0;\n    mret_insn_o           = 1'b0;\n    dret_insn_o           = 1'b0;\n    ecall_insn_o          = 1'b0;\n    wfi_insn_o            = 1'b0;\n    opcode                = opcode_e'(instr[6:0]);\n    unique case (opcode)\n      ///////////\n      // Jumps //\n      ///////////\n      OPCODE_JAL: begin   // Jump and Link\n        jump_in_dec_o      = 1'b1;\n        if (instr_first_cycle_i) begin\n          // Calculate jump target (and store PC)\n          rf_we            = 1'b0;\n          jump_set_o       = 1'b1;\n        end else begin\n          // Calculate and store PC+4\n          rf_we            = 1'b1;\n        end\n      end\n      OPCODE_JALR: begin  // Jump and Link Register\n        jump_in_dec_o      = 1'b1;\n        if (instr_first_cycle_i) begin\n          // Calculate jump target (and store PC)\n          rf_we            = 1'b0;\n          jump_set_o       = 1'b1;\n        end else begin\n          // Calculate and store PC+4\n          rf_we            = 1'b1;\n        end\n        if (instr[14:12] != 3'b0) begin\n          illegal_insn = 1'b1;\n        end\n        rf_ren_a_o = 1'b1;\n      end\n      OPCODE_BRANCH: begin // Branch\n        branch_in_dec_o       = 1'b1;\n        // Check branch condition selection\n        unique case (instr[14:12])\n          3'b000,\n          3'b001,\n          3'b100,\n          3'b101,\n          3'b110,\n          3'b111:  illegal_insn = 1'b0;\n          default: illegal_insn = 1'b1;\n        endcase\n        rf_ren_a_o = 1'b1;\n        rf_ren_b_o = 1'b1;\n      end\n      ////////////////\n      // Load/store //\n      ////////////////\n      OPCODE_STORE: begin\n        rf_ren_a_o         = 1'b1;\n        rf_ren_b_o         = 1'b1;\n        data_req_o         = 1'b1;\n        data_we_o          = 1'b1;\n        if (instr[14]) begin\n          illegal_insn = 1'b1;\n        end\n        // store size\n        unique case (instr[13:12])\n          2'b00:   data_type_o  = 2'b10; // sb\n          2'b01:   data_type_o  = 2'b01; // sh\n          2'b10:   data_type_o  = 2'b00; // sw\n          default: illegal_insn = 1'b1;\n        endcase\n      end\n      OPCODE_LOAD: begin\n        rf_ren_a_o          = 1'b1;\n        data_req_o          = 1'b1;\n        data_type_o         = 2'b00;\n        // sign/zero extension\n        data_sign_extension_o = ~instr[14];\n        // load size\n        unique case (instr[13:12])\n          2'b00: data_type_o = 2'b10; // lb(u)\n          2'b01: data_type_o = 2'b01; // lh(u)\n          2'b10: begin\n            data_type_o = 2'b00;      // lw\n            if (instr[14]) begin\n              illegal_insn = 1'b1;    // lwu does not exist\n            end\n          end\n          default: begin\n            illegal_insn = 1'b1;\n          end\n        endcase\n      end\n      /////////\n      // ALU //\n      /////////\n      OPCODE_LUI: begin  // Load Upper Immediate\n        rf_we            = 1'b1;\n      end\n      OPCODE_AUIPC: begin  // Add Upper Immediate to PC\n        rf_we            = 1'b1;\n      end\n      OPCODE_OP_IMM: begin // Register-Immediate ALU Operations\n        rf_ren_a_o       = 1'b1;\n        rf_we            = 1'b1;\n        unique case (instr[14:12])\n          3'b000,\n          3'b010,\n          3'b011,\n          3'b100,\n          3'b110,\n          3'b111: illegal_insn = 1'b0;\n          3'b001: begin\n            unique case (instr[31:27])\n              5'b0_0000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1;        // slli\n              5'b0_0100: begin                                                        // sloi\n                illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n              end\n              5'b0_1001,                                                              // bclri\n              5'b0_0101,                                                              // bseti\n              5'b0_1101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1;           // binvi\n              5'b0_0001: begin\n                if (instr[26] == 1'b0) begin                                          // shfl\n                  illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n                end else begin\n                  illegal_insn = 1'b1;\n                end\n              end\n              5'b0_1100: begin\n                unique case(instr[26:20])\n                  7'b000_0000,                                                         // clz\n                  7'b000_0001,                                                         // ctz\n                  7'b000_0010,                                                         // cpop\n                  7'b000_0100,                                                         // sext.b\n                  7'b000_0101: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1;      // sext.h\n                  7'b001_0000,                                                         // crc32.b\n                  7'b001_0001,                                                         // crc32.h\n                  7'b001_0010,                                                         // crc32.w\n                  7'b001_1000,                                                         // crc32c.b\n                  7'b001_1001,                                                         // crc32c.h\n                  7'b001_1010: begin                                                   // crc32c.w\n                    illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n                  end\n                  default: illegal_insn = 1'b1;\n                endcase\n              end\n              default : illegal_insn = 1'b1;\n            endcase\n          end\n          3'b101: begin\n            if (instr[26]) begin\n              illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1;                       // fsri\n            end else begin\n              unique case (instr[31:27])\n                5'b0_0000,                                                             // srli\n                5'b0_1000: illegal_insn = (instr[26:25] == 2'b00) ? 1'b0 : 1'b1;       // srai\n                5'b0_0100: begin                                                       // sroi\n                  illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n                end\n                5'b0_1100,                                                             // rori\n                5'b0_1001: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1;          // bexti\n                5'b0_1101: begin\n                  if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                    illegal_insn = 1'b0;                                               // grevi\n                  end else if (RV32B == RV32BBalanced) begin\n                    illegal_insn = (instr[24:20] == 5'b11000) ? 1'b0 : 1'b1;           // rev8\n                  end else begin\n                    illegal_insn = 1'b1;\n                  end\n                end\n                5'b0_0101: begin\n                  if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                    illegal_insn = 1'b0;                                              // gorci\n                  end else if (instr[24:20] == 5'b00111) begin\n                    illegal_insn = (RV32B == RV32BBalanced) ? 1'b0 : 1'b1;            // orc.b\n                  end else begin\n                    illegal_insn = 1'b1;\n                  end\n                end\n                5'b0_0001: begin\n                  if (instr[26] == 1'b0) begin                                        // unshfl\n                    illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n                  end else begin\n                    illegal_insn = 1'b1;\n                  end\n                end\n                default: illegal_insn = 1'b1;\n              endcase\n            end\n          end\n          default: illegal_insn = 1'b1;\n        endcase\n      end\n      OPCODE_OP: begin  // Register-Register ALU operation\n        rf_ren_a_o      = 1'b1;\n        rf_ren_b_o      = 1'b1;\n        rf_we           = 1'b1;\n        if ({instr[26], instr[13:12]} == {1'b1, 2'b01}) begin\n          illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // cmix / cmov / fsl / fsr\n        end else begin\n          unique case ({instr[31:25], instr[14:12]})\n            // RV32I ALU operations\n            {7'b000_0000, 3'b000},\n            {7'b010_0000, 3'b000},\n            {7'b000_0000, 3'b010},\n            {7'b000_0000, 3'b011},\n            {7'b000_0000, 3'b100},\n            {7'b000_0000, 3'b110},\n            {7'b000_0000, 3'b111},\n            {7'b000_0000, 3'b001},\n            {7'b000_0000, 3'b101},\n            {7'b010_0000, 3'b101}: illegal_insn = 1'b0;\n            // RV32B zba\n            {7'b001_0000, 3'b010}, // sh1add\n            {7'b001_0000, 3'b100}, // sh2add\n            {7'b001_0000, 3'b110}, // sh3add\n            // RV32B zbb\n            {7'b010_0000, 3'b111}, // andn\n            {7'b010_0000, 3'b110}, // orn\n            {7'b010_0000, 3'b100}, // xnor\n            {7'b011_0000, 3'b001}, // rol\n            {7'b011_0000, 3'b101}, // ror\n            {7'b000_0101, 3'b100}, // min\n            {7'b000_0101, 3'b110}, // max\n            {7'b000_0101, 3'b101}, // minu\n            {7'b000_0101, 3'b111}, // maxu\n            {7'b000_0100, 3'b100}, // pack\n            {7'b010_0100, 3'b100}, // packu\n            {7'b000_0100, 3'b111}, // packh\n            // RV32B zbs\n            {7'b010_0100, 3'b001}, // bclr\n            {7'b001_0100, 3'b001}, // bset\n            {7'b011_0100, 3'b001}, // binv\n            {7'b010_0100, 3'b101}, // bext\n            // RV32B zbf\n            {7'b010_0100, 3'b111}: illegal_insn = (RV32B != RV32BNone) ? 1'b0 : 1'b1; // bfp\n            // RV32B zbp\n            {7'b011_0100, 3'b101}, // grev\n            {7'b001_0100, 3'b101}, // gorc\n            {7'b000_0100, 3'b001}, // shfl\n            {7'b000_0100, 3'b101}, // unshfl\n            {7'b001_0100, 3'b010}, // xperm.n\n            {7'b001_0100, 3'b100}, // xperm.b\n            {7'b001_0100, 3'b110}, // xperm.h\n            {7'b001_0000, 3'b001}, // slo\n            {7'b001_0000, 3'b101}, // sro\n            // RV32B zbc\n            {7'b000_0101, 3'b001}, // clmul\n            {7'b000_0101, 3'b010}, // clmulr\n            {7'b000_0101, 3'b011}: begin // clmulh\n              illegal_insn = (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) ? 1'b0 : 1'b1;\n            end\n            // RV32B zbe\n            {7'b010_0100, 3'b110}, // bdecompress\n            {7'b000_0100, 3'b110}: illegal_insn = (RV32B == RV32BFull) ? 1'b0 : 1'b1; // bcompress\n            // RV32M instructions\n            {7'b000_0001, 3'b000}: begin // mul\n              multdiv_operator_o    = MD_OP_MULL;\n              multdiv_signed_mode_o = 2'b00;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            {7'b000_0001, 3'b001}: begin // mulh\n              multdiv_operator_o    = MD_OP_MULH;\n              multdiv_signed_mode_o = 2'b11;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            {7'b000_0001, 3'b010}: begin // mulhsu\n              multdiv_operator_o    = MD_OP_MULH;\n              multdiv_signed_mode_o = 2'b01;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            {7'b000_0001, 3'b011}: begin // mulhu\n              multdiv_operator_o    = MD_OP_MULH;\n              multdiv_signed_mode_o = 2'b00;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            {7'b000_0001, 3'b100}: begin // div\n              multdiv_operator_o    = MD_OP_DIV;\n              multdiv_signed_mode_o = 2'b11;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            {7'b000_0001, 3'b101}: begin // divu\n              multdiv_operator_o    = MD_OP_DIV;\n              multdiv_signed_mode_o = 2'b00;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            {7'b000_0001, 3'b110}: begin // rem\n              multdiv_operator_o    = MD_OP_REM;\n              multdiv_signed_mode_o = 2'b11;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            {7'b000_0001, 3'b111}: begin // remu\n              multdiv_operator_o    = MD_OP_REM;\n              multdiv_signed_mode_o = 2'b00;\n              illegal_insn          = (RV32M == RV32MNone) ? 1'b1 : 1'b0;\n            end\n            default: begin\n              illegal_insn = 1'b1;\n            end\n          endcase\n        end\n      end\n      /////////////\n      // Special //\n      /////////////\n      OPCODE_MISC_MEM: begin\n        unique case (instr[14:12])\n          3'b000: begin\n            // FENCE is treated as a NOP since all memory operations are already strictly ordered.\n            rf_we           = 1'b0;\n          end\n          3'b001: begin\n            // FENCE.I is implemented as a jump to the next PC, this gives the required flushing\n            // behaviour (iside prefetch buffer flushed and response to any outstanding iside\n            // requests will be ignored).\n            jump_in_dec_o   = 1'b1;\n            rf_we           = 1'b0;\n            if (instr_first_cycle_i) begin\n              jump_set_o       = 1'b1;\n            end\n          end\n          default: begin\n            illegal_insn       = 1'b1;\n          end\n        endcase\n      end\n      OPCODE_SYSTEM: begin\n        if (instr[14:12] == 3'b000) begin\n          // non CSR related SYSTEM instructions\n          unique case (instr[31:20])\n            12'h000:  // ECALL\n              // environment (system) call\n              ecall_insn_o = 1'b1;\n            12'h001:  // ebreak\n              // debugger trap\n              ebrk_insn_o = 1'b1;\n            12'h302:  // mret\n              mret_insn_o = 1'b1;\n            12'h7b2:  // dret\n              dret_insn_o = 1'b1;\n            12'h105:  // wfi\n              wfi_insn_o = 1'b1;\n            default:\n              illegal_insn = 1'b1;\n          endcase\n          // rs1 and rd must be 0\n          if (instr_rs1 != 5'b0 || instr_rd != 5'b0) begin\n            illegal_insn = 1'b1;\n          end\n        end else begin\n          // instruction to read/modify CSR\n          csr_access_o     = 1'b1;\n          rf_wdata_sel_o   = $bits(rf_wdata_sel_o)'({RF_WD_CSR});\n          rf_we            = 1'b1;\n          if (~instr[14]) begin\n            rf_ren_a_o         = 1'b1;\n          end\n          unique case (instr[13:12])\n            2'b01:   csr_op = CSR_OP_WRITE;\n            2'b10:   csr_op = CSR_OP_SET;\n            2'b11:   csr_op = CSR_OP_CLEAR;\n            default: csr_illegal = 1'b1;\n          endcase\n          illegal_insn = csr_illegal;\n        end\n      end\n      default: begin\n        illegal_insn = 1'b1;\n      end\n    endcase\n    // make sure illegal compressed instructions cause illegal instruction exceptions\n    if (illegal_c_insn_i) begin\n      illegal_insn = 1'b1;\n    end\n    // make sure illegal instructions detected in the decoder do not propagate from decoder\n    // into register file, LSU, EX, WB, CSRs, PC\n    // NOTE: instructions can also be detected to be illegal inside the CSRs (upon accesses with\n    // insufficient privileges), or when accessing non-available registers in RV32E,\n    // these cases are not handled here\n    if (illegal_insn) begin\n      rf_we           = 1'b0;\n      data_req_o      = 1'b0;\n      data_we_o       = 1'b0;\n      jump_in_dec_o   = 1'b0;\n      jump_set_o      = 1'b0;\n      branch_in_dec_o = 1'b0;\n      csr_access_o    = 1'b0;\n      // CV-X-IF\n      if(XInterface) begin\n        rf_ren_a_o       = x_issue_resp_register_read_i[0];\n        rf_ren_b_o       = x_issue_resp_register_read_i[1];\n        rf_ren_c_o       = x_issue_resp_register_read_i[2];\n        rf_wdata_sel_o   = $bits(rf_wdata_sel_o)'({RF_WD_COPROC});\n      end \n    end\n  end\n  /////////////////////////////\n  // Decoder for ALU control //\n  /////////////////////////////\n  always_comb begin\n    alu_operator_o     = ALU_SLTU;\n    alu_op_a_mux_sel_o = OP_A_IMM;\n    alu_op_b_mux_sel_o = OP_B_IMM;\n    imm_a_mux_sel_o    = IMM_A_ZERO;\n    imm_b_mux_sel_o    = IMM_B_I;\n    opcode_alu         = opcode_e'(instr_alu[6:0]);\n    use_rs3_d          = 1'b0;\n    alu_multicycle_o   = 1'b0;\n    mult_sel_o         = 1'b0;\n    div_sel_o          = 1'b0;\n    unique case (opcode_alu)\n      ///////////\n      // Jumps //\n      ///////////\n      OPCODE_JAL: begin // Jump and Link\n        // Jumps take two cycles without the BTALU\n        if (instr_first_cycle_i) begin\n          // Calculate jump target\n          alu_op_a_mux_sel_o  = OP_A_CURRPC;\n          alu_op_b_mux_sel_o  = OP_B_IMM;\n          imm_b_mux_sel_o     = IMM_B_J;\n          alu_operator_o      = ALU_ADD;\n        end else begin\n          // Calculate and store PC+4\n          alu_op_a_mux_sel_o  = OP_A_CURRPC;\n          alu_op_b_mux_sel_o  = OP_B_IMM;\n          imm_b_mux_sel_o     = IMM_B_INCR_PC;\n          alu_operator_o      = ALU_ADD;\n        end\n      end\n      OPCODE_JALR: begin // Jump and Link Register\n        // Jumps take two cycles without the BTALU\n        if (instr_first_cycle_i) begin\n          // Calculate jump target\n          alu_op_a_mux_sel_o  = OP_A_REG_A;\n          alu_op_b_mux_sel_o  = OP_B_IMM;\n          imm_b_mux_sel_o     = IMM_B_I;\n          alu_operator_o      = ALU_ADD;\n        end else begin\n          // Calculate and store PC+4\n          alu_op_a_mux_sel_o  = OP_A_CURRPC;\n          alu_op_b_mux_sel_o  = OP_B_IMM;\n          imm_b_mux_sel_o     = IMM_B_INCR_PC;\n          alu_operator_o      = ALU_ADD;\n        end\n      end\n      OPCODE_BRANCH: begin // Branch\n        // Check branch condition selection\n        unique case (instr_alu[14:12])\n          3'b000:  alu_operator_o = ALU_EQ;\n          3'b001:  alu_operator_o = ALU_NE;\n          3'b100:  alu_operator_o = ALU_LT;\n          3'b101:  alu_operator_o = ALU_GE;\n          3'b110:  alu_operator_o = ALU_LTU;\n          3'b111:  alu_operator_o = ALU_GEU;\n          default: ;\n        endcase\n        // Without branch target ALU, a branch is a two-stage operation using the Main ALU in both\n        // stages\n        if (instr_first_cycle_i) begin\n          // First evaluate the branch condition\n          alu_op_a_mux_sel_o  = OP_A_REG_A;\n          alu_op_b_mux_sel_o  = OP_B_REG_B;\n        end else begin\n          // Then calculate jump target\n          alu_op_a_mux_sel_o  = OP_A_CURRPC;\n          alu_op_b_mux_sel_o  = OP_B_IMM;\n          // Not-taken branch will jump to next instruction (used in secure mode)\n          imm_b_mux_sel_o     = IMM_B_B;\n          alu_operator_o      = ALU_ADD;\n        end\n      end\n      ////////////////\n      // Load/store //\n      ////////////////\n      OPCODE_STORE: begin\n        alu_op_a_mux_sel_o = OP_A_REG_A;\n        alu_op_b_mux_sel_o = OP_B_REG_B;\n        alu_operator_o     = ALU_ADD;\n        if (!instr_alu[14]) begin\n          // offset from immediate\n          imm_b_mux_sel_o     = IMM_B_S;\n          alu_op_b_mux_sel_o  = OP_B_IMM;\n        end\n      end\n      OPCODE_LOAD: begin\n        alu_op_a_mux_sel_o  = OP_A_REG_A;\n        // offset from immediate\n        alu_operator_o      = ALU_ADD;\n        alu_op_b_mux_sel_o  = OP_B_IMM;\n        imm_b_mux_sel_o     = IMM_B_I;\n      end\n      /////////\n      // ALU //\n      /////////\n      OPCODE_LUI: begin  // Load Upper Immediate\n        alu_op_a_mux_sel_o  = OP_A_IMM;\n        alu_op_b_mux_sel_o  = OP_B_IMM;\n        imm_a_mux_sel_o     = IMM_A_ZERO;\n        imm_b_mux_sel_o     = IMM_B_U;\n        alu_operator_o      = ALU_ADD;\n      end\n      OPCODE_AUIPC: begin  // Add Upper Immediate to PC\n        alu_op_a_mux_sel_o  = OP_A_CURRPC;\n        alu_op_b_mux_sel_o  = OP_B_IMM;\n        imm_b_mux_sel_o     = IMM_B_U;\n        alu_operator_o      = ALU_ADD;\n      end\n      OPCODE_OP_IMM: begin // Register-Immediate ALU Operations\n        alu_op_a_mux_sel_o  = OP_A_REG_A;\n        alu_op_b_mux_sel_o  = OP_B_IMM;\n        imm_b_mux_sel_o     = IMM_B_I;\n        unique case (instr_alu[14:12])\n          3'b000: alu_operator_o = ALU_ADD;  // Add Immediate\n          3'b010: alu_operator_o = ALU_SLT;  // Set to one if Lower Than Immediate\n          3'b011: alu_operator_o = ALU_SLTU; // Set to one if Lower Than Immediate Unsigned\n          3'b100: alu_operator_o = ALU_XOR;  // Exclusive Or with Immediate\n          3'b110: alu_operator_o = ALU_OR;   // Or with Immediate\n          3'b111: alu_operator_o = ALU_AND;  // And with Immediate\n          3'b001: begin\n            if (RV32B != RV32BNone) begin\n              unique case (instr_alu[31:27])\n                5'b0_0000: alu_operator_o = ALU_SLL;    // Shift Left Logical by Immediate\n                // Shift Left Ones by Immediate\n                5'b0_0100: begin\n                  if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_SLO;\n                end\n                5'b0_1001: alu_operator_o = ALU_BCLR; // Clear bit specified by immediate\n                5'b0_0101: alu_operator_o = ALU_BSET; // Set bit specified by immediate\n                5'b0_1101: alu_operator_o = ALU_BINV; // Invert bit specified by immediate.\n                // Shuffle with Immediate Control Value\n                5'b0_0001: if (instr_alu[26] == 0) alu_operator_o = ALU_SHFL;\n                5'b0_1100: begin\n                  unique case (instr_alu[26:20])\n                    7'b000_0000: alu_operator_o = ALU_CLZ;   // clz\n                    7'b000_0001: alu_operator_o = ALU_CTZ;   // ctz\n                    7'b000_0010: alu_operator_o = ALU_CPOP;  // cpop\n                    7'b000_0100: alu_operator_o = ALU_SEXTB; // sext.b\n                    7'b000_0101: alu_operator_o = ALU_SEXTH; // sext.h\n                    7'b001_0000: begin\n                      if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                        alu_operator_o = ALU_CRC32_B;  // crc32.b\n                        alu_multicycle_o = 1'b1;\n                      end\n                    end\n                    7'b001_0001: begin\n                      if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                        alu_operator_o = ALU_CRC32_H;  // crc32.h\n                        alu_multicycle_o = 1'b1;\n                      end\n                    end\n                    7'b001_0010: begin\n                      if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                        alu_operator_o = ALU_CRC32_W;  // crc32.w\n                        alu_multicycle_o = 1'b1;\n                      end\n                    end\n                    7'b001_1000: begin\n                      if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                        alu_operator_o = ALU_CRC32C_B; // crc32c.b\n                        alu_multicycle_o = 1'b1;\n                      end\n                    end\n                    7'b001_1001: begin\n                      if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                        alu_operator_o = ALU_CRC32C_H; // crc32c.h\n                        alu_multicycle_o = 1'b1;\n                      end\n                    end\n                    7'b001_1010: begin\n                      if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                        alu_operator_o = ALU_CRC32C_W; // crc32c.w\n                        alu_multicycle_o = 1'b1;\n                      end\n                    end\n                    default: ;\n                  endcase\n                end\n                default: ;\n              endcase\n            end else begin\n              alu_operator_o = ALU_SLL; // Shift Left Logical by Immediate\n            end\n          end\n          3'b101: begin\n            if (RV32B != RV32BNone) begin\n              if (instr_alu[26] == 1'b1) begin\n                alu_operator_o = ALU_FSR;\n                alu_multicycle_o = 1'b1;\n                if (instr_first_cycle_i) begin\n                  use_rs3_d = 1'b1;\n                end else begin\n                  use_rs3_d = 1'b0;\n                end\n              end else begin\n                unique case (instr_alu[31:27])\n                  5'b0_0000: alu_operator_o = ALU_SRL;   // Shift Right Logical by Immediate\n                  5'b0_1000: alu_operator_o = ALU_SRA;   // Shift Right Arithmetically by Immediate\n                  // Shift Right Ones by Immediate\n                  5'b0_0100: begin\n                    if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_SRO;\n                  end\n                  5'b0_1001: alu_operator_o = ALU_BEXT;  // Extract bit specified by immediate.\n                  5'b0_1100: begin\n                    alu_operator_o = ALU_ROR;            // Rotate Right by Immediate\n                    alu_multicycle_o = 1'b1;\n                  end\n                  5'b0_1101: alu_operator_o = ALU_GREV;  // General Reverse with Imm Control Val\n                  5'b0_0101: alu_operator_o = ALU_GORC;  // General Or-combine with Imm Control Val\n                  // Unshuffle with Immediate Control Value\n                  5'b0_0001: begin\n                    if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) begin\n                      if (instr_alu[26] == 1'b0) alu_operator_o = ALU_UNSHFL;\n                    end\n                  end\n                  default: ;\n                endcase\n              end\n            end else begin\n              if (instr_alu[31:27] == 5'b0_0000) begin\n                alu_operator_o = ALU_SRL;               // Shift Right Logical by Immediate\n              end else if (instr_alu[31:27] == 5'b0_1000) begin\n                alu_operator_o = ALU_SRA;               // Shift Right Arithmetically by Immediate\n              end\n            end\n          end\n          default: ;\n        endcase\n      end\n      OPCODE_OP: begin  // Register-Register ALU operation\n        alu_op_a_mux_sel_o = OP_A_REG_A;\n        alu_op_b_mux_sel_o = OP_B_REG_B;\n        if (instr_alu[26]) begin\n          if (RV32B != RV32BNone) begin\n            unique case ({instr_alu[26:25], instr_alu[14:12]})\n              {2'b11, 3'b001}: begin\n                alu_operator_o   = ALU_CMIX; // cmix\n                alu_multicycle_o = 1'b1;\n                if (instr_first_cycle_i) begin\n                  use_rs3_d = 1'b1;\n                end else begin\n                  use_rs3_d = 1'b0;\n                end\n              end\n              {2'b11, 3'b101}: begin\n                alu_operator_o   = ALU_CMOV; // cmov\n                alu_multicycle_o = 1'b1;\n                if (instr_first_cycle_i) begin\n                  use_rs3_d = 1'b1;\n                end else begin\n                  use_rs3_d = 1'b0;\n                end\n              end\n              {2'b10, 3'b001}: begin\n                alu_operator_o   = ALU_FSL;  // fsl\n                alu_multicycle_o = 1'b1;\n                if (instr_first_cycle_i) begin\n                  use_rs3_d = 1'b1;\n                end else begin\n                  use_rs3_d = 1'b0;\n                end\n              end\n              {2'b10, 3'b101}: begin\n                alu_operator_o   = ALU_FSR;  // fsr\n                alu_multicycle_o = 1'b1;\n                if (instr_first_cycle_i) begin\n                  use_rs3_d = 1'b1;\n                end else begin\n                  use_rs3_d = 1'b0;\n                end\n              end\n              default: ;\n            endcase\n          end\n        end else begin\n          unique case ({instr_alu[31:25], instr_alu[14:12]})\n            // RV32I ALU operations\n            {7'b000_0000, 3'b000}: alu_operator_o = ALU_ADD;   // Add\n            {7'b010_0000, 3'b000}: alu_operator_o = ALU_SUB;   // Sub\n            {7'b000_0000, 3'b010}: alu_operator_o = ALU_SLT;   // Set Lower Than\n            {7'b000_0000, 3'b011}: alu_operator_o = ALU_SLTU;  // Set Lower Than Unsigned\n            {7'b000_0000, 3'b100}: alu_operator_o = ALU_XOR;   // Xor\n            {7'b000_0000, 3'b110}: alu_operator_o = ALU_OR;    // Or\n            {7'b000_0000, 3'b111}: alu_operator_o = ALU_AND;   // And\n            {7'b000_0000, 3'b001}: alu_operator_o = ALU_SLL;   // Shift Left Logical\n            {7'b000_0000, 3'b101}: alu_operator_o = ALU_SRL;   // Shift Right Logical\n            {7'b010_0000, 3'b101}: alu_operator_o = ALU_SRA;   // Shift Right Arithmetic\n            // RV32B ALU Operations\n            {7'b011_0000, 3'b001}: begin\n              if (RV32B != RV32BNone) begin\n                alu_operator_o = ALU_ROL;\n                alu_multicycle_o = 1'b1;\n              end\n            end\n            {7'b011_0000, 3'b101}: begin\n              if (RV32B != RV32BNone) begin\n                alu_operator_o = ALU_ROR;\n                alu_multicycle_o = 1'b1;\n              end\n            end\n            {7'b000_0101, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_MIN;\n            {7'b000_0101, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAX;\n            {7'b000_0101, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_MINU;\n            {7'b000_0101, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_MAXU;\n            {7'b000_0100, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACK;\n            {7'b010_0100, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACKU;\n            {7'b000_0100, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_PACKH;\n            {7'b010_0000, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_XNOR;\n            {7'b010_0000, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_ORN;\n            {7'b010_0000, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_ANDN;\n            // RV32B zba\n            {7'b001_0000, 3'b010}: if (RV32B != RV32BNone) alu_operator_o = ALU_SH1ADD;\n            {7'b001_0000, 3'b100}: if (RV32B != RV32BNone) alu_operator_o = ALU_SH2ADD;\n            {7'b001_0000, 3'b110}: if (RV32B != RV32BNone) alu_operator_o = ALU_SH3ADD;\n            // RV32B zbs\n            {7'b010_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_BCLR;\n            {7'b001_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_BSET;\n            {7'b011_0100, 3'b001}: if (RV32B != RV32BNone) alu_operator_o = ALU_BINV;\n            {7'b010_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_BEXT;\n            // RV32B zbf\n            {7'b010_0100, 3'b111}: if (RV32B != RV32BNone) alu_operator_o = ALU_BFP;\n            // RV32B zbp\n            {7'b011_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_GREV;\n            {7'b001_0100, 3'b101}: if (RV32B != RV32BNone) alu_operator_o = ALU_GORC;\n            {7'b000_0100, 3'b001}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_SHFL;\n            end\n            {7'b000_0100, 3'b101}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_UNSHFL;\n            end\n            {7'b001_0100, 3'b010}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_XPERM_N;\n            end\n            {7'b001_0100, 3'b100}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_XPERM_B;\n            end\n            {7'b001_0100, 3'b110}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_XPERM_H;\n            end\n            {7'b001_0000, 3'b001}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_SLO;\n            end\n            {7'b001_0000, 3'b101}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_SRO;\n            end\n            // RV32B zbc\n            {7'b000_0101, 3'b001}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_CLMUL;\n            end\n            {7'b000_0101, 3'b010}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_CLMULR;\n            end\n            {7'b000_0101, 3'b011}: begin\n              if (RV32B == RV32BOTEarlGrey || RV32B == RV32BFull) alu_operator_o = ALU_CLMULH;\n            end\n            // RV32B zbe\n            {7'b010_0100, 3'b110}: begin\n              if (RV32B == RV32BFull) begin\n                alu_operator_o = ALU_BDECOMPRESS;\n                alu_multicycle_o = 1'b1;\n              end\n            end\n            {7'b000_0100, 3'b110}: begin\n              if (RV32B == RV32BFull) begin\n                alu_operator_o = ALU_BCOMPRESS;\n                alu_multicycle_o = 1'b1;\n              end\n            end\n            // RV32M instructions, all use the same ALU operation\n            {7'b000_0001, 3'b000}: begin // mul\n              alu_operator_o = ALU_ADD;\n              mult_sel_o     = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            {7'b000_0001, 3'b001}: begin // mulh\n              alu_operator_o = ALU_ADD;\n              mult_sel_o     = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            {7'b000_0001, 3'b010}: begin // mulhsu\n              alu_operator_o = ALU_ADD;\n              mult_sel_o     = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            {7'b000_0001, 3'b011}: begin // mulhu\n              alu_operator_o = ALU_ADD;\n              mult_sel_o     = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            {7'b000_0001, 3'b100}: begin // div\n              alu_operator_o = ALU_ADD;\n              div_sel_o      = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            {7'b000_0001, 3'b101}: begin // divu\n              alu_operator_o = ALU_ADD;\n              div_sel_o      = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            {7'b000_0001, 3'b110}: begin // rem\n              alu_operator_o = ALU_ADD;\n              div_sel_o      = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            {7'b000_0001, 3'b111}: begin // remu\n              alu_operator_o = ALU_ADD;\n              div_sel_o      = (RV32M == RV32MNone) ? 1'b0 : 1'b1;\n            end\n            default: ;\n          endcase\n        end\n      end\n      /////////////\n      // Special //\n      /////////////\n      OPCODE_MISC_MEM: begin\n        unique case (instr_alu[14:12])\n          3'b000: begin\n            // FENCE is treated as a NOP since all memory operations are already strictly ordered.\n            alu_operator_o     = ALU_ADD; // nop\n            alu_op_a_mux_sel_o = OP_A_REG_A;\n            alu_op_b_mux_sel_o = OP_B_IMM;\n          end\n          3'b001: begin\n            // FENCE.I will flush the IF stage, prefetch buffer and ICache if present.\n              alu_op_a_mux_sel_o = OP_A_CURRPC;\n              alu_op_b_mux_sel_o = OP_B_IMM;\n              imm_b_mux_sel_o    = IMM_B_INCR_PC;\n              alu_operator_o     = ALU_ADD;\n          end\n          default: ;\n        endcase\n      end\n      OPCODE_SYSTEM: begin\n        if (instr_alu[14:12] == 3'b000) begin\n          // non CSR related SYSTEM instructions\n          alu_op_a_mux_sel_o = OP_A_REG_A;\n          alu_op_b_mux_sel_o = OP_B_IMM;\n        end else begin\n          // instruction to read/modify CSR\n          alu_op_b_mux_sel_o = OP_B_IMM;\n          imm_a_mux_sel_o    = IMM_A_Z;\n          imm_b_mux_sel_o    = IMM_B_I;  // CSR address is encoded in I imm\n          if (instr_alu[14]) begin\n            // rs1 field is used as immediate\n            alu_op_a_mux_sel_o = OP_A_IMM;\n          end else begin\n            alu_op_a_mux_sel_o = OP_A_REG_A;\n          end\n        end\n      end\n      default: ;\n    endcase\n  end\n  // do not enable multdiv in case of illegal instruction exceptions\n  assign mult_en_o = illegal_insn ? 1'b0 : mult_sel_o;\n  assign div_en_o  = illegal_insn ? 1'b0 : div_sel_o;\n  // make sure instructions accessing non-available registers in RV32E cause illegal\n  // instruction exceptions\n  assign illegal_insn_o = illegal_insn | illegal_reg_rv32e;\n  // do not propgate regfile write enable if non-available registers are accessed in RV32E\n  assign rf_we_o = rf_we & ~illegal_reg_rv32e;\n  // Not all bits are used\n  assign unused_instr_alu = {instr_alu[19:15],instr_alu[11:7]};\n  ////////////////\n  // Assertions //\n  ////////////////\n  // Selectors must be known/valid.\nendmodule // controller\n", "mask_idx": {"conditional_statement": [[61396, 61448], [61027, 61078], [44904, 44989], [60512, 60561], [39739, 44255], [66584, 67198], [48843, 49324], [34148, 34244], [57292, 57449], [35586, 35850], [62054, 62103], [38164, 38569], [61200, 61249], [48240, 48722]], "blocking_assignment": [[50722, 50753], [31678, 31707], [31712, 31741], [46305, 46327], [56949, 56977], [45694, 45714], [47249, 47272], [62274, 62300], [59812, 59861], [63643, 63671]], "always_construct": [[30563, 30880], [47687, 67243], [30931, 47588]], "case_statement": [[49424, 49757], [32862, 33074], [65885, 66538], [33948, 34346], [35916, 37202], [44363, 45097], [34926, 37285], [59170, 65765], [51731, 57516], [48061, 67237], [39914, 44243], [31831, 46518], [45236, 45732], [33476, 33699], [46171, 46386], [34734, 39565], [37493, 39479]], "ansi_port_declaration": [[24644, 24687], [24460, 24549], [24173, 24262], [23602, 23692], [23778, 23869], [26573, 26628], [24942, 25019], [23872, 23948], [23448, 23530]], "continuous_assign": [[67537, 67594], [30444, 30476], [67315, 67367], [29031, 29084], [28402, 28439], [28610, 28666], [28366, 28399], [29643, 29675]], "parameter_declaration": [[23011, 23067], [16946, 16990], [16850, 16895], [23070, 23126], [16898, 16943], [16993, 17037], [13787, 13814], [13622, 13688], [23129, 23177], [13551, 13619]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[28366, 28399], [28402, 28439], [28610, 28666], [28669, 28738], [28741, 28837], [28840, 28886], [28889, 28976], [29031, 29084], [29499, 29525], [29530, 29559], [29583, 29612], [29643, 29675], [29678, 29710], [29713, 29745], [29748, 29842], [29845, 29884], [29887, 29937], [29966, 29996], [29999, 30036], [30158, 30391], [30444, 30476], [67315, 67367], [67370, 67421], [67537, 67594], [67688, 67732], [67762, 67823]], "blocking_assignment": [[30605, 30623], [30843, 30866], [30953, 30982], [30987, 31016], [31021, 31050], [31055, 31090], [31095, 31125], [31130, 31189], [31194, 31223], [31228, 31257], [31262, 31291], [31296, 31325], [31330, 31359], [31364, 31393], [31398, 31434], [31439, 31468], [31473, 31503], [31508, 31537], [31542, 31571], [31576, 31605], [31610, 31639], [31644, 31673], [31678, 31707], [31712, 31741], [31746, 31775], [31780, 31826], [31957, 31983], [32083, 32107], [32118, 32142], [32214, 32238], [32321, 32347], [32447, 32471], [32482, 32506], [32578, 32602], [32665, 32685], [32706, 32724], [32780, 32809], [32998, 33018], [33038, 33058], [33083, 33101], [33110, 33128], [33242, 33268], [33277, 33303], [33312, 33338], [33347, 33373], [33413, 33433], [33522, 33549], [33569, 33596], [33616, 33643], [33663, 33683], [33743, 33770], [33779, 33806], [33815, 33843], [33883, 33918], [33992, 34021], [34039, 34068], [34104, 34135], [34183, 34228], [34296, 34316], [34462, 34486], [34561, 34585], [34668, 34692], [34701, 34725], [34869, 34889], [34978, 35046], [35157, 35235], [35469, 35538], [35682, 35760], [35810, 35830], [36353, 36418], [37030, 37108], [37158, 37178], [37245, 37265], [37371, 37451], [37642, 37709], [37823, 37901], [38044, 38112], [38242, 38317], [38399, 38473], [38527, 38547], [38719, 38793], [38877, 38951], [39005, 39025], [39217, 39295], [39349, 39369], [39437, 39457], [39529, 39549], [39643, 39666], [39675, 39698], [39707, 39730], [39803, 39880], [40343, 40363], [41319, 41376], [41977, 42055], [42182, 42245], [42342, 42377], [42392, 42422], [42437, 42496], [42576, 42611], [42626, 42656], [42671, 42730], [42812, 42847], [42862, 42892], [42907, 42966], [43047, 43082], [43097, 43127], [43142, 43201], [43280, 43314], [43329, 43359], [43374, 43433], [43513, 43547], [43562, 43592], [43607, 43666], [43745, 43779], [43794, 43824], [43839, 43898], [43978, 44012], [44027, 44057], [44072, 44131], [44189, 44209], [44525, 44548], [44832, 44855], [44868, 44891], [44949, 44973], [45041, 45067], [45351, 45371], [45449, 45468], [45513, 45532], [45577, 45596], [45640, 45658], [45694, 45714], [45838, 45858], [45950, 45974], [45985, 46040], [46051, 46075], [46120, 46146], [46219, 46241], [46263, 46283], [46305, 46327], [46349, 46368], [46397, 46424], [46476, 46496], [46643, 46663], [47069, 47092], [47099, 47122], [47129, 47152], [47159, 47182], [47189, 47212], [47219, 47242], [47249, 47272], [47325, 47376], [47385, 47436], [47445, 47496], [47505, 47563], [47709, 47739], [47744, 47774], [47779, 47809], [47814, 47846], [47851, 47880], [47885, 47932], [47937, 47963], [47968, 47994], [47999, 48025], [48030, 48056], [48316, 48350], [48361, 48392], [48403, 48433], [48444, 48474], [48546, 48580], [48591, 48622], [48633, 48669], [48680, 48710], [48919, 48952], [48963, 48994], [49005, 49035], [49046, 49076], [49148, 49182], [49193, 49224], [49235, 49271], [49282, 49312], [49474, 49498], [49518, 49542], [49562, 49586], [49606, 49630], [49650, 49675], [49695, 49720], [49973, 50006], [50017, 50050], [50124, 50158], [50169, 50200], [50293, 50323], [50334, 50364], [50490, 50522], [50531, 50563], [50572, 50601], [50681, 50711], [50722, 50753], [50809, 50842], [50884, 50914], [50923, 50954], [50963, 50993], [51109, 51140], [51149, 51180], [51189, 51222], [51231, 51261], [51270, 51300], [51375, 51409], [51418, 51449], [51458, 51488], [51497, 51527], [51610, 51643], [51652, 51683], [51692, 51722], [51780, 51823], [51842, 51906], [51925, 51998], [52017, 52074], [52093, 52140], [52159, 52207], [52346, 52409], [52561, 52586], [52634, 52696], [52724, 52784], [52812, 52876], [52984, 53010], [53126, 53160], [53194, 53228], [53262, 53297], [53331, 53368], [53402, 53439], [53583, 53624], [53649, 53673], [53867, 53908], [53933, 53957], [54151, 54192], [54217, 54241], [54435, 54477], [54502, 54526], [54720, 54762], [54787, 54811], [55005, 55047], [55072, 55096], [55314, 55374], [55534, 55559], [55576, 55600], [55666, 55683], [55733, 55750], [55876, 55939], [55969, 56039], [56198, 56223], [56275, 56341], [56397, 56462], [56483, 56507], [56559, 56626], [56656, 56726], [56949, 56977], [57193, 57268], [57349, 57431], [57594, 57626], [57635, 57667], [57857, 57893], [57910, 57934], [58000, 58017], [58067, 58084], [58176, 58212], [58229, 58253], [58319, 58336], [58386, 58403], [58495, 58530], [58547, 58571], [58637, 58654], [58704, 58721], [58813, 58848], [58865, 58889], [58955, 58972], [59022, 59039], [59292, 59326], [59362, 59396], [59432, 59477], [59513, 59567], [59603, 59637], [59673, 59706], [59742, 59776], [59812, 59861], [59897, 59947], [59983, 60036], [60174, 60199], [60216, 60240], [60376, 60401], [60418, 60442], [60536, 60561], [60621, 60646], [60706, 60732], [60792, 60818], [60878, 60904], [60964, 60991], [61051, 61078], [61138, 61164], [61224, 61249], [61309, 61335], [61420, 61448], [61508, 61536], [61596, 61624], [61709, 61735], [61795, 61821], [61881, 61907], [61967, 61993], [62078, 62103], [62188, 62214], [62274, 62300], [62408, 62434], [62558, 62586], [62710, 62739], [62863, 62892], [63016, 63045], [63169, 63194], [63318, 63343], [63492, 63519], [63643, 63671], [63795, 63823], [63966, 63999], [64016, 64040], [64176, 64207], [64224, 64248], [64411, 64436], [64451, 64503], [64583, 64608], [64623, 64675], [64757, 64782], [64797, 64849], [64930, 64955], [64970, 65022], [65101, 65126], [65141, 65193], [65273, 65298], [65313, 65365], [65444, 65469], [65484, 65536], [65616, 65641], [65656, 65708], [66051, 66087], [66100, 66132], [66145, 66175], [66315, 66348], [66363, 66393], [66408, 66443], [66458, 66487], [66681, 66713], [66724, 66754], [66832, 66862], [66873, 66902], [66913, 66978], [67072, 67102], [67140, 67172]], "nonblocking_assignment": [[29269, 29287], [29317, 29340]], "case_statement": [[31831, 46518], [32862, 33074], [33476, 33699], [33948, 34346], [34734, 39565], [34926, 37285], [35916, 37202], [37493, 39479], [39914, 44243], [44363, 45097], [45236, 45732], [46171, 46386], [48061, 67237], [49424, 49757], [51731, 57516], [52288, 55272], [53062, 55203], [55816, 57076], [57753, 59122], [59170, 65765], [65885, 66538]], "conditional_statement": [[29242, 29350], [30750, 30874], [31992, 32250], [32356, 32614], [32623, 32697], [33382, 33445], [34148, 34244], [35586, 35850], [37336, 39495], [38164, 38569], [38345, 38569], [38641, 39047], [38821, 39047], [39119, 39391], [39739, 44255], [44904, 44989], [45143, 46436], [45777, 45872], [46086, 46160], [46609, 46671], [47039, 47582], [47296, 47574], [48240, 48722], [48843, 49324], [49883, 50376], [50610, 50765], [52244, 55390], [52509, 52586], [52960, 53010], [53501, 53699], [53785, 53983], [54069, 54267], [54353, 54552], [54638, 54837], [54923, 55122], [55441, 57465], [55485, 57094], [55617, 55770], [56146, 56223], [56842, 57001], [56922, 56977], [57136, 57449], [57292, 57449], [57676, 65777], [57711, 59136], [57951, 58104], [58270, 58423], [58588, 58741], [58906, 59059], [60128, 60258], [60330, 60460], [60512, 60561], [60597, 60646], [60682, 60732], [60768, 60818], [60854, 60904], [60940, 60991], [61027, 61078], [61114, 61164], [61200, 61249], [61285, 61335], [61396, 61448], [61484, 61536], [61572, 61624], [61685, 61735], [61771, 61821], [61857, 61907], [61943, 61993], [62054, 62103], [62164, 62214], [62250, 62300], [62356, 62434], [62506, 62586], [62658, 62739], [62811, 62892], [62964, 63045], [63117, 63194], [63266, 63343], [63440, 63519], [63591, 63671], [63743, 63823], [63920, 64058], [64130, 64266], [66584, 67198], [66989, 67186]], "always_construct": [[29184, 29358], [30563, 30880], [30931, 47588], [47687, 67243]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096], [22970, 23008], [23011, 23067], [23070, 23126], [23129, 23177]], "ansi_port_declaration": [[23184, 23219], [23222, 23258], [23285, 23365], [23368, 23445], [23448, 23530], [23602, 23692], [23695, 23775], [23778, 23869], [23872, 23948], [23985, 24078], [24081, 24170], [24173, 24262], [24350, 24441], [24460, 24549], [24552, 24641], [24644, 24687], [24690, 24733], [24736, 24779], [24782, 24825], [24828, 24871], [24874, 24920], [24942, 25019], [25022, 25100], [25103, 25149], [25152, 25198], [25201, 25247], [25250, 25294], [25297, 25386], [25389, 25478], [25481, 25588], [25600, 25682], [25685, 25779], [25861, 25953], [26027, 26114], [26133, 26222], [26225, 26321], [26324, 26418], [26421, 26515], [26518, 26570], [26573, 26628], [26641, 26713], [26716, 26802], [26814, 26905], [26908, 26979], [26982, 27072], [27149, 27241], [27350, 27412], [27434, 27524], [27527, 27575]]}}
{"sample_i": "p7", "topmodule": "cve2_if_stage", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Fetch Fifo for 32 bit memory interface\n *\n * input port: send address and data to the FIFO\n * clear_i clears the FIFO for the following cycle, including any new request\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_fetch_fifo #(\n  parameter int unsigned NUM_REQS = 2\n) (\n  input  logic                clk_i,\n  input  logic                rst_ni,\n  // control signals\n  input  logic                clear_i,   // clears the contents of the FIFO\n  output logic [NUM_REQS-1:0] busy_o,\n  // input port\n  input  logic                in_valid_i,\n  input  logic [31:0]         in_addr_i,\n  input  logic [31:0]         in_rdata_i,\n  input  logic                in_err_i,\n  // output port\n  output logic                out_valid_o,\n  input  logic                out_ready_i,\n  output logic [31:0]         out_addr_o,\n  output logic [31:0]         out_rdata_o,\n  output logic                out_err_o,\n  output logic                out_err_plus2_o\n);\n  localparam int unsigned DEPTH = NUM_REQS+1;\n  // index 0 is used for output\n  logic [DEPTH-1:0] [31:0]  rdata_d,   rdata_q;\n  logic [DEPTH-1:0]         err_d,     err_q;\n  logic [DEPTH-1:0]         valid_d,   valid_q;\n  logic [DEPTH-1:0]         lowest_free_entry;\n  logic [DEPTH-1:0]         valid_pushed, valid_popped;\n  logic [DEPTH-1:0]         entry_en;\n  logic                     pop_fifo;\n  logic             [31:0]  rdata, rdata_unaligned;\n  logic                     err,   err_unaligned, err_plus2;\n  logic                     valid, valid_unaligned;\n  logic                     aligned_is_compressed, unaligned_is_compressed;\n  logic                     addr_incr_two;\n  logic [31:1]              instr_addr_next;\n  logic [31:1]              instr_addr_d, instr_addr_q;\n  logic                     instr_addr_en;\n  logic                     unused_addr_in;\n  /////////////////\n  // Output port //\n  /////////////////\n  assign rdata = valid_q[0] ? rdata_q[0] : in_rdata_i;\n  assign err   = valid_q[0] ? err_q[0]   : in_err_i;\n  assign valid = valid_q[0] | in_valid_i;\n  // The FIFO contains word aligned memory fetches, but the instructions contained in each entry\n  // might be half-word aligned (due to compressed instructions)\n  // e.g.\n  //              | 31               16 | 15               0 |\n  // FIFO entry 0 | Instr 1 [15:0]      | Instr 0 [15:0]     |\n  // FIFO entry 1 | Instr 2 [15:0]      | Instr 1 [31:16]    |\n  //\n  // The FIFO also has a direct bypass path, so a complete instruction might be made up of data\n  // from the FIFO and new incoming data.\n  //\n  // Construct the output data for an unaligned instruction\n  assign rdata_unaligned = valid_q[1] ? {rdata_q[1][15:0], rdata[31:16]} :\n                                        {in_rdata_i[15:0], rdata[31:16]};\n  // If entry[1] is valid, an error can come from entry[0] or entry[1], unless the\n  // instruction in entry[0] is compressed (entry[1] is a new instruction)\n  // If entry[1] is not valid, and entry[0] is, an error can come from entry[0] or the incoming\n  // data, unless the instruction in entry[0] is compressed\n  // If entry[0] is not valid, the error must come from the incoming data\n  assign err_unaligned   = valid_q[1] ? ((err_q[1] & ~unaligned_is_compressed) | err_q[0]) :\n                                        ((valid_q[0] & err_q[0]) |\n                                         (in_err_i & (~valid_q[0] | ~unaligned_is_compressed)));\n  // Record when an error is caused by the second half of an unaligned 32bit instruction.\n  // Only needs to be correct when unaligned and if err_unaligned is set\n  assign err_plus2       = valid_q[1] ? (err_q[1] & ~err_q[0]) :\n                                        (in_err_i & valid_q[0] & ~err_q[0]);\n  // An uncompressed unaligned instruction is only valid if both parts are available\n  assign valid_unaligned = valid_q[1] ? 1'b1 :\n                                        (valid_q[0] & in_valid_i);\n  // If there is an error, rdata is unknown\n  assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err;\n  assign aligned_is_compressed   = (rdata[ 1: 0] != 2'b11) & ~err;\n  ////////////////////////////////////////\n  // Instruction aligner (if unaligned) //\n  ////////////////////////////////////////\n  always_comb begin\n    if (out_addr_o[1]) begin\n      // unaligned case\n      out_rdata_o     = rdata_unaligned;\n      out_err_o       = err_unaligned;\n      out_err_plus2_o = err_plus2;\n      if (unaligned_is_compressed) begin\n        out_valid_o = valid;\n      end else begin\n        out_valid_o = valid_unaligned;\n      end\n    end else begin\n      // aligned case\n      out_rdata_o     = rdata;\n      out_err_o       = err;\n      out_err_plus2_o = 1'b0;\n      out_valid_o     = valid;\n    end\n  end\n  /////////////////////////\n  // Instruction address //\n  /////////////////////////\n  // Update the address on branches and every time an instruction is driven\n  assign instr_addr_en = clear_i | (out_ready_i & out_valid_o);\n  // Increment the address by two every time a compressed instruction is popped\n  assign addr_incr_two = instr_addr_q[1] ? unaligned_is_compressed :\n                                           aligned_is_compressed;\n  assign instr_addr_next = (instr_addr_q[31:1] +\n                            // Increment address by 4 or 2\n                            {29'd0,~addr_incr_two,addr_incr_two});\n  assign instr_addr_d = clear_i ? in_addr_i[31:1] :\n                                  instr_addr_next;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      instr_addr_q <= '0;\n    end else if (instr_addr_en) begin\n      instr_addr_q <= instr_addr_d;\n    end\n  end\n  // Output PC of current instruction\n  assign out_addr_o      = {instr_addr_q, 1'b0};\n  // The LSB of the address is unused, since all addresses are halfword aligned\n  assign unused_addr_in = in_addr_i[0];\n  /////////////////\n  // FIFO status //\n  /////////////////\n  // Indicate the fill level of fifo-entries. This is used to determine when a new request can be\n  // made on the bus. The prefetch buffer only needs to know about the upper entries which overlap\n  // with NUM_REQS.\n  assign busy_o = valid_q[DEPTH-1:DEPTH-NUM_REQS];\n  /////////////////////\n  // FIFO management //\n  /////////////////////\n  // Since an entry can contain unaligned instructions, popping an entry can leave the entry valid\n  assign pop_fifo = out_ready_i & out_valid_o & (~aligned_is_compressed | out_addr_o[1]);\n  for (genvar i = 0; i < (DEPTH - 1); i++) begin : g_fifo_next\n    // Calculate lowest free entry (write pointer)\n    if (i == 0) begin : g_ent0\n      assign lowest_free_entry[i] = ~valid_q[i];\n    end else begin : g_ent_others\n      assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i-1];\n    end\n    // An entry is set when an incoming request chooses the lowest available entry\n    assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) |\n                             valid_q[i];\n    // Popping the FIFO shifts all entries down\n    assign valid_popped[i] = pop_fifo ? valid_pushed[i+1] : valid_pushed[i];\n    // All entries are wiped out on a clear\n    assign valid_d[i] = valid_popped[i] & ~clear_i;\n    // data flops are enabled if there is new data to shift into it, or\n    assign entry_en[i] = (valid_pushed[i+1] & pop_fifo) |\n                         // a new request is incoming and this is the lowest free entry\n                         (in_valid_i & lowest_free_entry[i] & ~pop_fifo);\n    // take the next entry or the incoming data\n    assign rdata_d[i]  = valid_q[i+1] ? rdata_q[i+1] : in_rdata_i;\n    assign err_d  [i]  = valid_q[i+1] ? err_q  [i+1] : in_err_i;\n  end\n  // The top entry is similar but with simpler muxing\n  assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & valid_q[DEPTH-2];\n  assign valid_pushed     [DEPTH-1] = valid_q[DEPTH-1] | (in_valid_i & lowest_free_entry[DEPTH-1]);\n  assign valid_popped     [DEPTH-1] = pop_fifo ? 1'b0 : valid_pushed[DEPTH-1];\n  assign valid_d [DEPTH-1]          = valid_popped[DEPTH-1] & ~clear_i;\n  assign entry_en[DEPTH-1]          = in_valid_i & lowest_free_entry[DEPTH-1];\n  assign rdata_d [DEPTH-1]          = in_rdata_i;\n  assign err_d   [DEPTH-1]          = in_err_i;\n  ////////////////////\n  // FIFO registers //\n  ////////////////////\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      valid_q <= '0;\n    end else begin\n      valid_q <= valid_d;\n    end\n  end\n  for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs\n      always_ff @(posedge clk_i or negedge rst_ni) begin\n        if (!rst_ni) begin\n          rdata_q[i] <= '0;\n          err_q[i]   <= '0;\n        end else if (entry_en[i]) begin\n          rdata_q[i] <= rdata_d[i];\n          err_q[i]   <= err_d[i];\n        end\n      end\n  end\n  ////////////////\n  // Assertions //\n  ////////////////\n  // Must not push and pop simultaneously when FIFO full.\n  // Must not push to FIFO when full.\nendmodule\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Prefetcher Buffer for 32 bit memory interface\n *\n * Prefetch Buffer that caches instructions. This cuts overly long critical\n * paths to the instruction cache.\n */\nmodule cve2_prefetch_buffer #(\n) (\n  input  logic        clk_i,\n  input  logic        rst_ni,\n  input  logic        req_i,\n  input  logic        branch_i,\n  input  logic [31:0] addr_i,\n  input  logic        ready_i,\n  output logic        valid_o,\n  output logic [31:0] rdata_o,\n  output logic [31:0] addr_o,\n  output logic        err_o,\n  output logic        err_plus2_o,\n  // goes to instruction memory / instruction cache\n  output logic        instr_req_o,\n  input  logic        instr_gnt_i,\n  output logic [31:0] instr_addr_o,\n  input  logic [31:0] instr_rdata_i,\n  input  logic        instr_err_i,\n  input  logic        instr_rvalid_i,\n  // Prefetch Buffer Status\n  output logic        busy_o\n);\n  localparam int unsigned NUM_REQS  = 2;\n  logic                valid_new_req, valid_req;\n  logic                valid_req_d, valid_req_q;\n  logic                discard_req_d, discard_req_q;\n  logic [NUM_REQS-1:0] rdata_outstanding_n, rdata_outstanding_s, rdata_outstanding_q;\n  logic [NUM_REQS-1:0] branch_discard_n, branch_discard_s, branch_discard_q;\n  logic [NUM_REQS-1:0] rdata_outstanding_rev;\n  logic [31:0]         stored_addr_d, stored_addr_q;\n  logic                stored_addr_en;\n  logic [31:0]         fetch_addr_d, fetch_addr_q;\n  logic                fetch_addr_en;\n  logic [31:0]         instr_addr, instr_addr_w_aligned;\n  logic                fifo_valid;\n  logic [31:0]         fifo_addr;\n  logic                fifo_ready;\n  logic                fifo_clear;\n  logic [NUM_REQS-1:0] fifo_busy;\n  logic                valid_raw;\n  ////////////////////////////\n  // Prefetch buffer status //\n  ////////////////////////////\n  assign busy_o = (|rdata_outstanding_q) | instr_req_o;\n  //////////////////////////////////////////////\n  // Fetch fifo - consumes addresses and data //\n  //////////////////////////////////////////////\n  // A branch will invalidate any previously fetched instructions.\n  // Note that the FENCE.I instruction relies on this flushing behaviour on branch. If it is\n  // altered the FENCE.I implementation may require changes.\n  assign fifo_clear = branch_i;\n  // Reversed version of rdata_outstanding_q which can be overlaid with fifo fill state\n  for (genvar i = 0; i < NUM_REQS; i++) begin : gen_rd_rev\n    assign rdata_outstanding_rev[i] = rdata_outstanding_q[NUM_REQS-1-i];\n  end\n  // The fifo is ready to accept a new request if it is not full - including space reserved for\n  // requests already outstanding.\n  // Overlay the fifo fill state with the outstanding requests to see if there is space.\n  assign fifo_ready = ~&(fifo_busy | rdata_outstanding_rev);\n  cve2_fetch_fifo #(\n    .NUM_REQS (NUM_REQS)\n  ) fifo_i (\n      .clk_i                 ( clk_i             ),\n      .rst_ni                ( rst_ni            ),\n      .clear_i               ( fifo_clear        ),\n      .busy_o                ( fifo_busy         ),\n      .in_valid_i            ( fifo_valid        ),\n      .in_addr_i             ( fifo_addr         ),\n      .in_rdata_i            ( instr_rdata_i     ),\n      .in_err_i              ( instr_err_i       ),\n      .out_valid_o           ( valid_raw         ),\n      .out_ready_i           ( ready_i           ),\n      .out_rdata_o           ( rdata_o           ),\n      .out_addr_o            ( addr_o            ),\n      .out_err_o             ( err_o             ),\n      .out_err_plus2_o       ( err_plus2_o       )\n  );\n  //////////////\n  // Requests //\n  //////////////\n  // Make a new request any time there is space in the FIFO, and space in the request queue\n  assign valid_new_req = req_i & (fifo_ready | branch_i) &\n                         ~rdata_outstanding_q[NUM_REQS-1];\n  assign valid_req = valid_req_q | valid_new_req;\n  // Hold the request stable for requests that didn't get granted\n  assign valid_req_d = valid_req & ~instr_gnt_i;\n  // Record whether an outstanding bus request is cancelled by a branch\n  assign discard_req_d = valid_req_q & (branch_i | discard_req_q);\n  ////////////////\n  // Fetch addr //\n  ////////////////\n  // Two addresses are tracked in the prefetch buffer:\n  // 1. stored_addr_q - This is the address issued on the bus. It stays stable until\n  //                    the request is granted.\n  // 2. fetch_addr_q  - This is our next address to fetch from. It is updated on branches to\n  //                    capture the new address, and then for each new request issued.\n  // A third address is tracked in the fetch FIFO itself:\n  // 3. instr_addr_q  - This is the address at the head of the FIFO, efectively our oldest fetched\n  //                    address. This address is updated on branches, and does its own increment\n  //                    each time the FIFO is popped.\n  // 1. stored_addr_q\n  // Only update stored_addr_q for new ungranted requests\n  assign stored_addr_en = valid_new_req & ~valid_req_q & ~instr_gnt_i;\n  // Store whatever address was issued on the bus\n  assign stored_addr_d = instr_addr;\n  // CPU resets with a branch, so no need to reset these addresses\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      stored_addr_q <= '0;\n    end else if (stored_addr_en) begin\n      stored_addr_q <= stored_addr_d;\n    end\n  end\n  // 2. fetch_addr_q\n  // Update on a branch or as soon as a request is issued\n  assign fetch_addr_en = branch_i | (valid_new_req & ~valid_req_q);\n  assign fetch_addr_d = (branch_i            ? addr_i :\n                                               {fetch_addr_q[31:2], 2'b00}) +\n                        // Current address + 4\n                        {{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00};\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      fetch_addr_q <= '0;\n    end else if (fetch_addr_en) begin\n      fetch_addr_q <= fetch_addr_d;\n    end\n  end\n  // Address mux\n  assign instr_addr = valid_req_q         ? stored_addr_q :\n                      branch_i            ? addr_i :\n                                            fetch_addr_q;\n  assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};\n  ///////////////////////////////\n  // Request outstanding queue //\n  ///////////////////////////////\n  for (genvar i = 0; i < NUM_REQS; i++) begin : g_outstanding_reqs\n    // Request 0 (always the oldest outstanding request)\n    if (i == 0) begin : g_req0\n      // A request becomes outstanding once granted, and is cleared once the rvalid is received.\n      // Outstanding requests shift down the queue towards entry 0.\n      assign rdata_outstanding_n[i] = (valid_req & instr_gnt_i) |\n                                      rdata_outstanding_q[i];\n      // If a branch is received at any point while a request is outstanding, it must be tracked\n      // to ensure we discard the data once received\n      assign branch_discard_n[i]    = (valid_req & instr_gnt_i & discard_req_d) |\n                                      (branch_i & rdata_outstanding_q[i]) |\n                                      branch_discard_q[i];\n    end else begin : g_reqtop\n    // Entries > 0 consider the FIFO fill state to calculate their next state (by checking\n    // whether the previous entry is valid)\n      assign rdata_outstanding_n[i] = (valid_req & instr_gnt_i &\n                                       rdata_outstanding_q[i-1]) |\n                                      rdata_outstanding_q[i];\n      assign branch_discard_n[i]    = (valid_req & instr_gnt_i & discard_req_d &\n                                       rdata_outstanding_q[i-1]) |\n                                      (branch_i & rdata_outstanding_q[i]) |\n                                      branch_discard_q[i];\n    end\n  end\n  // Shift the entries down on each instr_rvalid_i\n  assign rdata_outstanding_s = instr_rvalid_i ? {1'b0,rdata_outstanding_n[NUM_REQS-1:1]} :\n                                                rdata_outstanding_n;\n  assign branch_discard_s    = instr_rvalid_i ? {1'b0,branch_discard_n[NUM_REQS-1:1]} :\n                                                branch_discard_n;\n  // Push a new entry to the FIFO once complete (and not cancelled by a branch)\n  assign fifo_valid = instr_rvalid_i & ~branch_discard_q[0];\n  assign fifo_addr = addr_i;\n  ///////////////\n  // Registers //\n  ///////////////\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      valid_req_q          <= 1'b0;\n      discard_req_q        <= 1'b0;\n      rdata_outstanding_q  <= 'b0;\n      branch_discard_q     <= 'b0;\n    end else begin\n      valid_req_q          <= valid_req_d;\n      discard_req_q        <= discard_req_d;\n      rdata_outstanding_q  <= rdata_outstanding_s;\n      branch_discard_q     <= branch_discard_s;\n    end\n  end\n  /////////////\n  // Outputs //\n  /////////////\n  assign instr_req_o  = valid_req;\n  assign instr_addr_o = instr_addr_w_aligned;\n  assign valid_o = valid_raw;\nendmodule\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Compressed instruction decoder\n *\n * Decodes RISC-V compressed instructions into their RV32 equivalent.\n * This module is fully combinatorial, clock and reset are used for\n * assertions only.\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n // PRIM_ASSERT_SV\nmodule cve2_compressed_decoder (\n  input  logic        clk_i,\n  input  logic        rst_ni,\n  input  logic        valid_i,\n  input  logic [31:0] instr_i,\n  output logic [31:0] instr_o,\n  output logic        is_compressed_o,\n  output logic        illegal_instr_o\n);\n  import cve2_pkg::*;\n  // valid_i indicates if instr_i is valid and is used for assertions only.\n  // The following signal is used to avoid possible lint errors.\n  logic unused_valid;\n  assign unused_valid = valid_i;\n  ////////////////////////\n  // Compressed decoder //\n  ////////////////////////\n  always_comb begin\n    // By default, forward incoming instruction, mark it as legal.\n    instr_o         = instr_i;\n    illegal_instr_o = 1'b0;\n    // Check if incoming instruction is compressed.\n    unique case (instr_i[1:0])\n      // C0\n      2'b00: begin\n        unique case (instr_i[15:13])\n          3'b000: begin\n            // c.addi4spn -> addi rd', x2, imm\n            instr_o = {2'b0, instr_i[10:7], instr_i[12:11], instr_i[5],\n                       instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {OPCODE_OP_IMM}};\n            if (instr_i[12:5] == 8'b0)  illegal_instr_o = 1'b1;\n          end\n          3'b010: begin\n            // c.lw -> lw rd', imm(rs1')\n            instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6],\n                       2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD}};\n          end\n          3'b110: begin\n            // c.sw -> sw rs2', imm(rs1')\n            instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2],\n                       2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6],\n                       2'b00, {OPCODE_STORE}};\n          end\n          3'b001,\n          3'b011,\n          3'b100,\n          3'b101,\n          3'b111: begin\n            illegal_instr_o = 1'b1;\n          end\n          default: begin\n            illegal_instr_o = 1'b1;\n          end\n        endcase\n      end\n      // C1\n      //\n      // Register address checks for RV32E are performed in the regular instruction decoder.\n      // If this check fails, an illegal instruction exception is triggered and the controller\n      // writes the actual faulting instruction to mtval.\n      2'b01: begin\n        unique case (instr_i[15:13])\n          3'b000: begin\n            // c.addi -> addi rd, rd, nzimm\n            // c.nop\n            instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2],\n                       instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP_IMM}};\n          end\n          3'b001, 3'b101: begin\n            // 001: c.jal -> jal x1, imm\n            // 101: c.j   -> jal x0, imm\n            instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6],\n                       instr_i[7], instr_i[2], instr_i[11], instr_i[5:3],\n                       {9 {instr_i[12]}}, 4'b0, ~instr_i[15], {OPCODE_JAL}};\n          end\n          3'b010: begin\n            // c.li -> addi rd, x0, nzimm\n            // (c.li hints are translated into an addi hint)\n            instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b0,\n                       3'b0, instr_i[11:7], {OPCODE_OP_IMM}};\n          end\n          3'b011: begin\n            // c.lui -> lui rd, imm\n            // (c.lui hints are translated into a lui hint)\n            instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {OPCODE_LUI}};\n            if (instr_i[11:7] == 5'h02) begin\n              // c.addi16sp -> addi x2, x2, nzimm\n              instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2],\n                         instr_i[6], 4'b0, 5'h02, 3'b000, 5'h02, {OPCODE_OP_IMM}};\n            end\n            if ({instr_i[12], instr_i[6:2]} == 6'b0) illegal_instr_o = 1'b1;\n          end\n          3'b100: begin\n            unique case (instr_i[11:10])\n              2'b00,\n              2'b01: begin\n                // 00: c.srli -> srli rd, rd, shamt\n                // 01: c.srai -> srai rd, rd, shamt\n                // (c.srli/c.srai hints are translated into a srli/srai hint)\n                instr_o = {1'b0, instr_i[10], 5'b0, instr_i[6:2], 2'b01, instr_i[9:7],\n                           3'b101, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};\n                if (instr_i[12] == 1'b1)  illegal_instr_o = 1'b1;\n              end\n              2'b10: begin\n                // c.andi -> andi rd, rd, imm\n                instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7],\n                           3'b111, 2'b01, instr_i[9:7], {OPCODE_OP_IMM}};\n              end\n              2'b11: begin\n                unique case ({instr_i[12], instr_i[6:5]})\n                  3'b000: begin\n                    // c.sub -> sub rd', rd', rs2'\n                    instr_o = {2'b01, 5'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7],\n                               3'b000, 2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b001: begin\n                    // c.xor -> xor rd', rd', rs2'\n                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100,\n                               2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b010: begin\n                    // c.or  -> or  rd', rd', rs2'\n                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110,\n                               2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b011: begin\n                    // c.and -> and rd', rd', rs2'\n                    instr_o = {7'b0, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111,\n                               2'b01, instr_i[9:7], {OPCODE_OP}};\n                  end\n                  3'b100,\n                  3'b101,\n                  3'b110,\n                  3'b111: begin\n                    // 100: c.subw\n                    // 101: c.addw\n                    illegal_instr_o = 1'b1;\n                  end\n                  default: begin\n                    illegal_instr_o = 1'b1;\n                  end\n                endcase\n              end\n              default: begin\n                illegal_instr_o = 1'b1;\n              end\n            endcase\n          end\n          3'b110, 3'b111: begin\n            // 0: c.beqz -> beq rs1', x0, imm\n            // 1: c.bnez -> bne rs1', x0, imm\n            instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b0, 2'b01,\n                       instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3],\n                       instr_i[12], {OPCODE_BRANCH}};\n          end\n          default: begin\n            illegal_instr_o = 1'b1;\n          end\n        endcase\n      end\n      // C2\n      //\n      // Register address checks for RV32E are performed in the regular instruction decoder.\n      // If this check fails, an illegal instruction exception is triggered and the controller\n      // writes the actual faulting instruction to mtval.\n      2'b10: begin\n        unique case (instr_i[15:13])\n          3'b000: begin\n            // c.slli -> slli rd, rd, shamt\n            // (c.ssli hints are translated into a slli hint)\n            instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {OPCODE_OP_IMM}};\n            if (instr_i[12] == 1'b1)  illegal_instr_o = 1'b1; // reserved for custom extensions\n          end\n          3'b010: begin\n            // c.lwsp -> lw rd, imm(x2)\n            instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02,\n                       3'b010, instr_i[11:7], OPCODE_LOAD};\n            if (instr_i[11:7] == 5'b0)  illegal_instr_o = 1'b1;\n          end\n          3'b100: begin\n            if (instr_i[12] == 1'b0) begin\n              if (instr_i[6:2] != 5'b0) begin\n                // c.mv -> add rd/rs1, x0, rs2\n                // (c.mv hints are translated into an add hint)\n                instr_o = {7'b0, instr_i[6:2], 5'b0, 3'b0, instr_i[11:7], {OPCODE_OP}};\n              end else begin\n                // c.jr -> jalr x0, rd/rs1, 0\n                instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}};\n                if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;\n              end\n            end else begin\n              if (instr_i[6:2] != 5'b0) begin\n                // c.add -> add rd, rd, rs2\n                // (c.add hints are translated into an add hint)\n                instr_o = {7'b0, instr_i[6:2], instr_i[11:7], 3'b0, instr_i[11:7], {OPCODE_OP}};\n              end else begin\n                if (instr_i[11:7] == 5'b0) begin\n                  // c.ebreak -> ebreak\n                  instr_o = {32'h00_10_00_73};\n                end else begin\n                  // c.jalr -> jalr x1, rs1, 0\n                  instr_o = {12'b0, instr_i[11:7], 3'b000, 5'b00001, {OPCODE_JALR}};\n                end\n              end\n            end\n          end\n          3'b110: begin\n            // c.swsp -> sw rs2, imm(x2)\n            instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010,\n                       instr_i[11:9], 2'b00, {OPCODE_STORE}};\n          end\n          3'b001,\n          3'b011,\n          3'b101,\n          3'b111: begin\n            illegal_instr_o = 1'b1;\n          end\n          default: begin\n            illegal_instr_o = 1'b1;\n          end\n        endcase\n      end\n      // Incoming instruction is not compressed.\n      2'b11:;\n      default: begin\n        illegal_instr_o = 1'b1;\n      end\n    endcase\n  end\n  assign is_compressed_o = (instr_i[1:0] != 2'b11);\n  ////////////////\n  // Assertions //\n  ////////////////\n  // The valid_i signal used to gate below assertions must be known.\n  // Selectors must be known/valid.\nendmodule\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Instruction Fetch Stage\n *\n * Instruction fetch unit: Selection of the next PC, and buffering (sampling) of\n * the read instruction.\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n // PRIM_ASSERT_SV\nmodule cve2_if_stage import cve2_pkg::*; (\n  input  logic                         clk_i,\n  input  logic                         rst_ni,\n  input  logic [31:0]                  boot_addr_i,              // also used for mtvec\n  input  logic                         req_i,                    // instruction request control\n  // instruction cache interface\n  output logic                        instr_req_o,\n  output logic [31:0]                 instr_addr_o,\n  input  logic                        instr_gnt_i,\n  input  logic                        instr_rvalid_i,\n  input  logic [31:0]                 instr_rdata_i,\n  input  logic                        instr_err_i,\n  // output of ID stage\n  output logic                        instr_valid_id_o,         // instr in IF-ID is valid\n  output logic                        instr_new_id_o,           // instr in IF-ID is new\n  output logic [31:0]                 instr_rdata_id_o,         // instr for ID stage\n  output logic [31:0]                 instr_rdata_alu_id_o,     // replicated instr for ID stage\n                                                                // to reduce fan-out\n  output logic [15:0]                 instr_rdata_c_id_o,       // compressed instr for ID stage\n                                                                // (mtval), meaningful only if\n                                                                // instr_is_compressed_id_o = 1'b1\n  output logic                        instr_is_compressed_id_o, // compressed decoder thinks this\n                                                                // is a compressed instr\n  output logic                        instr_fetch_err_o,        // bus error on fetch\n  output logic                        instr_fetch_err_plus2_o,  // bus error misaligned\n  output logic                        illegal_c_insn_id_o,      // compressed decoder thinks this\n                                                                // is an invalid instr\n  output logic [31:0]                 pc_if_o,\n  output logic [31:0]                 pc_id_o,\n  input  logic                        pmp_err_if_i,\n  input  logic                        pmp_err_if_plus2_i,\n  // control signals\n  input  logic                        instr_valid_clear_i,      // clear instr valid bit in IF-ID\n  input  logic                        pc_set_i,                 // set the PC to a new value\n  input  pc_sel_e                     pc_mux_i,                 // selector for PC multiplexer\n  input  exc_pc_sel_e                 exc_pc_mux_i,             // selects ISR address\n  input  exc_cause_e                  exc_cause,                // selects ISR address for\n                                                                // vectorized interrupt lines\n  // jump and branch target\n  input  logic [31:0]                 branch_target_ex_i,       // branch/jump target address\n  // CSRs\n  input  logic [31:0]                 csr_mepc_i,               // PC to restore after handling\n                                                                // the interrupt/exception\n  input  logic [31:0]                 csr_depc_i,               // PC to restore after handling\n                                                                // the debug request\n  input  logic [31:0]                 csr_mtvec_i,              // base PC to jump to on exception\n  output logic                        csr_mtvec_init_o,         // tell CS regfile to init mtvec\n  // debug signals\n  input logic [31:0]                  dm_halt_addr_i,           // default 32'h1A110800\n  input logic [31:0]                  dm_exception_addr_i,      // default 32'h1A110808\n  // pipeline stall\n  input  logic                        id_in_ready_i,            // ID stage is ready for new instr\n  // misc signals\n  output logic                        if_busy_o                 // IF stage is busy fetching instr\n);\n  logic              instr_valid_id_d, instr_valid_id_q;\n  logic              instr_new_id_d, instr_new_id_q;\n  // prefetch buffer related signals\n  logic              prefetch_busy;\n  logic              branch_req;\n  logic       [31:0] fetch_addr_n;\n  logic              unused_fetch_addr_n0;\n  logic              fetch_valid;\n  logic              fetch_ready;\n  logic       [31:0] fetch_rdata;\n  logic       [31:0] fetch_addr;\n  logic              fetch_err;\n  logic              fetch_err_plus2;\n  logic [31:0]       instr_decompressed;\n  logic              illegal_c_insn;\n  logic              instr_is_compressed;\n  logic              if_instr_pmp_err;\n  logic              if_instr_err;\n  logic              if_instr_err_plus2;\n  logic       [31:0] exc_pc;\n  logic        [6:0] irq_id;\n  logic              unused_irq_bit;\n  logic              if_id_pipe_reg_we; // IF-ID pipeline reg write enable\n  cve2_pkg::pc_sel_e pc_mux_internal;\n  logic        [1:0] unused_boot_addr;\n  logic        [7:0] unused_csr_mtvec;\n  assign unused_boot_addr = boot_addr_i[1:0];\n  assign unused_csr_mtvec = csr_mtvec_i[7:0];\n  // extract interrupt ID from exception cause\n  assign irq_id         = {exc_cause};\n  assign unused_irq_bit = irq_id[6];   // MSB distinguishes interrupts from exceptions\n  // exception PC selection mux\n  always_comb begin : exc_pc_mux\n    unique case (exc_pc_mux_i)\n      EXC_PC_EXC:     exc_pc = { csr_mtvec_i[31:8], 8'h00              };\n      EXC_PC_IRQ:     exc_pc = { csr_mtvec_i[31:8], irq_id[5:0], 2'b00 };\n      EXC_PC_DBD:     exc_pc = dm_halt_addr_i;\n      EXC_PC_DBG_EXC: exc_pc = dm_exception_addr_i;\n      default:        exc_pc = { csr_mtvec_i[31:8], 8'h00              };\n    endcase\n  end\n  assign pc_mux_internal =\n    pc_mux_i;\n  // fetch address selection mux\n  always_comb begin : fetch_addr_mux\n    unique case (pc_mux_internal)\n      PC_BOOT: fetch_addr_n = { boot_addr_i[31:2], 2'b00 };\n      PC_JUMP: fetch_addr_n = branch_target_ex_i;\n      PC_EXC:  fetch_addr_n = exc_pc;                       // set PC to exception handler\n      PC_ERET: fetch_addr_n = csr_mepc_i;                   // restore PC when returning from EXC\n      PC_DRET: fetch_addr_n = csr_depc_i;\n      default: fetch_addr_n = { boot_addr_i[31:2], 2'b00 };\n    endcase\n  end\n  // tell CS register file to initialize mtvec on boot\n  assign csr_mtvec_init_o = (pc_mux_i == PC_BOOT) & pc_set_i;\n  // prefetch buffer, caches a fixed number of instructions\n  cve2_prefetch_buffer #(\n  ) prefetch_buffer_i (\n      .clk_i               ( clk_i                      ),\n      .rst_ni              ( rst_ni                     ),\n      .req_i               ( req_i                      ),\n      .branch_i            ( branch_req                 ),\n      .addr_i              ( {fetch_addr_n[31:1], 1'b0} ),\n      .ready_i             ( fetch_ready                ),\n      .valid_o             ( fetch_valid                ),\n      .rdata_o             ( fetch_rdata                ),\n      .addr_o              ( fetch_addr                 ),\n      .err_o               ( fetch_err                  ),\n      .err_plus2_o         ( fetch_err_plus2            ),\n      .instr_req_o         ( instr_req_o                ),\n      .instr_addr_o        ( instr_addr_o               ),\n      .instr_gnt_i         ( instr_gnt_i                ),\n      .instr_rvalid_i      ( instr_rvalid_i             ),\n      .instr_rdata_i       ( instr_rdata_i              ),\n      .instr_err_i         ( instr_err_i                ),\n      .busy_o              ( prefetch_busy              )\n  );\n  assign unused_fetch_addr_n0 = fetch_addr_n[0];\n  assign branch_req  = pc_set_i;\n  assign pc_if_o     = fetch_addr;\n  assign if_busy_o   = prefetch_busy;\n  // PMP errors\n  // An error can come from the instruction address, or the next instruction address for unaligned,\n  // uncompressed instructions.\n  assign if_instr_pmp_err = pmp_err_if_i |\n                            (fetch_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i);\n  // Combine bus errors and pmp errors\n  assign if_instr_err = fetch_err | if_instr_pmp_err;\n  // Capture the second half of the address for errors on the second part of an instruction\n  assign if_instr_err_plus2 = ((fetch_addr[2] & ~instr_is_compressed & pmp_err_if_plus2_i) |\n                               fetch_err_plus2) & ~pmp_err_if_i;\n  // compressed instruction decoding, or more precisely compressed instruction\n  // expander\n  //\n  // since it does not matter where we decompress instructions, we do it here\n  // to ease timing closure\n  cve2_compressed_decoder compressed_decoder_i (\n    .clk_i          (clk_i),\n    .rst_ni         (rst_ni),\n    .valid_i        (fetch_valid & ~fetch_err),\n    .instr_i        (fetch_rdata),\n    .instr_o        (instr_decompressed),\n    .is_compressed_o(instr_is_compressed),\n    .illegal_instr_o(illegal_c_insn)\n  );\n  // The ID stage becomes valid as soon as any instruction is registered in the ID stage flops.\n  // Note that the current instruction is squashed by the incoming pc_set_i signal.\n  // Valid is held until it is explicitly cleared (due to an instruction completing or an exception)\n  assign instr_valid_id_d = (fetch_valid & id_in_ready_i & ~pc_set_i) |\n                            (instr_valid_id_q & ~instr_valid_clear_i);\n  assign instr_new_id_d   = fetch_valid & id_in_ready_i;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      instr_valid_id_q <= 1'b0;\n      instr_new_id_q   <= 1'b0;\n    end else begin\n      instr_valid_id_q <= instr_valid_id_d;\n      instr_new_id_q   <= instr_new_id_d;\n    end\n  end\n  assign instr_valid_id_o = instr_valid_id_q;\n  // Signal when a new instruction enters the ID stage (only used for RVFI signalling).\n  assign instr_new_id_o   = instr_new_id_q;\n  // IF-ID pipeline registers, frozen when the ID stage is stalled\n  assign if_id_pipe_reg_we = instr_new_id_d;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      instr_rdata_id_o         <= '0;\n      instr_rdata_alu_id_o     <= '0;\n      instr_fetch_err_o        <= '0;\n      instr_fetch_err_plus2_o  <= '0;\n      instr_rdata_c_id_o       <= '0;\n      instr_is_compressed_id_o <= '0;\n      illegal_c_insn_id_o      <= '0;\n      pc_id_o                  <= '0;\n    end else if (if_id_pipe_reg_we) begin\n      instr_rdata_id_o         <= instr_decompressed;\n      // To reduce fan-out and help timing from the instr_rdata_id flops they are replicated.\n      instr_rdata_alu_id_o     <= instr_decompressed;\n      instr_fetch_err_o        <= if_instr_err;\n      instr_fetch_err_plus2_o  <= if_instr_err_plus2;\n      instr_rdata_c_id_o       <= fetch_rdata[15:0]; //if_instr_rdata[15:0];\n      instr_is_compressed_id_o <= instr_is_compressed;\n      illegal_c_insn_id_o      <= illegal_c_insn;\n      pc_id_o                  <= pc_if_o;\n    end\n  end\n  assign fetch_ready = id_in_ready_i;\n  ////////////////\n  // Assertions //\n  ////////////////\n  // Selectors must be known/valid.\n  // Boot address must be aligned to 4 bytes.\n  // Address must not contain X when request is sent.\n  // Address must be word aligned when request is sent.\nendmodule\n", "mask_idx": {"conditional_statement": [[49325, 50498], [61387, 61582], [45093, 45357], [45370, 45434], [37762, 37888], [31076, 31168], [37224, 37295], [31297, 31493], [31389, 31493], [62272, 62837]], "blocking_assignment": [[42663, 42818], [49079, 49210], [44735, 44859], [43219, 43408], [45411, 45434], [47217, 47349], [27401, 27423], [57852, 57896], [57523, 57547]], "module_program_interface_instantiation": [[58435, 59548], [34716, 35504], [60533, 60848]], "always_construct": [[28218, 28405], [26997, 27498], [57291, 57691], [42285, 51111], [57768, 58255], [40306, 40741], [61881, 62843], [37707, 37894], [37110, 37301], [61332, 61588], [31238, 31503], [31021, 31174]], "case_statement": [[42551, 43659], [42485, 51105], [57807, 58249], [57326, 57685], [48635, 50957], [46291, 47740], [45485, 47865], [43964, 48330]], "ansi_port_declaration": [[23073, 23107], [23245, 23280], [23481, 23521], [23382, 23421], [52311, 52404], [32392, 32419], [32538, 32570], [32716, 32751]], "continuous_assign": [[57133, 57169], [60025, 60076], [30524, 30621], [29436, 29493], [24781, 24820], [30775, 30851], [39928, 40079], [27661, 27722], [24673, 24725]], "parameter_declaration": [[13622, 13688], [13787, 13814], [16993, 17037], [16708, 16752], [23031, 23066], [16802, 16847], [16755, 16799], [16946, 16990]], "nonblocking_assignment": [[28362, 28391], [62307, 62354], [62611, 62681], [62509, 62550], [40547, 40583], [31458, 31481], [37256, 37287], [31422, 31447], [40635, 40679], [62557, 62604], [62743, 62786], [40686, 40727], [62688, 62736], [37851, 37880], [40590, 40628], [61495, 61532], [62455, 62502], [61539, 61574], [31141, 31160], [62793, 62829]]}, "all_mask_idx": {"module_program_interface_instantiation": [[34716, 35504], [58435, 59548], [60533, 60848]], "continuous_assign": [[24673, 24725], [24728, 24778], [24781, 24820], [25392, 25538], [25929, 26183], [26349, 26488], [26576, 26687], [26734, 26798], [26801, 26865], [27661, 27722], [27805, 27937], [27940, 28112], [28115, 28215], [28446, 28492], [28575, 28612], [28892, 28940], [29114, 29201], [29353, 29395], [29436, 29493], [29589, 29692], [29745, 29817], [29866, 29913], [29990, 30205], [30258, 30320], [30325, 30385], [30448, 30521], [30524, 30621], [30624, 30700], [30703, 30772], [30775, 30851], [30854, 30901], [30904, 30949], [33753, 33806], [34177, 34206], [34358, 34426], [34655, 34713], [35650, 35765], [35768, 35815], [35884, 35930], [36005, 36069], [36885, 36953], [37006, 37040], [37383, 37448], [37451, 37704], [37914, 38082], [38085, 38141], [38570, 38691], [38848, 39058], [39230, 39417], [39424, 39700], [39768, 39925], [39928, 40079], [40162, 40220], [40223, 40249], [40792, 40824], [40827, 40870], [40873, 40900], [42171, 42201], [51114, 51163], [56994, 57037], [57040, 57083], [57133, 57169], [57172, 57256], [57694, 57732], [58313, 58372], [59551, 59597], [59600, 59630], [59633, 59665], [59668, 59703], [59854, 59983], [60025, 60076], [60171, 60326], [61132, 61272], [61275, 61329], [61591, 61634], [61725, 61766], [61836, 61878], [62846, 62881]], "blocking_assignment": [[27074, 27108], [27115, 27147], [27154, 27182], [27232, 27252], [27282, 27312], [27370, 27394], [27401, 27423], [27430, 27453], [27460, 27484], [42374, 42400], [42405, 42428], [42663, 42818], [42859, 42882], [42974, 43126], [43219, 43408], [43531, 43554], [43606, 43629], [44094, 44227], [44368, 44581], [44735, 44859], [45006, 45080], [45191, 45341], [45411, 45434], [45760, 45904], [45947, 45970], [46078, 46229], [46436, 46575], [46701, 46833], [46959, 47091], [47217, 47349], [47572, 47595], [47671, 47694], [47804, 47827], [48016, 48225], [48277, 48300], [48806, 48892], [48931, 48988], [49079, 49210], [49251, 49274], [49529, 49600], [49692, 49752], [49796, 49819], [50036, 50116], [50253, 50281], [50378, 50444], [50590, 50724], [50829, 50852], [50904, 50927], [51060, 51083], [57375, 57426], [57449, 57500], [57523, 57547], [57570, 57599], [57622, 57673], [57852, 57896], [57912, 57946], [57962, 58037], [58053, 58135], [58151, 58177], [58193, 58237]], "nonblocking_assignment": [[28298, 28317], [28362, 28391], [31101, 31115], [31141, 31160], [31326, 31343], [31354, 31371], [31422, 31447], [31458, 31481], [37190, 37210], [37256, 37287], [37787, 37806], [37851, 37880], [40386, 40415], [40422, 40451], [40458, 40486], [40493, 40521], [40547, 40583], [40590, 40628], [40635, 40679], [40686, 40727], [61412, 61437], [61444, 61469], [61495, 61532], [61539, 61574], [61961, 61992], [61999, 62030], [62037, 62068], [62075, 62106], [62113, 62144], [62151, 62182], [62189, 62220], [62227, 62258], [62307, 62354], [62455, 62502], [62509, 62550], [62557, 62604], [62611, 62681], [62688, 62736], [62743, 62786], [62793, 62829]], "case_statement": [[42485, 51105], [42551, 43659], [43964, 48330], [45485, 47865], [46291, 47740], [48635, 50957], [57326, 57685], [57807, 58249]], "conditional_statement": [[27019, 27492], [27189, 27322], [28273, 28399], [28331, 28399], [31076, 31168], [31297, 31493], [31389, 31493], [37165, 37295], [37224, 37295], [37762, 37888], [37820, 37888], [40361, 40735], [42831, 42882], [45093, 45357], [45370, 45434], [45921, 45970], [48905, 48988], [49223, 49274], [49325, 50498], [49370, 49837], [49769, 49819], [49879, 50482], [50162, 50464], [61387, 61582], [61936, 62837], [62272, 62837]], "always_construct": [[26997, 27498], [28218, 28405], [31021, 31174], [31238, 31503], [37110, 37301], [37707, 37894], [40306, 40741], [42285, 51111], [57291, 57691], [57768, 58255], [61332, 61588], [61881, 62843]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096], [23031, 23066]], "ansi_port_declaration": [[23073, 23107], [23110, 23145], [23169, 23242], [23245, 23280], [23299, 23338], [23341, 23379], [23382, 23421], [23424, 23461], [23481, 23521], [23524, 23564], [23567, 23606], [23609, 23649], [23652, 23690], [23693, 23736], [32149, 32175], [32178, 32205], [32208, 32234], [32237, 32266], [32269, 32296], [32299, 32327], [32330, 32358], [32361, 32389], [32392, 32419], [32422, 32448], [32451, 32483], [32538, 32570], [32573, 32605], [32608, 32641], [32644, 32678], [32681, 32713], [32716, 32751], [32782, 32808], [41754, 41780], [41783, 41810], [41813, 41841], [41844, 41872], [41875, 41903], [41906, 41942], [41945, 41980], [52130, 52173], [52176, 52220], [52223, 52308], [52311, 52404], [52440, 52488], [52491, 52540], [52543, 52591], [52594, 52645], [52648, 52698], [52701, 52749], [52776, 52864], [52867, 52953], [52956, 53039], [53042, 53136], [53224, 53318], [53515, 53610], [53702, 53785], [53788, 53873], [53876, 53971], [54061, 54105], [54108, 54152], [54155, 54204], [54207, 54262], [54286, 54381], [54384, 54474], [54477, 54569], [54572, 54656], [54659, 54747], [54872, 54963], [54976, 55069], [55163, 55256], [55344, 55440], [55443, 55537], [55559, 55644], [55647, 55732], [55755, 55851], [55872, 55968]]}}
{"sample_i": "p8", "topmodule": "cve2_load_store_unit", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Load Store Unit\n *\n * Load Store Unit, used to eliminate multiple access during processor stalls,\n * and to align bytes and halfwords.\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Include FCOV RTL by default. Disable it for synthesis and where explicitly requested (by defining\n// DV_FCOV_DISABLE).\n// Disable instantiations of FCOV coverpoints or covergroups.\n// Instantiates a covergroup in an interface or module.\n//\n// This macro assumes that a covergroup of the same name as the NAME_ arg is defined in the\n// interface or module. It just adds some extra signals and logic to control the creation of the\n// covergroup instance with ~bit en_<cg_name>~. This defaults to 0. It is ORed with the external\n// COND_ signal. The testbench can modify it at t = 0 based on the test being run.\n// NOTE: This is not meant to be invoked inside a class.\n//\n// NAME_ : Name of the covergroup.\n// COND_ : External condition / expr that controls the creation of the covergroup.\n// ARGS_ : Arguments to covergroup instance, if any. Args MUST BE wrapped in (..).\n// Creates a coverpoint for an expression where only the expression true case is of interest for\n// coverage (e.g. where the expression indicates an event has occured).\n// Creates a SVA cover that can be used in a covergroup.\n//\n// This macro creates an unnamed SVA cover from the property (or an expression) `PROP_` and an event\n// with the name `EV_NAME_`. When the SVA cover is hit, the event is triggered. A coverpoint can\n// cover the `triggered` property of the event.\n// Coverage support is not always available but it's useful to include extra fcov signals for\n// linting purposes. They need to be marked as unused to avoid warnings.\n// Define a signal and expression in the design for capture in functional coverage\n// Define a signal and expression in the design for capture in functional coverage depending on\n// design configuration. The input GEN_COND_ must be a constant or parameter.\nmodule cve2_load_store_unit\n(\n  input  logic         clk_i,\n  input  logic         rst_ni,\n  // data interface\n  output logic         data_req_o,\n  input  logic         data_gnt_i,\n  input  logic         data_rvalid_i,\n  input  logic         data_err_i,\n  input  logic         data_pmp_err_i,\n  output logic [31:0]  data_addr_o,\n  output logic         data_we_o,\n  output logic [3:0]   data_be_o,\n  output logic [31:0]  data_wdata_o,\n  input  logic [31:0]  data_rdata_i,\n  // signals to/from ID/EX stage\n  input  logic         lsu_we_i,             // write enable                     -> from ID/EX\n  input  logic [1:0]   lsu_type_i,           // data type: word, half word, byte -> from ID/EX\n  input  logic [31:0]  lsu_wdata_i,          // data to write to memory          -> from ID/EX\n  input  logic         lsu_sign_ext_i,       // sign extension                   -> from ID/EX\n  output logic [31:0]  lsu_rdata_o,          // requested data                   -> to ID/EX\n  output logic         lsu_rdata_valid_o,\n  input  logic         lsu_req_i,            // data request                     -> from ID/EX\n  input  logic [31:0]  adder_result_ex_i,    // address computed in ALU          -> from ID/EX\n  output logic         addr_incr_req_o,      // request address increment for\n                                              // misaligned accesses              -> to ID/EX\n  output logic [31:0]  addr_last_o,          // address of last transaction      -> to controller\n                                              // -> mtval\n                                              // -> AGU for misaligned accesses\n  output logic         lsu_resp_valid_o,     // LSU has response from transaction -> to ID/EX\n  // exception signals\n  output logic         load_err_o,\n  output logic         store_err_o,\n  output logic         busy_o,\n  output logic         perf_load_o,\n  output logic         perf_store_o\n);\n  logic [31:0]  data_addr;\n  logic [31:0]  data_addr_w_aligned;\n  logic [31:0]  addr_last_q, addr_last_d;\n  logic         addr_update;\n  logic         ctrl_update;\n  logic         rdata_update;\n  logic [31:8]  rdata_q;\n  logic [1:0]   rdata_offset_q;\n  logic [1:0]   data_type_q;\n  logic         data_sign_ext_q;\n  logic         data_we_q;\n  logic [1:0]   data_offset;   // mux control for data to be written to memory\n  logic [3:0]   data_be;\n  logic [31:0]  data_wdata;\n  logic [31:0]  data_rdata_ext;\n  logic [31:0]  rdata_w_ext; // word realignment for misaligned loads\n  logic [31:0]  rdata_h_ext; // sign extension for half words\n  logic [31:0]  rdata_b_ext; // sign extension for bytes\n  logic         split_misaligned_access;\n  logic         handle_misaligned_q, handle_misaligned_d; // high after receiving grant for first\n                                                          // part of a misaligned access\n  logic         pmp_err_q, pmp_err_d;\n  logic         lsu_err_q, lsu_err_d;\n  logic         data_or_pmp_err;\n  typedef enum logic [2:0]  {\n    IDLE, WAIT_GNT_MIS, WAIT_RVALID_MIS, WAIT_GNT,\n    WAIT_RVALID_MIS_GNTS_DONE\n  } ls_fsm_e;\n  ls_fsm_e ls_fsm_cs, ls_fsm_ns;\n  assign data_addr   = adder_result_ex_i;\n  assign data_offset = data_addr[1:0];\n  ///////////////////\n  // BE generation //\n  ///////////////////\n  always_comb begin\n    unique case (lsu_type_i) // Data type 00 Word, 01 Half word, 11,10 byte\n      2'b00: begin // Writing a word\n        if (!handle_misaligned_q) begin // first part of potentially misaligned transaction\n          unique case (data_offset)\n            2'b00:   data_be = 4'b1111;\n            2'b01:   data_be = 4'b1110;\n            2'b10:   data_be = 4'b1100;\n            2'b11:   data_be = 4'b1000;\n            default: data_be = 4'b1111;\n          endcase // case (data_offset)\n        end else begin // second part of misaligned transaction\n          unique case (data_offset)\n            2'b00:   data_be = 4'b0000; // this is not used, but included for completeness\n            2'b01:   data_be = 4'b0001;\n            2'b10:   data_be = 4'b0011;\n            2'b11:   data_be = 4'b0111;\n            default: data_be = 4'b1111;\n          endcase // case (data_offset)\n        end\n      end\n      2'b01: begin // Writing a half word\n        if (!handle_misaligned_q) begin // first part of potentially misaligned transaction\n          unique case (data_offset)\n            2'b00:   data_be = 4'b0011;\n            2'b01:   data_be = 4'b0110;\n            2'b10:   data_be = 4'b1100;\n            2'b11:   data_be = 4'b1000;\n            default: data_be = 4'b1111;\n          endcase // case (data_offset)\n        end else begin // second part of misaligned transaction\n          data_be = 4'b0001;\n        end\n      end\n      2'b10,\n      2'b11: begin // Writing a byte\n        unique case (data_offset)\n          2'b00:   data_be = 4'b0001;\n          2'b01:   data_be = 4'b0010;\n          2'b10:   data_be = 4'b0100;\n          2'b11:   data_be = 4'b1000;\n          default: data_be = 4'b1111;\n        endcase // case (data_offset)\n      end\n      default:     data_be = 4'b1111;\n    endcase // case (lsu_type_i)\n  end\n  /////////////////////\n  // WData alignment //\n  /////////////////////\n  // prepare data to be written to the memory\n  // we handle misaligned accesses, half word and byte accesses here\n  always_comb begin\n    unique case (data_offset)\n      2'b00:   data_wdata =  lsu_wdata_i[31:0];\n      2'b01:   data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]};\n      2'b10:   data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]};\n      2'b11:   data_wdata = {lsu_wdata_i[ 7:0], lsu_wdata_i[31: 8]};\n      default: data_wdata =  lsu_wdata_i[31:0];\n    endcase // case (data_offset)\n  end\n  /////////////////////\n  // RData alignment //\n  /////////////////////\n  // register for unaligned rdata\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      rdata_q <= '0;\n    end else if (rdata_update) begin\n      rdata_q <= data_rdata_i[31:8];\n    end\n  end\n  // registers for transaction control\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      rdata_offset_q  <= 2'h0;\n      data_type_q     <= 2'h0;\n      data_sign_ext_q <= 1'b0;\n      data_we_q       <= 1'b0;\n    end else if (ctrl_update) begin\n      rdata_offset_q  <= data_offset;\n      data_type_q     <= lsu_type_i;\n      data_sign_ext_q <= lsu_sign_ext_i;\n      data_we_q       <= lsu_we_i;\n    end\n  end\n  // Store last address for mtval + AGU for misaligned transactions.  Do not update in case of\n  // errors, mtval needs the (first) failing address.  Where an aligned access or the first half of\n  // a misaligned access sees an error provide the calculated access address. For the second half of\n  // a misaligned access provide the word aligned address of the second half.\n  assign addr_last_d = addr_incr_req_o ? data_addr_w_aligned : data_addr;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      addr_last_q <= '0;\n    end else if (addr_update) begin\n      addr_last_q <= addr_last_d;\n    end\n  end\n  // take care of misaligned words\n  always_comb begin\n    unique case (rdata_offset_q)\n      2'b00:   rdata_w_ext =  data_rdata_i[31:0];\n      2'b01:   rdata_w_ext = {data_rdata_i[ 7:0], rdata_q[31:8]};\n      2'b10:   rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]};\n      2'b11:   rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]};\n      default: rdata_w_ext =  data_rdata_i[31:0];\n    endcase\n  end\n  ////////////////////\n  // Sign extension //\n  ////////////////////\n  // sign extension for half words\n  always_comb begin\n    unique case (rdata_offset_q)\n      2'b00: begin\n        if (!data_sign_ext_q) begin\n          rdata_h_ext = {16'h0000, data_rdata_i[15:0]};\n        end else begin\n          rdata_h_ext = {{16{data_rdata_i[15]}}, data_rdata_i[15:0]};\n        end\n      end\n      2'b01: begin\n        if (!data_sign_ext_q) begin\n          rdata_h_ext = {16'h0000, data_rdata_i[23:8]};\n        end else begin\n          rdata_h_ext = {{16{data_rdata_i[23]}}, data_rdata_i[23:8]};\n        end\n      end\n      2'b10: begin\n        if (!data_sign_ext_q) begin\n          rdata_h_ext = {16'h0000, data_rdata_i[31:16]};\n        end else begin\n          rdata_h_ext = {{16{data_rdata_i[31]}}, data_rdata_i[31:16]};\n        end\n      end\n      2'b11: begin\n        if (!data_sign_ext_q) begin\n          rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]};\n        end else begin\n          rdata_h_ext = {{16{data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]};\n        end\n      end\n      default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]};\n    endcase // case (rdata_offset_q)\n  end\n  // sign extension for bytes\n  always_comb begin\n    unique case (rdata_offset_q)\n      2'b00: begin\n        if (!data_sign_ext_q) begin\n          rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};\n        end else begin\n          rdata_b_ext = {{24{data_rdata_i[7]}}, data_rdata_i[7:0]};\n        end\n      end\n      2'b01: begin\n        if (!data_sign_ext_q) begin\n          rdata_b_ext = {24'h00_0000, data_rdata_i[15:8]};\n        end else begin\n          rdata_b_ext = {{24{data_rdata_i[15]}}, data_rdata_i[15:8]};\n        end\n      end\n      2'b10: begin\n        if (!data_sign_ext_q) begin\n          rdata_b_ext = {24'h00_0000, data_rdata_i[23:16]};\n        end else begin\n          rdata_b_ext = {{24{data_rdata_i[23]}}, data_rdata_i[23:16]};\n        end\n      end\n      2'b11: begin\n        if (!data_sign_ext_q) begin\n          rdata_b_ext = {24'h00_0000, data_rdata_i[31:24]};\n        end else begin\n          rdata_b_ext = {{24{data_rdata_i[31]}}, data_rdata_i[31:24]};\n        end\n      end\n      default: rdata_b_ext = {24'h00_0000, data_rdata_i[7:0]};\n    endcase // case (rdata_offset_q)\n  end\n  // select word, half word or byte sign extended version\n  always_comb begin\n    unique case (data_type_q)\n      2'b00:       data_rdata_ext = rdata_w_ext;\n      2'b01:       data_rdata_ext = rdata_h_ext;\n      2'b10,2'b11: data_rdata_ext = rdata_b_ext;\n      default:     data_rdata_ext = rdata_w_ext;\n    endcase // case (data_type_q)\n  end\n  /////////////\n  // LSU FSM //\n  /////////////\n  // check for misaligned accesses that need to be split into two word-aligned accesses\n  assign split_misaligned_access =\n      ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || // misaligned word access\n      ((lsu_type_i == 2'b01) && (data_offset == 2'b11));   // misaligned half-word access\n  // FSM\n  always_comb begin\n    ls_fsm_ns       = ls_fsm_cs;\n    data_req_o          = 1'b0;\n    addr_incr_req_o     = 1'b0;\n    handle_misaligned_d = handle_misaligned_q;\n    pmp_err_d           = pmp_err_q;\n    lsu_err_d           = lsu_err_q;\n    addr_update         = 1'b0;\n    ctrl_update         = 1'b0;\n    rdata_update        = 1'b0;\n    perf_load_o         = 1'b0;\n    perf_store_o        = 1'b0;\n    unique case (ls_fsm_cs)\n      IDLE: begin\n        pmp_err_d = 1'b0;\n        if (lsu_req_i) begin\n          data_req_o   = 1'b1;\n          pmp_err_d    = data_pmp_err_i;\n          lsu_err_d    = 1'b0;\n          perf_load_o  = ~lsu_we_i;\n          perf_store_o = lsu_we_i;\n          if (data_gnt_i) begin\n            ctrl_update         = 1'b1;\n            addr_update         = 1'b1;\n            handle_misaligned_d = split_misaligned_access;\n            ls_fsm_ns           = split_misaligned_access ? WAIT_RVALID_MIS : IDLE;\n          end else begin\n            ls_fsm_ns           = split_misaligned_access ? WAIT_GNT_MIS    : WAIT_GNT;\n          end\n        end\n      end\n      WAIT_GNT_MIS: begin\n        data_req_o = 1'b1;\n        // data_pmp_err_i is valid during the address phase of a request. An error will block the\n        // external request and so a data_gnt_i might never be signalled. The registered version\n        // pmp_err_q is only updated for new address phases and so can be used in WAIT_GNT* and\n        // WAIT_RVALID* states\n        if (data_gnt_i || pmp_err_q) begin\n          addr_update         = 1'b1;\n          ctrl_update         = 1'b1;\n          handle_misaligned_d = 1'b1;\n          ls_fsm_ns           = WAIT_RVALID_MIS;\n        end\n      end\n      WAIT_RVALID_MIS: begin\n        // push out second request\n        data_req_o = 1'b1;\n        // tell ID/EX stage to update the address\n        addr_incr_req_o = 1'b1;\n        // first part rvalid is received, or gets a PMP error\n        if (data_rvalid_i || pmp_err_q) begin\n          // Update the PMP error for the second part\n          pmp_err_d = data_pmp_err_i;\n          // Record the error status of the first part\n          lsu_err_d = data_err_i | pmp_err_q;\n          // Capture the first rdata for loads\n          rdata_update = ~data_we_q;\n          // If already granted, wait for second rvalid\n          ls_fsm_ns = data_gnt_i ? IDLE : WAIT_GNT;\n          // Update the address for the second part, if no error\n          addr_update = data_gnt_i & ~(data_err_i | pmp_err_q);\n          // clear handle_misaligned if second request is granted\n          handle_misaligned_d = ~data_gnt_i;\n        end else begin\n          // first part rvalid is NOT received\n          if (data_gnt_i) begin\n            // second grant is received\n            ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE;\n            handle_misaligned_d = 1'b0;\n          end\n        end\n      end\n      WAIT_GNT: begin\n        // tell ID/EX stage to update the address\n        addr_incr_req_o = handle_misaligned_q;\n        data_req_o      = 1'b1;\n        if (data_gnt_i || pmp_err_q) begin\n          ctrl_update         = 1'b1;\n          // Update the address, unless there was an error\n          addr_update         = ~lsu_err_q;\n          ls_fsm_ns           = IDLE;\n          handle_misaligned_d = 1'b0;\n        end\n      end\n      WAIT_RVALID_MIS_GNTS_DONE: begin\n        // tell ID/EX stage to update the address (to make sure the\n        // second address can be captured correctly for mtval and PMP checking)\n        addr_incr_req_o = 1'b1;\n        // Wait for the first rvalid, second request is already granted\n        if (data_rvalid_i) begin\n          // Update the pmp error for the second part\n          pmp_err_d = data_pmp_err_i;\n          // The first part cannot see a PMP error in this state\n          lsu_err_d = data_err_i;\n          // Now we can update the address for the second part if no error\n          addr_update = ~data_err_i;\n          // Capture the first rdata for loads\n          rdata_update = ~data_we_q;\n          // Wait for second rvalid\n          ls_fsm_ns = IDLE;\n        end\n      end\n      default: begin\n        ls_fsm_ns = IDLE;\n      end\n    endcase\n  end\n  // registers for FSM\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      ls_fsm_cs           <= IDLE;\n      handle_misaligned_q <= '0;\n      pmp_err_q           <= '0;\n      lsu_err_q           <= '0;\n    end else begin\n      ls_fsm_cs           <= ls_fsm_ns;\n      handle_misaligned_q <= handle_misaligned_d;\n      pmp_err_q           <= pmp_err_d;\n      lsu_err_q           <= lsu_err_d;\n    end\n  end\n  /////////////\n  // Outputs //\n  /////////////\n  assign data_or_pmp_err    = lsu_err_q | data_err_i | pmp_err_q;\n  assign lsu_resp_valid_o   = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE);\n  assign lsu_rdata_valid_o  = (ls_fsm_cs == IDLE) & data_rvalid_i & ~data_or_pmp_err & ~data_we_q;\n  // output to register file\n  assign lsu_rdata_o = data_rdata_ext;\n  // output data address must be word aligned\n  assign data_addr_w_aligned = {data_addr[31:2], 2'b00};\n  // output to data interface\n  assign data_addr_o   = data_addr_w_aligned;\n  assign data_wdata_o  = data_wdata;\n  assign data_we_o     = lsu_we_i;\n  assign data_be_o     = data_be;\n  // output to ID stage: mtval + AGU for misaligned transactions\n  assign addr_last_o   = addr_last_q;\n  // Signal a load or store error depending on the transaction type outstanding\n  assign load_err_o    = data_or_pmp_err & ~data_we_q & lsu_resp_valid_o;\n  assign store_err_o   = data_or_pmp_err &  data_we_q & lsu_resp_valid_o;\n  assign busy_o = (ls_fsm_cs != IDLE);\n  //////////\n  // FCOV //\n  //////////\n  ////////////////\n  // Assertions //\n  ////////////////\n  // Selectors must be known/valid.\n  // Address must not contain X when request is sent.\n  // Address must be word aligned when request is sent.\nendmodule\n", "mask_idx": {"conditional_statement": [[10054, 10816], [20116, 20379], [13567, 13688], [17580, 18168], [14737, 14927], [14285, 14473], [15633, 15824], [20689, 21176], [15862, 16055], [17785, 18156]], "blocking_assignment": [[10626, 10644], [11311, 11329], [20161, 20188], [19406, 19447], [17191, 17218], [18721, 18759], [10235, 10253], [19220, 19255], [14549, 14594], [17683, 17703]], "always_construct": [[14207, 15296], [12439, 12621], [9915, 11750], [15329, 16402], [12663, 13061], [13732, 14100], [17104, 21261], [21287, 21697], [11940, 12330], [16463, 16746], [13512, 13694]], "case_statement": [[13754, 14094], [10488, 10804], [9937, 11744], [14229, 15290], [10971, 11236], [11962, 12324], [16485, 16740], [17504, 21255], [10148, 10413], [15351, 16396], [11410, 11663]], "ansi_port_declaration": [[8050, 8145], [7878, 7953], [7363, 7455], [8438, 8471], [7066, 7100], [7688, 7780], [6998, 7029]], "continuous_assign": [[22195, 22238], [22241, 22275], [22313, 22344], [22604, 22675], [9810, 9846], [21895, 21991], [13438, 13509]], "nonblocking_assignment": [[12903, 12934], [12941, 12971], [21610, 21643], [21560, 21603], [13653, 13680], [13019, 13047], [12577, 12607], [12978, 13012], [21520, 21553], [21650, 21683]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[9768, 9807], [9810, 9846], [13438, 13509], [16885, 17092], [21748, 21811], [21814, 21892], [21895, 21991], [22023, 22059], [22108, 22162], [22195, 22238], [22241, 22275], [22278, 22310], [22313, 22344], [22412, 22447], [22530, 22601], [22604, 22675], [22678, 22714]], "blocking_assignment": [[10195, 10213], [10235, 10253], [10275, 10293], [10315, 10333], [10355, 10373], [10535, 10604], [10626, 10644], [10666, 10684], [10706, 10724], [10746, 10764], [11018, 11036], [11058, 11076], [11098, 11116], [11138, 11156], [11178, 11196], [11311, 11329], [11455, 11473], [11493, 11511], [11531, 11549], [11569, 11587], [11607, 11625], [11693, 11711], [12003, 12035], [12051, 12104], [12120, 12173], [12189, 12242], [12258, 12290], [13798, 13832], [13848, 13898], [13914, 13965], [13981, 14032], [14048, 14082], [14323, 14368], [14402, 14461], [14549, 14594], [14628, 14687], [14775, 14821], [14855, 14915], [15003, 15063], [15097, 15170], [15208, 15253], [15445, 15492], [15526, 15583], [15671, 15719], [15753, 15812], [15900, 15949], [15983, 16043], [16131, 16180], [16214, 16274], [16312, 16359], [16530, 16559], [16579, 16608], [16628, 16657], [16677, 16706], [17126, 17154], [17159, 17186], [17191, 17218], [17223, 17265], [17270, 17302], [17307, 17339], [17344, 17371], [17376, 17403], [17408, 17435], [17440, 17467], [17472, 17499], [17554, 17571], [17611, 17631], [17642, 17672], [17683, 17703], [17714, 17739], [17750, 17774], [17819, 17846], [17859, 17886], [17899, 17945], [17958, 18029], [18067, 18142], [18213, 18231], [18607, 18634], [18645, 18672], [18683, 18710], [18721, 18759], [18854, 18872], [18931, 18954], [19127, 19154], [19220, 19255], [19313, 19339], [19406, 19447], [19523, 19576], [19653, 19687], [19842, 19880], [19893, 19920], [20037, 20075], [20084, 20107], [20161, 20188], [20258, 20291], [20302, 20329], [20340, 20367], [20585, 20608], [20778, 20805], [20881, 20904], [20990, 21016], [21074, 21100], [21147, 21164], [21216, 21233]], "nonblocking_assignment": [[12519, 12533], [12577, 12607], [12743, 12767], [12774, 12798], [12805, 12829], [12836, 12860], [12903, 12934], [12941, 12971], [12978, 13012], [13019, 13047], [13592, 13610], [13653, 13680], [21367, 21395], [21402, 21428], [21435, 21461], [21468, 21494], [21520, 21553], [21560, 21603], [21610, 21643], [21650, 21683]], "case_statement": [[9937, 11744], [10148, 10413], [10488, 10804], [10971, 11236], [11410, 11663], [11962, 12324], [13754, 14094], [14229, 15290], [15351, 16396], [16485, 16740], [17504, 21255]], "conditional_statement": [[10054, 10816], [10877, 11341], [12494, 12615], [12547, 12615], [12718, 13055], [12874, 13055], [13567, 13688], [13624, 13688], [14285, 14473], [14511, 14699], [14737, 14927], [14965, 15182], [15407, 15595], [15633, 15824], [15862, 16055], [16093, 16286], [17580, 18168], [17785, 18156], [18562, 18771], [19025, 19946], [19768, 19934], [20116, 20379], [20689, 21176], [21342, 21691]], "always_construct": [[9915, 11750], [11940, 12330], [12439, 12621], [12663, 13061], [13512, 13694], [13732, 14100], [14207, 15296], [15329, 16402], [16463, 16746], [17104, 21261], [21287, 21697]], "parameter_declaration": [], "ansi_port_declaration": [[6699, 6726], [6729, 6757], [6780, 6812], [6815, 6847], [6850, 6885], [6888, 6920], [6923, 6959], [6962, 6995], [6998, 7029], [7032, 7063], [7066, 7100], [7103, 7137], [7173, 7265], [7268, 7360], [7363, 7455], [7458, 7550], [7553, 7643], [7646, 7685], [7688, 7780], [7783, 7875], [7878, 7953], [8050, 8145], [8286, 8377], [8403, 8435], [8438, 8471], [8474, 8502], [8505, 8538], [8541, 8574]]}}
{"sample_i": "p9", "topmodule": "cve2_multdiv_fast", "code": "// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Package with constants used by CVE2\n */\npackage cve2_pkg;\n  ////////////////\n  // IO Structs //\n  ////////////////\n  typedef struct packed {\n    logic [31:0] current_pc;\n    logic [31:0] next_pc;\n    logic [31:0] last_data_addr;\n    logic [31:0] exception_addr;\n  } crash_dump_t;\n  typedef struct packed {\n    logic        dummy_instr_id;\n    logic [4:0]  raddr_a;\n    logic [4:0]  waddr_a;\n    logic        we_a;\n    logic [4:0]  raddr_b;\n  } core2rf_t;\n  /////////////////////\n  // Parameter Enums //\n  /////////////////////\n  typedef enum integer {\n    RV32MNone        = 0,\n    RV32MSlow        = 1,\n    RV32MFast        = 2,\n    RV32MSingleCycle = 3\n  } rv32m_e;\n  typedef enum integer {\n    RV32BNone       = 0,\n    RV32BBalanced   = 1,\n    RV32BOTEarlGrey = 2,\n    RV32BFull       = 3\n  } rv32b_e;\n  /////////////\n  // Opcodes //\n  /////////////\n  typedef enum logic [6:0] {\n    OPCODE_LOAD     = 7'h03,\n    OPCODE_MISC_MEM = 7'h0f,\n    OPCODE_OP_IMM   = 7'h13,\n    OPCODE_AUIPC    = 7'h17,\n    OPCODE_STORE    = 7'h23,\n    OPCODE_OP       = 7'h33,\n    OPCODE_LUI      = 7'h37,\n    OPCODE_BRANCH   = 7'h63,\n    OPCODE_JALR     = 7'h67,\n    OPCODE_JAL      = 7'h6f,\n    OPCODE_SYSTEM   = 7'h73\n  } opcode_e;\n  ////////////////////\n  // ALU operations //\n  ////////////////////\n  typedef enum logic [6:0] {\n    // Arithmetics\n    ALU_ADD,\n    ALU_SUB,\n    // Logics\n    ALU_XOR,\n    ALU_OR,\n    ALU_AND,\n    // RV32B\n    ALU_XNOR,\n    ALU_ORN,\n    ALU_ANDN,\n    // Shifts\n    ALU_SRA,\n    ALU_SRL,\n    ALU_SLL,\n    // RV32B\n    ALU_SRO,\n    ALU_SLO,\n    ALU_ROR,\n    ALU_ROL,\n    ALU_GREV,\n    ALU_GORC,\n    ALU_SHFL,\n    ALU_UNSHFL,\n    ALU_XPERM_N,\n    ALU_XPERM_B,\n    ALU_XPERM_H,\n    // Address Calculations\n    // RV32B\n    ALU_SH1ADD,\n    ALU_SH2ADD,\n    ALU_SH3ADD,\n    // Comparisons\n    ALU_LT,\n    ALU_LTU,\n    ALU_GE,\n    ALU_GEU,\n    ALU_EQ,\n    ALU_NE,\n    // RV32B\n    ALU_MIN,\n    ALU_MINU,\n    ALU_MAX,\n    ALU_MAXU,\n    // Pack\n    // RV32B\n    ALU_PACK,\n    ALU_PACKU,\n    ALU_PACKH,\n    // Sign-Extend\n    // RV32B\n    ALU_SEXTB,\n    ALU_SEXTH,\n    // Bitcounting\n    // RV32B\n    ALU_CLZ,\n    ALU_CTZ,\n    ALU_CPOP,\n    // Set lower than\n    ALU_SLT,\n    ALU_SLTU,\n    // Ternary Bitmanip Operations\n    // RV32B\n    ALU_CMOV,\n    ALU_CMIX,\n    ALU_FSL,\n    ALU_FSR,\n    // Single-Bit Operations\n    // RV32B\n    ALU_BSET,\n    ALU_BCLR,\n    ALU_BINV,\n    ALU_BEXT,\n    // Bit Compress / Decompress\n    // RV32B\n    ALU_BCOMPRESS,\n    ALU_BDECOMPRESS,\n    // Bit Field Place\n    // RV32B\n    ALU_BFP,\n    // Carry-less Multiply\n    // RV32B\n    ALU_CLMUL,\n    ALU_CLMULR,\n    ALU_CLMULH,\n    // Cyclic Redundancy Check\n    ALU_CRC32_B,\n    ALU_CRC32C_B,\n    ALU_CRC32_H,\n    ALU_CRC32C_H,\n    ALU_CRC32_W,\n    ALU_CRC32C_W\n  } alu_op_e;\n  typedef enum logic [1:0] {\n    // Multiplier/divider\n    MD_OP_MULL,\n    MD_OP_MULH,\n    MD_OP_DIV,\n    MD_OP_REM\n  } md_op_e;\n  //////////////////////////////////\n  // Control and status registers //\n  //////////////////////////////////\n  // CSR operations\n  typedef enum logic [1:0] {\n    CSR_OP_READ,\n    CSR_OP_WRITE,\n    CSR_OP_SET,\n    CSR_OP_CLEAR\n  } csr_op_e;\n  // Privileged mode\n  typedef enum logic[1:0] {\n    PRIV_LVL_M = 2'b11,\n    PRIV_LVL_H = 2'b10,\n    PRIV_LVL_S = 2'b01,\n    PRIV_LVL_U = 2'b00\n  } priv_lvl_e;\n  // Constants for the dcsr.xdebugver fields\n  typedef enum logic[3:0] {\n    XDEBUGVER_NO     = 4'd0, // no external debug support\n    XDEBUGVER_STD    = 4'd4, // external debug according to RISC-V debug spec\n    XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec\n  } x_debug_ver_e;\n  //////////////\n  // WB stage //\n  //////////////\n  // Type of instruction present in writeback stage\n  typedef enum logic[1:0] {\n    WB_INSTR_LOAD,  // Instruction is awaiting load data\n    WB_INSTR_STORE, // Instruction is awaiting store response\n    WB_INSTR_OTHER  // Instruction doesn't fit into above categories\n  } wb_instr_type_e;\n  //////////////\n  // ID stage //\n  //////////////\n  // Operand a selection\n  typedef enum logic[1:0] {\n    OP_A_REG_A,\n    OP_A_FWD,\n    OP_A_CURRPC,\n    OP_A_IMM\n  } op_a_sel_e;\n  // Immediate a selection\n  typedef enum logic {\n    IMM_A_Z,\n    IMM_A_ZERO\n  } imm_a_sel_e;\n  // Operand b selection\n  typedef enum logic {\n    OP_B_REG_B,\n    OP_B_IMM\n  } op_b_sel_e;\n  // Immediate b selection\n  typedef enum logic [2:0] {\n    IMM_B_I,\n    IMM_B_S,\n    IMM_B_B,\n    IMM_B_U,\n    IMM_B_J,\n    IMM_B_INCR_PC,\n    IMM_B_INCR_ADDR\n  } imm_b_sel_e;\n  // Regfile write data selection\n  typedef enum {\n    RF_WD_EX,\n    RF_WD_CSR,\n    RF_WD_COPROC // Only used when XInterface = 1\n  } rf_wd_sel_e;\n  //////////////\n  // IF stage //\n  //////////////\n  // PC mux selection\n  typedef enum logic [2:0] {\n    PC_BOOT,\n    PC_JUMP,\n    PC_EXC,\n    PC_ERET,\n    PC_DRET,\n    PC_BP\n  } pc_sel_e;\n  // Exception PC mux selection\n  typedef enum logic [1:0] {\n    EXC_PC_EXC,\n    EXC_PC_IRQ,\n    EXC_PC_DBD,\n    EXC_PC_DBG_EXC // Exception while in debug mode\n  } exc_pc_sel_e;\n  // Interrupt requests\n  typedef struct packed {\n    logic        irq_software;\n    logic        irq_timer;\n    logic        irq_external;\n    logic [15:0] irq_fast; // 16 fast interrupts\n  } irqs_t;\n  // Exception cause\n  typedef enum logic [6:0] {\n    EXC_CAUSE_IRQ_SOFTWARE_M     = {1'b1, 6'd03},\n    EXC_CAUSE_IRQ_TIMER_M        = {1'b1, 6'd07},\n    EXC_CAUSE_IRQ_EXTERNAL_M     = {1'b1, 6'd11},\n    // EXC_CAUSE_IRQ_FAST_0      = {1'b1, 6'd16},\n    // EXC_CAUSE_IRQ_FAST_15     = {1'b1, 6'd31},\n    EXC_CAUSE_IRQ_NM             = {1'b1, 6'd32},\n    EXC_CAUSE_INSN_ADDR_MISA     = {1'b0, 6'd00},\n    EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 6'd01},\n    EXC_CAUSE_ILLEGAL_INSN       = {1'b0, 6'd02},\n    EXC_CAUSE_BREAKPOINT         = {1'b0, 6'd03},\n    EXC_CAUSE_LOAD_ACCESS_FAULT  = {1'b0, 6'd05},\n    EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 6'd07},\n    EXC_CAUSE_ECALL_UMODE        = {1'b0, 6'd08},\n    EXC_CAUSE_ECALL_MMODE        = {1'b0, 6'd11}\n  } exc_cause_e;\n  // Debug cause\n  typedef enum logic [2:0] {\n    DBG_CAUSE_NONE    = 3'h0,\n    DBG_CAUSE_EBREAK  = 3'h1,\n    DBG_CAUSE_TRIGGER = 3'h2,\n    DBG_CAUSE_HALTREQ = 3'h3,\n    DBG_CAUSE_STEP    = 3'h4\n  } dbg_cause_e;\n  // PMP constants\n  parameter int unsigned PMP_MAX_REGIONS      = 16;\n  parameter int unsigned PMP_CFG_W            = 8;\n  // PMP acces type\n  parameter int unsigned PMP_I  = 0;\n  parameter int unsigned PMP_I2 = 1;\n  parameter int unsigned PMP_D  = 2;\n  typedef enum logic [1:0] {\n    PMP_ACC_EXEC    = 2'b00,\n    PMP_ACC_WRITE   = 2'b01,\n    PMP_ACC_READ    = 2'b10\n  } pmp_req_e;\n  // PMP cfg structures\n  typedef enum logic [1:0] {\n    PMP_MODE_OFF   = 2'b00,\n    PMP_MODE_TOR   = 2'b01,\n    PMP_MODE_NA4   = 2'b10,\n    PMP_MODE_NAPOT = 2'b11\n  } pmp_cfg_mode_e;\n  typedef struct packed {\n    logic          lock;\n    pmp_cfg_mode_e mode;\n    logic          exec;\n    logic          write;\n    logic          read;\n  } pmp_cfg_t;\n  // Machine Security Configuration (ePMP)\n  typedef struct packed {\n    logic rlb;  // Rule Locking Bypass\n    logic mmwp; // Machine Mode Whitelist Policy\n    logic mml;  // Machine Mode Lockdown\n  } pmp_mseccfg_t;\n  // CSRs\n  typedef enum logic[11:0] {\n    // Machine information\n    CSR_MVENDORID  = 12'hF11,\n    CSR_MARCHID    = 12'hF12,\n    CSR_MIMPID     = 12'hF13,\n    CSR_MHARTID    = 12'hF14,\n    CSR_MCONFIGPTR = 12'hF15,\n    // Machine trap setup\n    CSR_MSTATUS   = 12'h300,\n    CSR_MISA      = 12'h301,\n    CSR_MIE       = 12'h304,\n    CSR_MTVEC     = 12'h305,\n    CSR_MCOUNTEREN= 12'h306,\n    CSR_MSTATUSH  = 12'h310,\n    CSR_MENVCFG   = 12'h30A,\n    CSR_MENVCFGH  = 12'h31A,\n    // Machine trap handling\n    CSR_MSCRATCH  = 12'h340,\n    CSR_MEPC      = 12'h341,\n    CSR_MCAUSE    = 12'h342,\n    CSR_MTVAL     = 12'h343,\n    CSR_MIP       = 12'h344,\n    // Physical memory protection\n    CSR_PMPCFG0   = 12'h3A0,\n    CSR_PMPCFG1   = 12'h3A1,\n    CSR_PMPCFG2   = 12'h3A2,\n    CSR_PMPCFG3   = 12'h3A3,\n    CSR_PMPADDR0  = 12'h3B0,\n    CSR_PMPADDR1  = 12'h3B1,\n    CSR_PMPADDR2  = 12'h3B2,\n    CSR_PMPADDR3  = 12'h3B3,\n    CSR_PMPADDR4  = 12'h3B4,\n    CSR_PMPADDR5  = 12'h3B5,\n    CSR_PMPADDR6  = 12'h3B6,\n    CSR_PMPADDR7  = 12'h3B7,\n    CSR_PMPADDR8  = 12'h3B8,\n    CSR_PMPADDR9  = 12'h3B9,\n    CSR_PMPADDR10 = 12'h3BA,\n    CSR_PMPADDR11 = 12'h3BB,\n    CSR_PMPADDR12 = 12'h3BC,\n    CSR_PMPADDR13 = 12'h3BD,\n    CSR_PMPADDR14 = 12'h3BE,\n    CSR_PMPADDR15 = 12'h3BF,\n    // ePMP control\n    CSR_MSECCFG   = 12'h747,\n    CSR_MSECCFGH  = 12'h757,\n    // Debug trigger\n    CSR_TSELECT   = 12'h7A0,\n    CSR_TDATA1    = 12'h7A1,\n    CSR_TDATA2    = 12'h7A2,\n    CSR_TDATA3    = 12'h7A3,\n    CSR_MCONTEXT  = 12'h7A8,\n    CSR_SCONTEXT  = 12'h7AA,\n    // Debug/trace\n    CSR_DCSR      = 12'h7b0,\n    CSR_DPC       = 12'h7b1,\n    // Debug\n    CSR_DSCRATCH0 = 12'h7b2, // optional\n    CSR_DSCRATCH1 = 12'h7b3, // optional\n    // Machine Counter/Timers\n    CSR_MCOUNTINHIBIT  = 12'h320,\n    CSR_MHPMEVENT3     = 12'h323,\n    CSR_MHPMEVENT4     = 12'h324,\n    CSR_MHPMEVENT5     = 12'h325,\n    CSR_MHPMEVENT6     = 12'h326,\n    CSR_MHPMEVENT7     = 12'h327,\n    CSR_MHPMEVENT8     = 12'h328,\n    CSR_MHPMEVENT9     = 12'h329,\n    CSR_MHPMEVENT10    = 12'h32A,\n    CSR_MHPMEVENT11    = 12'h32B,\n    CSR_MHPMEVENT12    = 12'h32C,\n    CSR_MHPMEVENT13    = 12'h32D,\n    CSR_MHPMEVENT14    = 12'h32E,\n    CSR_MHPMEVENT15    = 12'h32F,\n    CSR_MHPMEVENT16    = 12'h330,\n    CSR_MHPMEVENT17    = 12'h331,\n    CSR_MHPMEVENT18    = 12'h332,\n    CSR_MHPMEVENT19    = 12'h333,\n    CSR_MHPMEVENT20    = 12'h334,\n    CSR_MHPMEVENT21    = 12'h335,\n    CSR_MHPMEVENT22    = 12'h336,\n    CSR_MHPMEVENT23    = 12'h337,\n    CSR_MHPMEVENT24    = 12'h338,\n    CSR_MHPMEVENT25    = 12'h339,\n    CSR_MHPMEVENT26    = 12'h33A,\n    CSR_MHPMEVENT27    = 12'h33B,\n    CSR_MHPMEVENT28    = 12'h33C,\n    CSR_MHPMEVENT29    = 12'h33D,\n    CSR_MHPMEVENT30    = 12'h33E,\n    CSR_MHPMEVENT31    = 12'h33F,\n    CSR_MCYCLE         = 12'hB00,\n    CSR_MINSTRET       = 12'hB02,\n    CSR_MHPMCOUNTER3   = 12'hB03,\n    CSR_MHPMCOUNTER4   = 12'hB04,\n    CSR_MHPMCOUNTER5   = 12'hB05,\n    CSR_MHPMCOUNTER6   = 12'hB06,\n    CSR_MHPMCOUNTER7   = 12'hB07,\n    CSR_MHPMCOUNTER8   = 12'hB08,\n    CSR_MHPMCOUNTER9   = 12'hB09,\n    CSR_MHPMCOUNTER10  = 12'hB0A,\n    CSR_MHPMCOUNTER11  = 12'hB0B,\n    CSR_MHPMCOUNTER12  = 12'hB0C,\n    CSR_MHPMCOUNTER13  = 12'hB0D,\n    CSR_MHPMCOUNTER14  = 12'hB0E,\n    CSR_MHPMCOUNTER15  = 12'hB0F,\n    CSR_MHPMCOUNTER16  = 12'hB10,\n    CSR_MHPMCOUNTER17  = 12'hB11,\n    CSR_MHPMCOUNTER18  = 12'hB12,\n    CSR_MHPMCOUNTER19  = 12'hB13,\n    CSR_MHPMCOUNTER20  = 12'hB14,\n    CSR_MHPMCOUNTER21  = 12'hB15,\n    CSR_MHPMCOUNTER22  = 12'hB16,\n    CSR_MHPMCOUNTER23  = 12'hB17,\n    CSR_MHPMCOUNTER24  = 12'hB18,\n    CSR_MHPMCOUNTER25  = 12'hB19,\n    CSR_MHPMCOUNTER26  = 12'hB1A,\n    CSR_MHPMCOUNTER27  = 12'hB1B,\n    CSR_MHPMCOUNTER28  = 12'hB1C,\n    CSR_MHPMCOUNTER29  = 12'hB1D,\n    CSR_MHPMCOUNTER30  = 12'hB1E,\n    CSR_MHPMCOUNTER31  = 12'hB1F,\n    CSR_MCYCLEH        = 12'hB80,\n    CSR_MINSTRETH      = 12'hB82,\n    CSR_MHPMCOUNTER3H  = 12'hB83,\n    CSR_MHPMCOUNTER4H  = 12'hB84,\n    CSR_MHPMCOUNTER5H  = 12'hB85,\n    CSR_MHPMCOUNTER6H  = 12'hB86,\n    CSR_MHPMCOUNTER7H  = 12'hB87,\n    CSR_MHPMCOUNTER8H  = 12'hB88,\n    CSR_MHPMCOUNTER9H  = 12'hB89,\n    CSR_MHPMCOUNTER10H = 12'hB8A,\n    CSR_MHPMCOUNTER11H = 12'hB8B,\n    CSR_MHPMCOUNTER12H = 12'hB8C,\n    CSR_MHPMCOUNTER13H = 12'hB8D,\n    CSR_MHPMCOUNTER14H = 12'hB8E,\n    CSR_MHPMCOUNTER15H = 12'hB8F,\n    CSR_MHPMCOUNTER16H = 12'hB90,\n    CSR_MHPMCOUNTER17H = 12'hB91,\n    CSR_MHPMCOUNTER18H = 12'hB92,\n    CSR_MHPMCOUNTER19H = 12'hB93,\n    CSR_MHPMCOUNTER20H = 12'hB94,\n    CSR_MHPMCOUNTER21H = 12'hB95,\n    CSR_MHPMCOUNTER22H = 12'hB96,\n    CSR_MHPMCOUNTER23H = 12'hB97,\n    CSR_MHPMCOUNTER24H = 12'hB98,\n    CSR_MHPMCOUNTER25H = 12'hB99,\n    CSR_MHPMCOUNTER26H = 12'hB9A,\n    CSR_MHPMCOUNTER27H = 12'hB9B,\n    CSR_MHPMCOUNTER28H = 12'hB9C,\n    CSR_MHPMCOUNTER29H = 12'hB9D,\n    CSR_MHPMCOUNTER30H = 12'hB9E,\n    CSR_MHPMCOUNTER31H = 12'hB9F,\n    CSR_CPUCTRL        = 12'h7C0,\n    CSR_SECURESEED     = 12'h7C1\n  } csr_num_e;\n  // CSR pmp-related offsets\n  parameter logic [11:0] CSR_OFF_PMP_CFG  = 12'h3A0; // pmp_cfg  @ 12'h3a0 - 12'h3a3\n  parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf\n  // CSR status bits\n  parameter int unsigned CSR_MSTATUS_MIE_BIT      = 3;\n  parameter int unsigned CSR_MSTATUS_MPIE_BIT     = 7;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW  = 11;\n  parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;\n  parameter int unsigned CSR_MSTATUS_MPRV_BIT     = 17;\n  parameter int unsigned CSR_MSTATUS_TW_BIT       = 21;\n  // CSR machine ISA\n  parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32\n  // CSR interrupt pending/enable bits\n  parameter int unsigned CSR_MSIX_BIT      = 3;\n  parameter int unsigned CSR_MTIX_BIT      = 7;\n  parameter int unsigned CSR_MEIX_BIT      = 11;\n  parameter int unsigned CSR_MFIX_BIT_LOW  = 16;\n  parameter int unsigned CSR_MFIX_BIT_HIGH = 31;\n  // CSR Machine Security Configuration bits\n  parameter int unsigned CSR_MSECCFG_MML_BIT  = 0;\n  parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1;\n  parameter int unsigned CSR_MSECCFG_RLB_BIT  = 2;\n  // Machine Vendor ID - OpenHW JEDEC ID is '2 decimal (bank 13)'\n  parameter MVENDORID_OFFSET = 7'h2;  // Final byte without parity bit\n  parameter MVENDORID_BANK = 25'hC;  // Number of continuation codes\n  // Machine Architecture ID (https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md)\n  parameter MARCHID = 32'd35;\n  localparam logic [31:0] CSR_MVENDORID_VALUE  = {MVENDORID_BANK, MVENDORID_OFFSET};\n  localparam logic [31:0] CSR_MARCHID_VALUE = MARCHID;\n  // Implementation ID\n  // 0 indicates this field is not implemeted. cve2 implementors may wish to indicate an RTL/netlist\n  // version here using their own unique encoding (e.g. 32 bits of the git hash of the implemented\n  // commit).\n  localparam logic [31:0] CSR_MIMPID_VALUE = 32'b0;\n  // Machine Configuration Pointer\n  // 0 indicates the configuration data structure does not eixst. cve2 implementors may wish to\n  // alter this to point to their system specific configuration data structure.\n  localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;\n // RVFI CSR element\n  typedef struct packed {\n    bit [63:0] rdata;\n    bit [63:0] rmask;\n    bit [63:0] wdata;\n    bit [63:0] wmask;\n  } rvfi_csr_elmt_t;\n  // RVFI CSR structure\n  typedef struct packed {\n    rvfi_csr_elmt_t fflags;\n    rvfi_csr_elmt_t frm;\n    rvfi_csr_elmt_t fcsr;\n    rvfi_csr_elmt_t ftran;\n    rvfi_csr_elmt_t dcsr;\n    rvfi_csr_elmt_t dpc;\n    rvfi_csr_elmt_t dscratch0;\n    rvfi_csr_elmt_t dscratch1;\n    rvfi_csr_elmt_t sstatus;\n    rvfi_csr_elmt_t sie;\n    rvfi_csr_elmt_t sip;\n    rvfi_csr_elmt_t stvec;\n    rvfi_csr_elmt_t scounteren;\n    rvfi_csr_elmt_t sscratch;\n    rvfi_csr_elmt_t sepc;\n    rvfi_csr_elmt_t scause;\n    rvfi_csr_elmt_t stval;\n    rvfi_csr_elmt_t satp;\n    rvfi_csr_elmt_t mstatus;\n    rvfi_csr_elmt_t mstatush;\n    rvfi_csr_elmt_t misa;\n    rvfi_csr_elmt_t medeleg;\n    rvfi_csr_elmt_t mideleg;\n    rvfi_csr_elmt_t mie;\n    rvfi_csr_elmt_t mtvec;\n    rvfi_csr_elmt_t mcounteren;\n    rvfi_csr_elmt_t mscratch;\n    rvfi_csr_elmt_t mepc;\n    rvfi_csr_elmt_t mcause;\n    rvfi_csr_elmt_t mtval;\n    rvfi_csr_elmt_t mip;\n    rvfi_csr_elmt_t menvcfg;\n    rvfi_csr_elmt_t menvcfgh;\n    rvfi_csr_elmt_t mvendorid;\n    rvfi_csr_elmt_t marchid;\n    rvfi_csr_elmt_t mhartid;\n    rvfi_csr_elmt_t mcountinhibit;\n    rvfi_csr_elmt_t mcycle;\n    rvfi_csr_elmt_t mcycleh;\n    rvfi_csr_elmt_t minstret;\n    rvfi_csr_elmt_t minstreth;\n    rvfi_csr_elmt_t cycle;\n    rvfi_csr_elmt_t cycleh;\n    rvfi_csr_elmt_t instret;\n    rvfi_csr_elmt_t instreth;\n    rvfi_csr_elmt_t dcache;\n    rvfi_csr_elmt_t icache;\n    rvfi_csr_elmt_t acc_cons;\n    rvfi_csr_elmt_t pmpcfg0;\n    rvfi_csr_elmt_t pmpcfg1;\n    rvfi_csr_elmt_t pmpcfg2;\n    rvfi_csr_elmt_t pmpcfg3;\n    rvfi_csr_elmt_t pmpaddr0;\n    rvfi_csr_elmt_t pmpaddr1;\n    rvfi_csr_elmt_t pmpaddr2;\n    rvfi_csr_elmt_t pmpaddr3;\n    rvfi_csr_elmt_t pmpaddr4;\n    rvfi_csr_elmt_t pmpaddr5;\n    rvfi_csr_elmt_t pmpaddr6;\n    rvfi_csr_elmt_t pmpaddr7;\n    rvfi_csr_elmt_t pmpaddr8;\n    rvfi_csr_elmt_t pmpaddr9;\n    rvfi_csr_elmt_t pmpaddr10;\n    rvfi_csr_elmt_t pmpaddr11;\n    rvfi_csr_elmt_t pmpaddr12;\n    rvfi_csr_elmt_t pmpaddr13;\n    rvfi_csr_elmt_t pmpaddr14;\n    rvfi_csr_elmt_t pmpaddr15;\n  } rvfi_csr_t;\n  // CV-X-IF\n  parameter int unsigned X_NUM_RS         = 3;\n  parameter int unsigned X_ID_WIDTH       = 4;\n  parameter int unsigned X_RFR_WIDTH      = 32;\n  parameter int unsigned X_RFW_WIDTH      = 32;\n  parameter int unsigned X_HARTID_WIDTH   = 32;\n  parameter int unsigned X_DUAL_READ      = 0;\n  parameter int unsigned X_DUAL_WRITE     = 0;\n  parameter int unsigned X_INSTR_INFLIGHT = 2**X_ID_WIDTH;\n  typedef logic [X_NUM_RS+X_DUAL_READ-1:0] readregflags_t;\n  typedef logic [X_DUAL_WRITE:0]           writeregflags_t;\n  typedef logic [X_ID_WIDTH-1:0]           id_t;\n  typedef logic [X_HARTID_WIDTH-1:0]       hartid_t;\n  // Issue Interface\n  typedef struct packed {\n    logic [31:0] instr;\n    hartid_t     hartid;\n    id_t         id;\n  } x_issue_req_t;\n  typedef struct packed {\n    logic           accept;\n    writeregflags_t writeback;\n    readregflags_t  register_read;\n  } x_issue_resp_t;\n  // Register Interface\n  typedef struct packed {\n    hartid_t                              hartid;\n    id_t                                  id;\n    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;\n    readregflags_t                        rs_valid;\n  } x_register_t;\n  // Commit Interface\n  typedef struct packed {\n    hartid_t hartid;\n    id_t     id;\n    logic    commit_kill;\n  } x_commit_t;\n  // Result Interface\n  typedef struct packed {\n    hartid_t                hartid;\n    id_t                    id;\n    logic [X_RFW_WIDTH-1:0] data;\n    logic [4:0]             rd;\n    writeregflags_t         we;\n  } x_result_t;\nendpackage\n// Copyright (c) 2025 Eclipse Foundation\n// Copyright lowRISC contributors.\n// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n/**\n * Fast Multiplier and Division\n *\n * 16x16 kernel multiplier and Long Division\n */\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macros and helper code for using assertions.\n//  - Provides default clk and rst options to simplify code\n//  - Provides boiler plate template for common assertions\n///////////////////\n// Helper macros //\n///////////////////\n// Default clk and reset signals used by assertion macros below.\n// Converts an arbitrary block of code into a Verilog string\n// ASSERT_ERROR logs an error message with either `uvm_error or with $error.\n//\n// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason\n// for redefining it here is to avoid creating a dependency.\n// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes\n// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want\n// to allow this for tapeout.\n// The basic helper macros are actually defined in \"implementation headers\". The macros should do\n// the same thing in each case (except for the dummy flavour), but in a way that the respective\n// tools support.\n//\n// If the tool supports assertions in some form, we also define INC_ASSERT (which can be used to\n// hide signal definitions that are only used for assertions).\n//\n// The list of basic macros supported is:\n//\n//  ASSERT_I:     Immediate assertion. Note that immediate assertions are sensitive to simulation\n//                glitches.\n//\n//  ASSERT_INIT:  Assertion in initial block. Can be used for things like parameter checking.\n//\n//  ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net.\n//\n//  ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of\n//                sim, all credits returned at end of sim, state machines in idle at end of sim.\n//\n//  ASSERT:       Assert a concurrent property directly. It can be called as a module (or\n//                interface) body item.\n//\n//                Note: We use (__rst !== '0) in the disable iff statements instead of (__rst ==\n//                '1). This properly disables the assertion in cases when reset is X at the\n//                beginning of a simulation. For that case, (reset == '1) does not disable the\n//                assertion.\n//\n//  ASSERT_NEVER: Assert a concurrent property NEVER happens\n//\n//  ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset.\n//                It can be called as a module (or interface) body item.\n//\n//  COVER:        Cover a concurrent property\n//\n//  ASSUME:       Assume a concurrent property\n//\n//  ASSUME_I:     Assume an immediate property\n  // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// Macro bodies included by prim_assert.sv for tools that don't support assertions. See\n// prim_assert.sv for documentation for each of the macros.\n//////////////////////////////\n// Complex assertion macros //\n//////////////////////////////\n// Assert that signal is an active-high pulse with pulse length of 1 clock cycle\n// Assert that a property is true only when an enable signal is set.  It can be called as a module\n// (or interface) body item.\n// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is\n// set.  It can be called as a module (or interface) body item.\n//////////////////////////////////\n// For formal verification only //\n//////////////////////////////////\n// Note that the existing set of ASSERT macros specified above shall be used for FPV,\n// thereby ensuring that the assertions are evaluated during DV simulations as well.\n// ASSUME_FPV\n// Assume a concurrent property during formal verification only.\n// ASSUME_I_FPV\n// Assume a concurrent property during formal verification only.\n// COVER_FPV\n// Cover a concurrent property during formal verification\n // Copyright lowRISC contributors.\n// Licensed under the Apache License, Version 2.0, see LICENSE for details.\n// SPDX-License-Identifier: Apache-2.0\n// // Macros and helper code for security countermeasures.\n// Helper macros\n// macros for security countermeasures\n // PRIM_ASSERT_SEC_CM_SVH\n // PRIM_ASSERT_SV\nmodule cve2_multdiv_fast #(\n  parameter cve2_pkg::rv32m_e RV32M = cve2_pkg::RV32MFast\n  ) (\n  input  logic             clk_i,\n  input  logic             rst_ni,\n  input  logic             mult_en_i,  // dynamic enable signal, for FSM control\n  input  logic             div_en_i,   // dynamic enable signal, for FSM control\n  input  logic             mult_sel_i, // static decoder output, for data muxes\n  input  logic             div_sel_i,  // static decoder output, for data muxes\n  input  cve2_pkg::md_op_e operator_i,\n  input  logic  [1:0]      signed_mode_i,\n  input  logic [31:0]      op_a_i,\n  input  logic [31:0]      op_b_i,\n  input  logic [33:0]      alu_adder_ext_i,\n  input  logic [31:0]      alu_adder_i,\n  input  logic             equal_to_zero_i,\n  output logic [32:0]      alu_operand_a_o,\n  output logic [32:0]      alu_operand_b_o,\n  input  logic [33:0]      imd_val_q_i[2],\n  output logic [33:0]      imd_val_d_o[2],\n  output logic [1:0]       imd_val_we_o,\n  output logic [31:0]      multdiv_result_o,\n  output logic             valid_o\n);\n  import cve2_pkg::*;\n  // Both multiplier variants\n  logic signed [34:0] mac_res_signed;\n  logic        [34:0] mac_res_ext;\n  logic        [33:0] accum;\n  logic        sign_a, sign_b;\n  logic        mult_valid;\n  logic        signed_mult;\n  // Results that become intermediate value depending on whether mul or div is being calculated\n  logic [33:0] mac_res_d, op_remainder_d;\n  // Raw output of MAC calculation\n  logic [33:0] mac_res;\n  // Divider signals\n  logic        div_sign_a, div_sign_b;\n  logic        is_greater_equal;\n  logic        div_change_sign, rem_change_sign;\n  logic [31:0] one_shift;\n  logic [31:0] op_denominator_q;\n  logic [31:0] op_numerator_q;\n  logic [31:0] op_quotient_q;\n  logic [31:0] op_denominator_d;\n  logic [31:0] op_numerator_d;\n  logic [31:0] op_quotient_d;\n  logic [31:0] next_remainder;\n  logic [32:0] next_quotient;\n  logic [31:0] res_adder_h;\n  logic        div_valid;\n  logic [ 4:0] div_counter_q, div_counter_d;\n  logic        multdiv_en;\n  logic        mult_hold;\n  logic        div_hold;\n  logic        div_by_zero_d, div_by_zero_q;\n  logic        mult_en_internal;\n  logic        div_en_internal;\n  typedef enum logic [2:0] {\n    MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH\n  } md_fsm_e;\n  md_fsm_e md_state_q, md_state_d;\n  logic unused_mult_sel_i;\n  assign unused_mult_sel_i = mult_sel_i;\n  assign mult_en_internal = mult_en_i & ~mult_hold;\n  assign div_en_internal  = div_en_i & ~div_hold;\n  always_ff @(posedge clk_i or negedge rst_ni) begin\n    if (!rst_ni) begin\n      div_counter_q    <= '0;\n      md_state_q       <= MD_IDLE;\n      op_numerator_q   <= '0;\n      op_quotient_q    <= '0;\n      div_by_zero_q    <= '0;\n    end else if (div_en_internal) begin\n      div_counter_q    <= div_counter_d;\n      op_numerator_q   <= op_numerator_d;\n      op_quotient_q    <= op_quotient_d;\n      md_state_q       <= md_state_d;\n      div_by_zero_q    <= div_by_zero_d;\n    end\n  end\n  assign multdiv_en = mult_en_internal | div_en_internal;\n  // Intermediate value register shared with ALU\n  assign imd_val_d_o[0] = div_sel_i ? op_remainder_d : mac_res_d;\n  assign imd_val_we_o[0] = multdiv_en;\n  assign imd_val_d_o[1] = {2'b0, op_denominator_d};\n  assign imd_val_we_o[1] = div_en_internal;\n  assign op_denominator_q = imd_val_q_i[1][31:0];\n  logic [1:0] unused_imd_val;\n  assign unused_imd_val = imd_val_q_i[1][33:32];\n  logic unused_mac_res_ext;\n  assign unused_mac_res_ext = mac_res_ext[34];\n  assign signed_mult      = (signed_mode_i != 2'b00);\n  assign multdiv_result_o = div_sel_i ? imd_val_q_i[0][31:0] : mac_res_d[31:0];\n  // The single cycle multiplier uses three 17 bit multipliers to compute MUL instructions in a\n  // single cycle and MULH instructions in two cycles.\n  if (RV32M == RV32MSingleCycle) begin : gen_mult_single_cycle\n    typedef enum logic {\n      MULL, MULH\n    } mult_fsm_e;\n    mult_fsm_e mult_state_q, mult_state_d;\n    logic signed [33:0] mult1_res, mult2_res, mult3_res;\n    logic [33:0]        mult1_res_uns;\n    logic [33:32]       unused_mult1_res_uns;\n    logic [15:0]        mult1_op_a, mult1_op_b;\n    logic [15:0]        mult2_op_a, mult2_op_b;\n    logic [15:0]        mult3_op_a, mult3_op_b;\n    logic               mult1_sign_a, mult1_sign_b;\n    logic               mult2_sign_a, mult2_sign_b;\n    logic               mult3_sign_a, mult3_sign_b;\n    logic [33:0]        summand1, summand2, summand3;\n    assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b});\n    assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b});\n    assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b});\n    assign mac_res_signed = $signed(summand1) + $signed(summand2) + $signed(summand3);\n    assign mult1_res_uns  = $unsigned(mult1_res);\n    assign mac_res_ext    = $unsigned(mac_res_signed);\n    assign mac_res        = mac_res_ext[33:0];\n    assign sign_a = signed_mode_i[0] & op_a_i[31];\n    assign sign_b = signed_mode_i[1] & op_b_i[31];\n    // The first two multipliers are only used in state 1 (MULL). We can assign them statically.\n    // al*bl\n    assign mult1_sign_a = 1'b0;\n    assign mult1_sign_b = 1'b0;\n    assign mult1_op_a = op_a_i[15:0];\n    assign mult1_op_b = op_b_i[15:0];\n    // al*bh\n    assign mult2_sign_a = 1'b0;\n    assign mult2_sign_b = sign_b;\n    assign mult2_op_a = op_a_i[15:0];\n    assign mult2_op_b = op_b_i[31:16];\n    // used in MULH\n    assign accum[17:0] = imd_val_q_i[0][33:16];\n    assign accum[33:18] = {16{signed_mult & imd_val_q_i[0][33]}};\n    always_comb begin\n      // Default values == MULL\n      // ah*bl\n      mult3_sign_a = sign_a;\n      mult3_sign_b = 1'b0;\n      mult3_op_a = op_a_i[31:16];\n      mult3_op_b = op_b_i[15:0];\n      summand1 = {18'h0, mult1_res_uns[31:16]};\n      summand2 = $unsigned(mult2_res);\n      summand3 = $unsigned(mult3_res);\n      // mac_res = A*B[47:16], mult1_res = A*B[15:0]\n      mac_res_d = {2'b0, mac_res[15:0], mult1_res_uns[15:0]};\n      mult_valid = mult_en_i;\n      mult_state_d = MULL;\n      mult_hold = 1'b0;\n      unique case (mult_state_q)\n        MULL: begin\n          if (operator_i != MD_OP_MULL) begin\n            mac_res_d = mac_res;\n            mult_valid = 1'b0;\n            mult_state_d = MULH;\n          end else begin\n            mult_hold = 1'b0;\n          end\n        end\n        MULH: begin\n          // ah*bh\n          mult3_sign_a = sign_a;\n          mult3_sign_b = sign_b;\n          mult3_op_a = op_a_i[31:16];\n          mult3_op_b = op_b_i[31:16];\n          mac_res_d = mac_res;\n          summand1 = '0;\n          summand2 = accum;\n          summand3 = $unsigned(mult3_res);\n          mult_state_d = MULL;\n          mult_valid = 1'b1;\n          mult_hold = 1'b0;\n        end\n        default: begin\n          mult_state_d = MULL;\n        end\n      endcase // mult_state_q\n    end\n    always_ff @(posedge clk_i or negedge rst_ni) begin\n      if (!rst_ni) begin\n        mult_state_q <= MULL;\n      end else begin\n        if (mult_en_internal) begin\n          mult_state_q <= mult_state_d;\n        end\n      end\n    end\n    assign unused_mult1_res_uns = mult1_res_uns[33:32];\n    // States must be knwon/valid.\n  // The fast multiplier uses one 17 bit multiplier to compute MUL instructions in 3 cycles\n  // and MULH instructions in 4 cycles.\n  end else begin : gen_mult_fast\n    logic [15:0] mult_op_a;\n    logic [15:0] mult_op_b;\n    typedef enum logic [1:0] {\n      ALBL, ALBH, AHBL, AHBH\n    } mult_fsm_e;\n    mult_fsm_e mult_state_q, mult_state_d;\n    // The 2 MSBs of mac_res_ext (mac_res_ext[34:33]) are always equal since:\n    // 1. The 2 MSBs of the multiplicants are always equal, and\n    // 2. The 16 MSBs of the addend (accum[33:18]) are always equal.\n    // Thus, it is safe to ignore mac_res_ext[34].\n    assign mac_res_signed =\n        $signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b}) + $signed(accum);\n    assign mac_res_ext    = $unsigned(mac_res_signed);\n    assign mac_res        = mac_res_ext[33:0];\n    always_comb begin\n      mult_op_a    = op_a_i[15:0];\n      mult_op_b    = op_b_i[15:0];\n      sign_a       = 1'b0;\n      sign_b       = 1'b0;\n      accum        = imd_val_q_i[0];\n      mac_res_d    = mac_res;\n      mult_state_d = mult_state_q;\n      mult_valid   = 1'b0;\n      mult_hold    = 1'b0;\n      unique case (mult_state_q)\n        ALBL: begin\n          // al*bl\n          mult_op_a = op_a_i[15:0];\n          mult_op_b = op_b_i[15:0];\n          sign_a    = 1'b0;\n          sign_b    = 1'b0;\n          accum     = '0;\n          mac_res_d = mac_res;\n          mult_state_d = ALBH;\n        end\n        ALBH: begin\n          // al*bh<<16\n          mult_op_a = op_a_i[15:0];\n          mult_op_b = op_b_i[31:16];\n          sign_a    = 1'b0;\n          sign_b    = signed_mode_i[1] & op_b_i[31];\n          // result of AL*BL (in imd_val_q_i[0]) always unsigned with no carry\n          accum     = {18'b0, imd_val_q_i[0][31:16]};\n          if (operator_i == MD_OP_MULL) begin\n            mac_res_d = {2'b0, mac_res[15:0], imd_val_q_i[0][15:0]};\n          end else begin\n            // MD_OP_MULH\n            mac_res_d = mac_res;\n          end\n          mult_state_d = AHBL;\n        end\n        AHBL: begin\n          // ah*bl<<16\n          mult_op_a = op_a_i[31:16];\n          mult_op_b = op_b_i[15:0];\n          sign_a    = signed_mode_i[0] & op_a_i[31];\n          sign_b    = 1'b0;\n          if (operator_i == MD_OP_MULL) begin\n            accum        = {18'b0, imd_val_q_i[0][31:16]};\n            mac_res_d    = {2'b0, mac_res[15:0], imd_val_q_i[0][15:0]};\n            mult_valid   = 1'b1;\n            // Note no state transition will occur if mult_hold is set\n            mult_state_d = ALBL;\n            mult_hold    = 1'b0;\n          end else begin\n            accum        = imd_val_q_i[0];\n            mac_res_d    = mac_res;\n            mult_state_d = AHBH;\n          end\n        end\n        AHBH: begin\n          // only MD_OP_MULH here\n          // ah*bh\n          mult_op_a = op_a_i[31:16];\n          mult_op_b = op_b_i[31:16];\n          sign_a    = signed_mode_i[0] & op_a_i[31];\n          sign_b    = signed_mode_i[1] & op_b_i[31];\n          accum[17: 0]  = imd_val_q_i[0][33:16];\n          accum[33:18]  = {16{signed_mult & imd_val_q_i[0][33]}};\n          // result of AH*BL is not signed only if signed_mode_i == 2'b00\n          mac_res_d    = mac_res;\n          mult_valid   = 1'b1;\n          // Note no state transition will occur if mult_hold is set\n          mult_state_d = ALBL;\n          mult_hold    = 1'b0;\n        end\n        default: begin\n          mult_state_d = ALBL;\n        end\n      endcase // mult_state_q\n    end\n    always_ff @(posedge clk_i or negedge rst_ni) begin\n      if (!rst_ni) begin\n        mult_state_q <= ALBL;\n      end else begin\n        if (mult_en_internal) begin\n          mult_state_q <= mult_state_d;\n        end\n      end\n    end\n    // States must be knwon/valid.\n  end // gen_mult_fast\n  // Divider\n  assign res_adder_h    = alu_adder_ext_i[32:1];\n  logic [1:0] unused_alu_adder_ext;\n  assign unused_alu_adder_ext = {alu_adder_ext_i[33],alu_adder_ext_i[0]};\n  assign next_remainder = is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[0][31:0];\n  assign next_quotient  = is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} :\n                                             {1'b0, op_quotient_q};\n  assign one_shift      = {31'b0, 1'b1} << div_counter_q;\n  // The adder in the ALU computes alu_operand_a_o + alu_operand_b_o which means\n  // Remainder - Divisor. If Remainder - Divisor >= 0, is_greater_equal is equal to 1,\n  // the next Remainder is Remainder - Divisor contained in res_adder_h and the\n  always_comb begin\n    if ((imd_val_q_i[0][31] ^ op_denominator_q[31]) == 1'b0) begin\n      is_greater_equal = (res_adder_h[31] == 1'b0);\n    end else begin\n      is_greater_equal = imd_val_q_i[0][31];\n    end\n  end\n  assign div_sign_a      = op_a_i[31] & signed_mode_i[0];\n  assign div_sign_b      = op_b_i[31] & signed_mode_i[1];\n  assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q;\n  assign rem_change_sign = div_sign_a;\n  always_comb begin\n    div_counter_d    = div_counter_q - 5'h1;\n    op_remainder_d   = imd_val_q_i[0];\n    op_quotient_d    = op_quotient_q;\n    md_state_d       = md_state_q;\n    op_numerator_d   = op_numerator_q;\n    op_denominator_d = op_denominator_q;\n    alu_operand_a_o  = {32'h0  , 1'b1};\n    alu_operand_b_o  = {~op_b_i, 1'b1};\n    div_valid        = 1'b0;\n    div_hold         = 1'b0;\n    div_by_zero_d    = div_by_zero_q;\n    unique case (md_state_q)\n      MD_IDLE: begin\n        if (operator_i == MD_OP_DIV) begin\n          // Check if the Denominator is 0\n          // quotient for division by 0 is specified to be -1\n          // Note with data-independent time option, the full divide operation will proceed as\n          // normal and will naturally return -1\n          op_remainder_d = '1;\n          // SEC_CM: CORE.DATA_REG_SW.SCA\n          md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;\n          // Record that this is a div by zero to stop the sign change at the end of the\n          // division (in data_ind_timing mode).\n          div_by_zero_d  = equal_to_zero_i;\n        end else begin\n          // Check if the Denominator is 0\n          // remainder for division by 0 is specified to be the numerator (operand a)\n          // Note with data-independent time option, the full divide operation will proceed as\n          // normal and will naturally return operand a\n          op_remainder_d = {2'b0, op_a_i};\n          // SEC_CM: CORE.DATA_REG_SW.SCA\n          md_state_d     = equal_to_zero_i ? MD_FINISH : MD_ABS_A;\n        end\n        // 0 - B = 0 iff B == 0\n        alu_operand_a_o  = {32'h0  , 1'b1};\n        alu_operand_b_o  = {~op_b_i, 1'b1};\n        div_counter_d    = 5'd31;\n      end\n      MD_ABS_A: begin\n        // quotient\n        op_quotient_d   = '0;\n        // A abs value\n        op_numerator_d  = div_sign_a ? alu_adder_i : op_a_i;\n        md_state_d      = MD_ABS_B;\n        div_counter_d   = 5'd31;\n        // ABS(A) = 0 - A\n        alu_operand_a_o = {32'h0  , 1'b1};\n        alu_operand_b_o = {~op_a_i, 1'b1};\n      end\n      MD_ABS_B: begin\n        // remainder\n        op_remainder_d   = { 33'h0, op_numerator_q[31]};\n        // B abs value\n        op_denominator_d = div_sign_b ? alu_adder_i : op_b_i;\n        md_state_d       = MD_COMP;\n        div_counter_d    = 5'd31;\n        // ABS(B) = 0 - B\n        alu_operand_a_o  = {32'h0  , 1'b1};\n        alu_operand_b_o  = {~op_b_i, 1'b1};\n      end\n      MD_COMP: begin\n        op_remainder_d  = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]};\n        op_quotient_d   = next_quotient[31:0];\n        md_state_d      = (div_counter_q == 5'd1) ? MD_LAST : MD_COMP;\n        // Division\n        alu_operand_a_o = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder\n        alu_operand_b_o = {~op_denominator_q[31:0], 1'b1};  // -denominator two's compliment\n      end\n      MD_LAST: begin\n        if (operator_i == MD_OP_DIV) begin\n          // this time we save the quotient in op_remainder_d (i.e. imd_val_q_i[0]) since\n          // we do not need anymore the remainder\n          op_remainder_d = {1'b0, next_quotient};\n        end else begin\n          // this time we do not save the quotient anymore since we need only the remainder\n          op_remainder_d = {2'b0, next_remainder[31:0]};\n        end\n        // Division\n        alu_operand_a_o  = {imd_val_q_i[0][31:0], 1'b1}; // it contains the remainder\n        alu_operand_b_o  = {~op_denominator_q[31:0], 1'b1};  // -denominator two's compliment\n        md_state_d = MD_CHANGE_SIGN;\n      end\n      MD_CHANGE_SIGN: begin\n        md_state_d  = MD_FINISH;\n        if (operator_i == MD_OP_DIV) begin\n          op_remainder_d = (div_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0];\n        end else begin\n          op_remainder_d = (rem_change_sign) ? {2'h0, alu_adder_i} : imd_val_q_i[0];\n        end\n        // ABS(Quotient) = 0 - Quotient (or Remainder)\n        alu_operand_a_o  = {32'h0  , 1'b1};\n        alu_operand_b_o  = {~imd_val_q_i[0][31:0], 1'b1};\n      end\n      MD_FINISH: begin\n        // Hold result until ID stage is ready to accept it\n        // Note no state transition will occur if div_hold is set\n        md_state_d = MD_IDLE;\n        div_hold   = 1'b0;\n        div_valid   = 1'b1;\n      end\n      default: begin\n        md_state_d = MD_IDLE;\n      end\n    endcase // md_state_q\n  end\n  assign valid_o = mult_valid | div_valid;\n  // States must be knwon/valid.\nendmodule // cve2_mult\n", "mask_idx": {"conditional_statement": [[33798, 33877], [25681, 25918], [33720, 33887], [35610, 36682], [25494, 25918]], "blocking_assignment": [[31264, 31284], [31291, 31311], [35339, 35375], [36529, 36561], [35460, 35484], [35904, 35924], [31522, 31537], [35489, 35513]], "always_construct": [[33663, 33895], [31014, 33658], [25439, 25924], [35121, 39504]], "case_statement": [[35556, 39498], [31318, 33650]], "ansi_port_declaration": [[23935, 23967], [23806, 23846], [23316, 23393], [23074, 23152], [23675, 23716], [23849, 23887], [23719, 23760], [23396, 23432]], "continuous_assign": [[39507, 39547], [26191, 26232], [25927, 25982], [26034, 26097], [26493, 26570], [26139, 26188], [30798, 30907]], "parameter_declaration": [[16755, 16799], [16993, 17037], [13622, 13688], [16708, 16752], [16946, 16990], [16850, 16895], [16802, 16847], [13551, 13619], [13787, 13814]], "nonblocking_assignment": [[33836, 33865], [25838, 25869]]}, "all_mask_idx": {"module_program_interface_instantiation": [], "continuous_assign": [[25296, 25334], [25337, 25386], [25389, 25436], [25927, 25982], [26034, 26097], [26100, 26136], [26139, 26188], [26191, 26232], [26235, 26282], [26315, 26361], [26392, 26436], [26439, 26490], [26493, 26570], [27388, 27481], [27486, 27579], [27584, 27677], [27682, 27764], [27769, 27814], [27819, 27869], [27874, 27916], [27921, 27967], [27972, 28018], [28133, 28160], [28165, 28192], [28197, 28230], [28235, 28268], [28286, 28313], [28318, 28347], [28352, 28385], [28390, 28424], [28449, 28492], [28497, 28558], [30103, 30154], [30798, 30907], [30912, 30962], [30967, 31009], [33969, 34015], [34054, 34125], [34128, 34212], [34215, 34369], [34372, 34427], [34895, 34950], [34953, 35008], [35011, 35079], [35082, 35118], [39507, 39547]], "blocking_assignment": [[28634, 28656], [28663, 28683], [28690, 28717], [28724, 28750], [28757, 28798], [28805, 28837], [28844, 28876], [28936, 28991], [28998, 29021], [29028, 29048], [29055, 29072], [29184, 29204], [29217, 29235], [29248, 29268], [29306, 29323], [29399, 29421], [29432, 29454], [29465, 29492], [29503, 29530], [29541, 29561], [29572, 29586], [29597, 29614], [29625, 29657], [29668, 29688], [29699, 29717], [29728, 29745], [29791, 29811], [31038, 31066], [31073, 31101], [31108, 31128], [31135, 31155], [31162, 31192], [31199, 31222], [31229, 31257], [31264, 31284], [31291, 31311], [31394, 31419], [31430, 31455], [31466, 31483], [31494, 31511], [31522, 31537], [31548, 31568], [31579, 31599], [31665, 31690], [31701, 31727], [31738, 31755], [31766, 31808], [31898, 31941], [32000, 32056], [32120, 32140], [32165, 32185], [32251, 32277], [32288, 32313], [32324, 32366], [32377, 32394], [32453, 32499], [32512, 32571], [32584, 32604], [32688, 32708], [32721, 32741], [32779, 32809], [32822, 32845], [32858, 32878], [32988, 33014], [33025, 33051], [33062, 33104], [33115, 33157], [33168, 33206], [33217, 33272], [33357, 33380], [33391, 33411], [33491, 33511], [33522, 33542], [33588, 33608], [34769, 34814], [34840, 34878], [35143, 35183], [35188, 35222], [35227, 35260], [35265, 35295], [35300, 35334], [35339, 35375], [35380, 35415], [35420, 35455], [35460, 35484], [35489, 35513], [35518, 35551], [35904, 35924], [35977, 36033], [36182, 36215], [36529, 36561], [36614, 36670], [36723, 36758], [36767, 36802], [36811, 36836], [36897, 36918], [36950, 37002], [37011, 37038], [37047, 37071], [37106, 37140], [37149, 37183], [37245, 37293], [37325, 37378], [37387, 37414], [37423, 37448], [37483, 37518], [37527, 37562], [37602, 37680], [37689, 37727], [37736, 37798], [37827, 37903], [37912, 37996], [38221, 38260], [38386, 38432], [38473, 38550], [38559, 38644], [38653, 38681], [38728, 38752], [38806, 38880], [38914, 38988], [39064, 39099], [39108, 39157], [39325, 39346], [39355, 39373], [39382, 39401], [39441, 39462]], "nonblocking_assignment": [[25519, 25542], [25549, 25577], [25584, 25607], [25614, 25637], [25644, 25667], [25714, 25748], [25755, 25790], [25797, 25831], [25838, 25869], [25876, 25910], [29950, 29971], [30039, 30068], [33747, 33768], [33836, 33865]], "case_statement": [[29079, 29853], [31318, 33650], [35556, 39498]], "conditional_statement": [[25494, 25918], [25681, 25918], [29136, 29337], [29923, 30090], [30001, 30080], [31952, 32154], [32405, 32892], [33720, 33887], [33798, 33877], [34700, 34886], [35610, 36682], [38036, 38444], [38761, 39000]], "always_construct": [[25439, 25924], [28563, 29861], [29866, 30098], [31014, 33658], [33663, 33895], [34678, 34892], [35121, 39504]], "parameter_declaration": [[6471, 6520], [6523, 6571], [6594, 6628], [6631, 6665], [6668, 6702], [12379, 12461], [12464, 12546], [12570, 12622], [12625, 12677], [12680, 12733], [12736, 12789], [12792, 12845], [12848, 12901], [12925, 13002], [13044, 13089], [13092, 13137], [13140, 13186], [13189, 13235], [13238, 13284], [13332, 13380], [13383, 13431], [13434, 13482], [13551, 13619], [13622, 13688], [13787, 13814], [16708, 16752], [16755, 16799], [16802, 16847], [16850, 16895], [16898, 16943], [16946, 16990], [16993, 17037], [17040, 17096], [22941, 22996]], "ansi_port_declaration": [[23005, 23036], [23039, 23071], [23074, 23152], [23155, 23233], [23236, 23313], [23316, 23393], [23396, 23432], [23435, 23474], [23477, 23509], [23512, 23544], [23547, 23588], [23591, 23628], [23631, 23672], [23675, 23716], [23719, 23760], [23763, 23803], [23806, 23846], [23849, 23887], [23890, 23932], [23935, 23967]]}}