---
license: mit
pretty_name: x86-64 Instruction Test Vectors
tags:
- x86
- x86-64
- assembly
- instructions
- cpu
- test-vectors
- reverse-engineering
configs:
- config_name: 13th_Gen_Intel_R_Core_TM_i5_13600_f6m191s2
  data_files:
  - split: train
    path: data/13th_Gen_Intel_R_Core_TM_i5_13600_f6m191s2.parquet
- config_name: 13th_Gen_Intel_R_Core_TM_i7_13700K_f6m183s1
  data_files:
  - split: train
    path: data/13th_Gen_Intel_R_Core_TM_i7_13700K_f6m183s1.parquet
- config_name: 13th_Gen_Intel_R_Core_TM_i9_13900HK_f6m186s2
  data_files:
  - split: train
    path: data/13th_Gen_Intel_R_Core_TM_i9_13900HK_f6m186s2.parquet
- config_name: 13th_Gen_Intel_R_Core_TM_i9_13900KF_f6m183s1
  data_files:
  - split: train
    path: data/13th_Gen_Intel_R_Core_TM_i9_13900KF_f6m183s1.parquet
- config_name: AMD_Ryzen_5_3400G_with_Radeon_Vega_Graphics_f23m24s1
  data_files:
  - split: train
    path: data/AMD_Ryzen_5_3400G_with_Radeon_Vega_Graphics_f23m24s1.parquet
- config_name: AMD_Ryzen_5_3600_6_Core_Processor_f23m113s0
  data_files:
  - split: train
    path: data/AMD_Ryzen_5_3600_6_Core_Processor_f23m113s0.parquet
- config_name: AMD_Ryzen_7_5825U_with_Radeon_Graphics_f25m80s0
  data_files:
  - split: train
    path: data/AMD_Ryzen_7_5825U_with_Radeon_Graphics_f25m80s0.parquet
- config_name: AMD_Ryzen_7_8845HS_w_Radeon_780M_Graphics_f25m117s2
  data_files:
  - split: train
    path: data/AMD_Ryzen_7_8845HS_w_Radeon_780M_Graphics_f25m117s2.parquet
- config_name: AMD_Ryzen_9_9950X3D_16_Core_Processor_f26m68s0
  data_files:
  - split: train
    path: data/AMD_Ryzen_9_9950X3D_16_Core_Processor_f26m68s0.parquet
- config_name: Intel_R_Core_TM_i3_4170T_CPU_3_20GHz_f6m60s3
  data_files:
  - split: train
    path: data/Intel_R_Core_TM_i3_4170T_CPU_3_20GHz_f6m60s3.parquet
- config_name: Intel_R_Core_TM_i3_6100_CPU_3_70GHz_f6m94s3
  data_files:
  - split: train
    path: data/Intel_R_Core_TM_i3_6100_CPU_3_70GHz_f6m94s3.parquet
- config_name: Intel_R_Core_TM_i5_1035G4_CPU_1_10GHz_f6m126s5
  data_files:
  - split: train
    path: data/Intel_R_Core_TM_i5_1035G4_CPU_1_10GHz_f6m126s5.parquet
- config_name: Intel_R_Core_TM_i5_8600K_CPU_3_60GHz_f6m158s10
  data_files:
  - split: train
    path: data/Intel_R_Core_TM_i5_8600K_CPU_3_60GHz_f6m158s10.parquet
- config_name: Intel_R_Core_TM_i7_8700K_CPU_3_70GHz_f6m158s10
  data_files:
  - split: train
    path: data/Intel_R_Core_TM_i7_8700K_CPU_3_70GHz_f6m158s10.parquet
- config_name: Intel_R_Core_TM_i7_CPU_920_2_67GHz_f6m26s5
  data_files:
  - split: train
    path: data/Intel_R_Core_TM_i7_CPU_920_2_67GHz_f6m26s5.parquet
- config_name: Intel_R_Core_TM_i9_9900KF_CPU_3_60GHz_f6m158s13
  data_files:
  - split: train
    path: data/Intel_R_Core_TM_i9_9900KF_CPU_3_60GHz_f6m158s13.parquet
- config_name: Intel_R_Xeon_R_Silver_4416_f6m143s8
  data_files:
  - split: train
    path: data/Intel_R_Xeon_R_Silver_4416_f6m143s8.parquet
---

# x86-64 Instruction Test Vectors

Ground truth behavior of individual x86-64 instructions, captured by executing every encoding on real hardware and recording the resulting register and flag state. This is measured silicon behavior, not a model and not an emulator, so it also reflects implementation specific results such as the values an instruction leaves in flags that the architecture documents as undefined.

## How it was generated

Each test case is produced by the x86Tester tool. For a single instruction encoding it sets a known input register and flag state, runs the instruction inside a debugger harness (the Windows debug API on Windows, ptrace on Linux), and reads back the resulting state. Inputs are swept so that every reachable output bit is exercised.

Instructions execute at a fixed code base address of 0x04000001. Any address dependent result, for example a RIP relative lea, already has its computed output recorded in the outputs.

## Scope

Some instructions may be missing and coverage will be expanded over time.

Each CPU is stored as its own parquet file under `data/` and exposed as a separate config, named by the processor brand string together with its family, model and stepping, so results from different silicon never collide. Select a config to view a single processor.

## Data format

Each row is one test case: a single instruction encoding, executed from one known
input state, together with the resulting output state. An instruction with many
encodings (register variants, operand sizes, immediate forms) contributes many
rows, and each encoding is exercised from several input states chosen to drive its
reachable output bits to both `0` and `1`.

### Columns

- `address`: the code address the encoding executed at, as an unsigned integer. It
  is a fixed base for the whole run, so any address dependent result already has
  its output recorded.
- `asm`: full disassembly of the encoding.
- `mnemonic`: instruction mnemonic.
- `encoding`: instruction bytes as uppercase hex.
- `inputs`: JSON object, stored as a string, mapping each read location to its
  value before execution.
- `outputs`: JSON object, stored as a string, mapping each written location to its
  value after execution. Empty when the instruction faulted.
- `exception`: the fault that was raised, if any, for example `INT_DIVIDE_ERROR` or
  `INT_OVERFLOW`, otherwise null.

### Values

Every register, flag and memory value is hex of the raw little endian bytes, so the
first hex pair is the least significant byte. The width follows the location: a 64
bit register is 16 hex digits, a 32 bit register 8, an `xmm` register 32, and so on.

- `rax` = `0000000000000000` is `0`; `rax` = `EFCDAB8967452301` is
  `0x0123456789ABCDEF`.
- `flags` = `01000000` is `0x00000001`, the carry flag. Bit positions follow
  `EFLAGS`: CF bit 0, PF 2, AF 4, ZF 6, SF 7, DF 10, OF 11.

### Keys

Keys in `inputs` and `outputs` name what was read or written:

- Registers in Zydis spelling: `rax` .. `r15`, `xmm0` .. `xmm15`,
  `ymm0` .. `ymm15`, the x87 stack `st0` .. `st7`, and the x87 `x87status` and
  `x87control` words.
- `flags` for the `EFLAGS` register.
- `[<address>]` for a memory operand, where `<address>` is the effective address
  the instruction accessed, written in the same little endian hex form as any other
  value. The bytes stored under the key are what was read (in `inputs`) or written
  (in `outputs`); a read modify write operand appears in both. Instructions that
  touch memory (stack `push` / `pop` / `pushfq` / `popfq`, the string operations
  `stos` / `lods` / `scas` / `movs` / `cmps`, and instructions with an explicit
  memory operand) are run against a fixed scratch region, so a `[<address>]` key is
  a constant address inside that region for the run.

### Undefined flags

A flag the architecture leaves undefined is still fed as an input and recorded as an
output, so the data captures whether real silicon overwrites it or preserves it. The
recorded value is what the hardware actually produced, undefined bits included.

### Exceptions

When an encoding faults, `exception` names the fault (`INT_DIVIDE_ERROR`,
`INT_OVERFLOW`) and `outputs` is empty for that row.

### Examples

`push rax` reads `rax` and `rsp`, decrements `rsp`, and writes `rax` to the stack:

```json
inputs:  {"rax": "0000000000000000", "rsp": "8004000400000000"}
outputs: {"rsp": "7804000400000000", "[7804000400000000]": "0000000000000000"}
```

Here `rsp` goes from `0x0000000004000480` to `0x0000000004000478`, and the pushed
eight bytes land at `[0x0000000004000478]`.

`add [0x0000000004000480], al` adds `al` to a byte in memory and sets flags:

```json
inputs:  {"rax": "00CCCCCCCCCCCCCC", "flags": "95080000", "[8004000400000000]": "00"}
outputs: {"flags": "44000000", "[8004000400000000]": "00"}
```

`al` is `0x00`, the memory byte is `0x00`, so the sum is `0x00`, and the memory
operand appears in both `inputs` (read) and `outputs` (written).

## Source

Generated by [x86Tester](https://github.com/BinPrey/x86Tester).