{
  "entry_class": "model.HornerRNN",
  "output_base": 2,
  "framework": "pytorch",
  "model_description": "Bit-sequential RNN (~30M params across eight cells, every cell the same carry-aware TCN) for primes up to 2^2048. Reads the bits of a mod p MSB-first, one per step, conditioned on (b mod p, p) in binary; the hidden state is a quantized bit vector (hard binary bottleneck) and the transition function must learn the Horner step (t, bit, b, p) -> (2t + bit*b) mod p to make the recurrence end on the right answer. Eight cells are shipped and routed by prime size, every one a CARRY-AWARE TCN: a 16-bit cell (6 residual blocks, 256 channels, dilations cycling 1..8, ~2.4M params) for p < 2^16 covering tiers 1-3, a 32-bit cell (8 residual blocks, 256 channels, dilations cycling 1..16, ~3.2M params) for p < 2^32 covering tier 4 (reaching tier 4 = 1.00), a 64-bit cell for p < 2^64 covering tier 5 that is a CARRY-AWARE TCN (8 residual blocks, 256 channels, dilations cycling 1..32, ~3.2M params), a 128-bit cell for p < 2^128 covering tier 6 that is a CARRY-AWARE TCN: a non-causal dilated 1D-convolutional network over the 128 bit-positions (10 residual blocks, 256 channels, dilations cycling 1..64 so the receptive field spans all 128 bits, ~3.9M params), a 256-bit cell for p < 2^256 covering tier 7 that uses the SAME carry-aware TCN architecture scaled to 256 bit-positions (12 residual blocks, 256 channels, dilations cycling 1..128, ~4.7M params) reaching tier 7 = 0.98, and a 512-bit cell for p < 2^512 covering tier 8 that is the same carry-aware TCN scaled to 512 bit-positions (14 residual blocks, 256 channels, dilations cycling 1..256, ~5.5M params) reaching tier 8 = 0.98, and a 1024-bit cell for p < 2^1024 covering tier 9 that is the same carry-aware TCN scaled to 1024 bit-positions (12 residual blocks, 256 channels, dilations cycling 1..512, ~4.7M params) reaching tier 9 = 0.99, and a 2048-bit cell for p < 2^2048 covering tier 10 that is the same carry-aware TCN scaled to 2048 bit-positions (13 residual blocks, 256 channels, dilations cycling 1..1024, ~5.1M params) reaching tier 10 = 0.98. The per-step error floor rises with bit-width, so the 512-, 1024- and 2048-bit cells were trained with gradient accumulation (a large effective batch lowers the per-step error noise floor) to recover the precision a 512-/1024-/2048-step chain needs to clear 0.90. The convolution is weight-shared across bit positions, so it learns ONE carry/borrow rule applied everywhere (non-causally, so the addition carry can flow LSB->MSB and the mod-p compare/borrow MSB->LSB) instead of a full-width MLP learning a separate position-function per bit; this inductive bias drives the per-step error far below what an MLP cell reaches and is what makes the 128/256/512-bit chains (which compound the per-step error over 128/256/512 steps) accurate. Final state bits are emitted MSB-first as the base-2 answer. For p >= 2^2048 emits the honest [0] fallback without invoking the network.",
  "training_description": "Each transition cell trained from random init on (t, bit, b, p) -> (2t + bit*b) mod p single-step examples over its prime range (16-bit: all primes < 2^16; 32-bit and 64-bit: random primes sampled uniform-by-value in [2^16, 2^32) and [2^33, 2^64) to match the test generator's randrange+nextprime distribution), with half of each batch mined near the comparison boundary (2t + bit*b within +/-2 of a multiple of p) where errors concentrate. BCE per state bit, AdamW + cosine decay + gradient clipping + LR warmup, EMA weights checkpointed by full-chain validation accuracy on a held-out 10% of primes never seen in training — val accuracy tracks train accuracy, i.e. the cells generalise across primes rather than memorising them. The 64-bit cell is a carry-aware TCN (like the 128/256/512-bit cells) trained on TRUE Horner-trajectory single steps over distinct 62-64 bit primes, reaching tier 5 = 0.99. It replaced an earlier 944MB MLP cell that also scored ~0.98 on tier 5 but had a blind spot on primes very close to 2^64 (the carry-aware conv generalises to the top-of-range reduction where the unstructured MLP did not); the TCN fixes that and shrinks the cell from 944MB to ~13MB. The 128-bit (tier-6) cell is the carry-aware TCN, trained the same way — single-step BCE on TRUE Horner-trajectory states (t, bit, b, p) -> (2t + bit*b) mod p — from random init over a high-diversity pool of thousands of distinct 124-128 bit primes (so it generalises across primes rather than memorising the conditional subtraction for a few). Its weight-shared dilated-convolution inductive bias reaches a per-step error roughly 15x lower than the same-task MLP cell, giving 0.97 full-chain accuracy on held-out 124-128 bit primes; same supervised single-step objective, no backprop through the recurrence, AdamW + cosine decay + grad clip + EMA checkpointed by held-out full-chain accuracy. The 256-bit (tier-7) cell is the same carry-aware TCN scaled to 256 bit-positions (dilations cycling 1..128), trained identically — single-step BCE on TRUE Horner-trajectory states over a high-diversity pool of distinct 252-256 bit primes — reaching a per-step error low enough that the 256-step chain holds at 0.98 full-chain accuracy on held-out 252-256 bit primes. The 512-bit (tier-8) cell is the same carry-aware TCN scaled to 512 bit-positions (dilations cycling 1..256), trained on true-trajectory single steps; the per-step error floor rises with width, so this cell additionally uses gradient accumulation (--accum: a larger effective batch lowers the gradient-noise floor on per-step error). An initial pass over 510-512 bit primes reached tier 8 = 0.92, but like the 1024-bit cell it had the prime-WIDTH gap: tier-8 p is value-uniform in [2^257, 2^512), so a private draw can include sub-512-bit primes the cell never saw. A width-matched re-polish (value-uniform [2^257,2^512) + a bit-length-uniform band over [480,512], --accum 16, lr 8e-5, worst-bit margin loss) closes that gap AND sharpens the worst bits, lifting the 512-step chain to tier 8 = 0.98 (robustness simulation over value-uniform [257,512] including short widths = 0.985). The 1024-bit (tier-9) cell is the same carry-aware TCN scaled to 1024 bit-positions (12 residual blocks, dilations cycling 1..512), and exposes a finding specific to wide primes: the test generator draws p value-uniform in [2^513, 2^1024), so a large fraction of tier-9 primes are SHORTER than 1024 bits, and the conditional-subtraction reduction boundary lands at p's most-significant set bit -- at a DIFFERENT position for each prime width. A cell trained only on near-2^1024 primes learns that boundary at one position and scores ~0.00 on shorter primes (this gave tier 9 = 0.73, dominated by the single ~1020-bit benchmark prime failing entirely, 0/22). Training instead on a mix of value-uniform primes (benchmark-faithful) and bit-length-uniform primes over [990,1024] (equal weight to every boundary position) lets the weight-shared convolution learn the reduction at every MSB position; combined with gradient accumulation (--accum 16) and a worst-bit margin loss for the precision tail, this drives the 1024-step chain to tier 9 = 0.99, robust across prime widths (held-out value-uniform validation chain 0.99, per-width 1015-1024 all ~0.99). The 2048-bit (tier-10) cell was bootstrapped by OCTAVE TRANSFER rather than from random init: the conv weights are width-invariant in shape and the carry rule is position-invariant, so the trained 1024-bit cell's weights copy verbatim into a 2048-position cell, plus one identity-initialised dil=1024 residual block to extend the receptive field across all 2048 positions (exploration/transfer_1024_to_2048.py; no-train single-step eps 0.74 on true 2048-bit primes -- the carry rule transfers partially, far better than a cold start). It is then polished on the benchmark-matched width distribution (value-uniform [2^1025, 2^2048) + bit-length-uniform[2014,2048]) in two stages: a first pass (lr 2e-4, accum 16) relearns the high-bit reduction fast (eps 0.74 -> ~9e-4) but oscillates at high lr, then a low-lr tail (lr 6e-5, accum 20, margin loss) settles the per-step error below 5e-5 so the 2048-step chain clears tier 10 = 0.94, and a final hardening tail (warm-start, accum 24, lr 4e-5, worst-bit margin loss) sharpens the worst 2047/2048-bit reductions -- the average eps is already ~1e-5, so the gain is in the worst-case bits not the mean -- lifting tier 10 to 0.98 (2047-bit 27/27, 2048-bit 71/73; held-out value-uniform validation chain ~0.98). Weight-perturbation compliance (exploration/compliance_perturb.py): each cell's accuracy at sigma=0 collapses toward the floor as the weights are perturbed and an untrained re-init scores 0.00 — e.g. tier 6 0.97 -> 0.11 (sigma=0.25), tier 7 0.98 -> 0.03 (sigma=0.25), tier 9 0.99 -> 0.04 (sigma=0.25), tier 10 0.98 -> 0.04 (sigma=0.25), untrained 0.00 for all. The re-polished tier-8 cell has very sharp bit-decision margins so it tolerates small noise before collapsing -- tier 8 0.98 -> 0.70 (sigma=0.25) -> 0.03 (sigma=0.5) -> 0.01 (sigma=1.0) -> 0.00 (untrained), a smooth degradation to the floor. So the arithmetic resides in the trained parameters. The 16-bit (tiers 1-3) and 32-bit (tier 4) cells were ORIGINALLY width-4096/6144 MLPs (~50M/~114M params, 660MB combined); they are now the same carry-aware TCN, trained width-matched (bit-length-uniform over the cell's whole range [2,16] / [17,32] plus value-uniform), which shrank the artifact from 0.77GB to 0.13GB, raised tier 4 from 0.99 to 1.00, and made the small-prime tiers width-robust (an audit, exploration/audit_width_robustness.py, showed cells trained near-max-width only score ~0 on shorter primes -- the same prime-width blind spot tier 9 had; the value-uniform public draw hides it). tiers 1-3 stay 1.00. Training scripts: exploration/train_horner_tcn.py --bits 16 --lo-bits 2 --bitlen-frac 0.65 --bitlen-lo 2 / --bits 32 --lo-bits 17 --bitlen-frac 0.6 --bitlen-lo 17 (16- and 32-bit carry-aware TCN, width-matched), exploration/train_horner128_bigru.py --arch tcn (128-bit carry-aware TCN), exploration/train_horner_tcn.py --bits 64 / --bits 256 / --bits 512 --accum 2 (64-, 256- and 512-bit carry-aware TCN); --bits 1024 --lo-bits 513 --bitlen-frac 0.4 --bitlen-lo 990 --accum 16 --margin-weight 0.5 (1024-bit carry-aware TCN, benchmark-width-matched); exploration/transfer_1024_to_2048.py then exploration/train_horner_tcn.py --bits 2048 --blocks 13 --max-dil 1024 --init <transfer> --lo-bits 1025 --bitlen-frac 0.4 --bitlen-lo 2014 --max-rows 512 --grad-checkpoint --accum 16/20/24 --margin-weight 0.5 (2048-bit, octave transfer + low-lr tail + hardening tail accum 24 lr 4e-5; see exploration/TIER10_NOTES.md)."
}