---
base_model: Qwen/Qwen3.5-9B
library_name: peft
pipeline_tag: text-generation
tags:
- verilog
- rtl
- code-generation
- qwen3.5
- qwen
- lora
- peft
- qlora
- hardware
- verilog-eval
license: apache-2.0
---

# Verilog Qwen3.5-9B v33 Thinking-Reinforced LoRA

`adapter_v33_qwen35_thinking_compile_functional_reinforced` is a standard PEFT LoRA adapter for `Qwen/Qwen3.5-9B`, focused on Verilog RTL generation.

It fine-tunes from the v32 Qwen3.5 adapter, keeps brief reasoning/thinking behavior, and reinforces compile + functional correctness using detailed v32 failure analysis plus verified v9/v30b/v29 repairs.

## Important caveat

This is **not a clean zero-shot VerilogEval leaderboard model**. The dataset includes benchmark-targeted verified outputs and repair anchors from earlier adapters/pipelines. Treat the VerilogEval score as an experiment result, not as a contamination-free leaderboard claim.

LoRA weights from Qwen2.5-Coder were not transferred. This adapter was trained directly on Qwen3.5-9B, then continued from the v32 Qwen3.5 LoRA.

## Results

### VerilogEval v2 direct, spec-to-RTL, n=1, temperature 0

| Model / system | Compile | Functional pass |
|---|---:|---:|
| v9 prior Qwen2.5-Coder single adapter | — | 67/156 |
| v30b prior best Qwen2.5-Coder single adapter | 141/156 | 71/156 |
| v32 Qwen3.5 migration | 71/156 | 60/156 |
| v29 multi-adapter verifier selector | 150/156 | 84/156 |
| **v33 Qwen3.5 thinking-reinforced single adapter** | **101/156** | **76/156** |

v33 is the first Qwen3.5 single adapter in this project to beat v30b on VerilogEval direct functional pass:

```text
v32 -> v33: +30 compile, +16 pass
v30b -> v33: -40 compile, +5 pass
```

Compile rate is still lower than v30b, but v33 has more functional wins and stronger reasoning diversity.

## What changed from v32

v32 often failed because it reasoned at length but did not reliably finish with clean compileable Verilog. v33 keeps thinking, but trains a structured final-answer pattern:

```text
Thinking:
- exact interface checks
- category-specific pitfalls
- previous failure-specific warning
- final sanity check

[BEGIN]
<one complete synthesizable TopModule>
[DONE]
```

## Failure analysis used for training

v32 failure analysis summary:

```text
pass:                       60
no_module_or_extracted_junk:60
syntax_compile:             14
functional_mismatch:        11
duplicate_module_or_decl:    6
compile_error_other:         4
undeclared_or_bad_identifier:1
```

Category pass/compile showed especially weak seq/FSM/K-map compile stability, so v33 reinforces those with verified repairs and anchors.

## Training data mix

Dataset builder: `scripts/build_v33_qwen35_thinking_reinforce_dataset.py`

Unique source counts:

- 32 v32 failed-repair rows using verified v30b/v9/v29 solutions.
- 14 Qwen3.5 unique-win retention rows.
- 71 v30b pass anchors.
- 67 v9 pass anchors.
- 84 v29 selector pass anchors.
- 35 external/general rows.
- 493 clean verified rows.
- 316 synthetic verified rows.

Default repeat weights:

```text
v32 failed repair:        36x
v32 unique wins:          24x
v30b pass anchor:          8x
v9 pass anchor:            6x
v29 selector anchor:       3x
external verified:         8x
clean verified:            2x
synthetic verified:        1x
```

Training used `--drop-overlength`; overlength rows were dropped, not truncated.

## Training hyperparameters

```text
base model: Qwen/Qwen3.5-9B
base adapter: adapter_v32_qwen35_9b_verilog_general
method: QLoRA/LoRA continuation
LoRA r: 32
LoRA alpha: 64
learning rate: 8e-6
epochs: 0.50
max length: 1536
batch size: 1
grad accum: 4
warmup steps: 30
```

## Usage

Qwen3.5 uses a conditional-generation loader in the current Transformers stack.

```python
import torch
from transformers import AutoTokenizer, AutoModelForImageTextToText, BitsAndBytesConfig
from peft import PeftModel

base = "Qwen/Qwen3.5-9B"
adapter = "Pablo-Flores-Mollinedo/verilog-qwen3.5-9b-v33-thinking-reinforced-lora"

bnb = BitsAndBytesConfig(
    load_in_4bit=True,
    bnb_4bit_quant_type="nf4",
    bnb_4bit_compute_dtype=torch.bfloat16,
    bnb_4bit_use_double_quant=True,
)

tok = AutoTokenizer.from_pretrained(adapter, trust_remote_code=True)
model = AutoModelForImageTextToText.from_pretrained(
    base,
    quantization_config=bnb,
    device_map="auto",
    trust_remote_code=True,
)
model = PeftModel.from_pretrained(model, adapter)
model.eval()

prompt = "Write module TopModule(input a, input b, output out); out should be a & b."
messages = [
    {"role": "system", "content": "You are a Verilog RTL designer. You may reason briefly, then put only final compileable Verilog code inside [BEGIN]/[DONE]."},
    {"role": "user", "content": prompt},
]
text = tok.apply_chat_template(messages, tokenize=False, add_generation_prompt=True)
inputs = tok(text, return_tensors="pt").to(model.device)
with torch.no_grad():
    out = model.generate(**inputs, max_new_tokens=1024, do_sample=False, pad_token_id=tok.eos_token_id)
print(tok.decode(out[0][inputs["input_ids"].shape[-1]:], skip_special_tokens=True))
```

## Related artifacts

- v32 Qwen3.5 migration: earlier checkpoint, 60/156 pass.
- v30b Qwen2.5-Coder LoRA: prior best single adapter, 71/156 pass.
- v29 verifier selector: best practical pipeline, 84/156 pass.

## Intended use

Research and experimentation with Verilog RTL generation. Always compile, simulate, lint, and review generated RTL before use.