# Internal RTL Diagnostic-30 Suite

Internal RTL Diagnostic-30 is a local 30-task Verilog RTL diagnostic suite used by the project for regression testing and adapter sanity checks.

Purpose:
- internal evaluation and ablation checks;
- coverage across basic combinational logic, arithmetic, bit manipulation, sequential logic, FSMs, memory, and compile-heavy RTL blocks;
- local diagnostic comparison between project adapters.

Important caveat: this is not a public leaderboard benchmark and should not be treated as directly comparable to external adapter/model results unless prompts, harness, simulator version, extraction, and scoring protocol are matched.

Files:
- `internal_rtl_diagnostic_30.py`: benchmark harness with task prompts and testbenches.

Original project name was `paper_style_full`; it was renamed because the suite is an internal diagnostic benchmark, not only a paper-specific artifact.