Add external SOTA context charts

README.md

@@ -123,3 +123,63 @@ Typical reporting:
 - category breakdown for combinational, arithmetic, sequential, FSM, memory, and larger RTL designs
 
 This adapter has been evaluated on the full internal 30-task suite with both pass@1 and pass@5. Official external SOTA comparison should next run VerilogEval and RTLLM directly with the same decoding settings.
+
+
+## External SOTA context
+
+> Important: the following charts are **context only**, not official leaderboard placement. External results come from the public Chip Design LLM Zoo table, while this adapter's score is from this repository's internal 30-task paper-style suite. Benchmarks, prompts, decoding settings, and contamination controls differ.
+
+Sources:
+
+- Chip Design LLM Zoo reports VerilogEval, VerilogEval v2, RTLLM, and other RTL benchmark results and ranks models by VerilogEval pass@1 / RTLLM correct rate: https://iprc-dip.github.io/Chip-Design-LLM-Zoo/
+- NVIDIA's VerilogEval repository describes the VerilogEval harness and dataset: https://github.com/NVlabs/verilog-eval
+- The VerilogEval paper page describes a 156-problem Verilog generation benchmark: https://research.nvidia.com/publication/2023-09_verilogeval-evaluating-large-language-models-verilog-code-generation
+- RTL-Coder is an RTL-code-generation fine-tuning project with RTLCoder-Mistral inference scripts and synthetic RTL data flow: https://github.com/hkust-zhiyao/RTL-Coder
+
+### Reported top performers vs this adapter
+
+![External SOTA context](model_card_assets/external_sota_context.svg)
+
+### Reported fine-tuned/open Verilog models
+
+![Top fine-tuned context](model_card_assets/top_finetuned_context.svg)
+
+Representative reported models found in the public tables/search results include:
+
+| Model / method | Notes |
+|---|---|
+| ScaleRTL-32B / ScaleRTL†-32B | fine-tuned RTL model, strong VerilogEval reported scores |
+| ChipSeek-R1 | fine-tuned 7B RTL model, strong VerilogEval-Machine reported score |
+| CodeV-CodeLlama / CodeV-DeepSeek / CodeV-CodeQwen | fine-tuned 6.7B/7B RTL/code models |
+| DecoRTL-CodeV | RTL-specific model reported on VerilogEval-Human |
+| VeriReason-Qwen2.5-7B | fine-tuned Qwen2.5 7B RTL model |
+| RTL++ @ 200K Trained | fine-tuned 7B RTL model |
+| RTLCoder-Mistral | RTL-Coder project model family |
+| qwen3-32b-verilog-lora | Hugging Face Verilog LoRA adapter |
+
+### Why this comparison is cautious
+
+The current v4.1 adapter has been tested thoroughly on this repository's full internal suite:
+
+```text
+30 tasks total
+22 functional simulation tasks
+8 compile-only / RTL-heavy tasks
+pass@1 task pass: 83.33%
+pass@5 task pass: 86.67%
+```
+
+But it has **not yet** been run directly on official VerilogEval or RTLLM. Fair SOTA comparison requires running all candidate models with the same:
+
+```text
+benchmark version
+prompt formatting
+sampling temperature / k
+max tokens
+code extraction rules
+iverilog/vvp version
+timeout
+contamination policy
+```
+
+Next recommended step: run this adapter on official VerilogEval and RTLLM harnesses, then replace the context charts with direct apples-to-apples results.